KR102327330B1 - Soi웨이퍼의 제조방법 - Google Patents

Soi웨이퍼의 제조방법 Download PDF

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Publication number
KR102327330B1
KR102327330B1 KR1020177035353A KR20177035353A KR102327330B1 KR 102327330 B1 KR102327330 B1 KR 102327330B1 KR 1020177035353 A KR1020177035353 A KR 1020177035353A KR 20177035353 A KR20177035353 A KR 20177035353A KR 102327330 B1 KR102327330 B1 KR 102327330B1
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South Korea
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wafer
heat treatment
silicon
oxide film
soi
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Korean (ko)
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KR20180016394A (ko
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이사오 요코카와
히로지 아가
노리히로 코바야시
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신에쯔 한도타이 가부시키가이샤
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    • H01L21/76254—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H01L21/30604—
    • H01L21/324—
    • H01L21/76259—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Element Separation (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
KR1020177035353A 2015-06-15 2016-03-08 Soi웨이퍼의 제조방법 Active KR102327330B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2015120424A JP6380245B2 (ja) 2015-06-15 2015-06-15 Ｓｏｉウェーハの製造方法
JPJP-P-2015-120424 2015-06-15
PCT/JP2016/001235 WO2016203677A1 (ja) 2015-06-15 2016-03-08 Ｓｏｉウェーハの製造方法

Publications (2)

Publication Number Publication Date
KR20180016394A KR20180016394A (ko) 2018-02-14
KR102327330B1 true KR102327330B1 (ko) 2021-11-17

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KR1020177035353A Active KR102327330B1 (ko) 2015-06-15 2016-03-08 Soi웨이퍼의 제조방법

Country Status (8)

Country Link
US (1) US10204824B2 (https=)
EP (1) EP3309820B1 (https=)
JP (1) JP6380245B2 (https=)
KR (1) KR102327330B1 (https=)
CN (1) CN107615445B (https=)
SG (1) SG11201709420PA (https=)
TW (1) TWI685019B (https=)
WO (1) WO2016203677A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6473970B2 (ja) * 2015-10-28 2019-02-27 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
CN109037031B (zh) * 2018-07-11 2021-11-19 华东师范大学 一种掺镍氧化铜薄膜晶体管及制备方法
CN110739285A (zh) * 2019-10-30 2020-01-31 北京工业大学 硅基金属中间层化合物半导体晶圆的结构及制备方法
JP7354420B2 (ja) * 2020-04-02 2023-10-02 東京エレクトロン株式会社 基板処理方法及び基板処理装置
FR3110282B1 (fr) * 2020-05-18 2022-04-15 Soitec Silicon On Insulator Procédé de fabrication d’un substrat semi-conducteur sur isolant pour applications radiofréquences
KR102456461B1 (ko) 2020-11-26 2022-10-19 현대제철 주식회사 딥러닝을 이용한 철강 미세 조직 분석 방법 및 시스템
CN112582332A (zh) * 2020-12-08 2021-03-30 上海新昇半导体科技有限公司 一种绝缘体上硅结构及其方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2004071836A (ja) * 2002-08-06 2004-03-04 Sumitomo Mitsubishi Silicon Corp 半導体基板の製造方法
JP2006156858A (ja) * 2004-12-01 2006-06-15 Shin Etsu Chem Co Ltd 酸化膜付きシリコン基板の製造方法及び酸化膜付きシリコン基板
JP2007317988A (ja) 2006-05-29 2007-12-06 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
JP2009027124A (ja) * 2007-06-21 2009-02-05 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法
JP2009032972A (ja) 2007-07-27 2009-02-12 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
JP2011151267A (ja) 2010-01-22 2011-08-04 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
US20130078785A1 (en) 2004-12-28 2013-03-28 Commissariat A L' Energie Atomique Method for trimming a structure obtained by the assembly of two plates
JP2013153016A (ja) 2012-01-24 2013-08-08 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウェーハの製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH11307472A (ja) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP4304879B2 (ja) * 2001-04-06 2009-07-29 信越半導体株式会社 水素イオンまたは希ガスイオンの注入量の決定方法
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
JP2008028070A (ja) 2006-07-20 2008-02-07 Sumco Corp 貼り合わせウェーハの製造方法
JP5477277B2 (ja) * 2010-12-20 2014-04-23 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP5704039B2 (ja) * 2011-10-06 2015-04-22 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP2013143407A (ja) * 2012-01-06 2013-07-22 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウェーハの製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2004071836A (ja) * 2002-08-06 2004-03-04 Sumitomo Mitsubishi Silicon Corp 半導体基板の製造方法
JP2006156858A (ja) * 2004-12-01 2006-06-15 Shin Etsu Chem Co Ltd 酸化膜付きシリコン基板の製造方法及び酸化膜付きシリコン基板
US20130078785A1 (en) 2004-12-28 2013-03-28 Commissariat A L' Energie Atomique Method for trimming a structure obtained by the assembly of two plates
JP2007317988A (ja) 2006-05-29 2007-12-06 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
JP2009027124A (ja) * 2007-06-21 2009-02-05 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法
JP2009032972A (ja) 2007-07-27 2009-02-12 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
JP2011151267A (ja) 2010-01-22 2011-08-04 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
JP2013153016A (ja) 2012-01-24 2013-08-08 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウェーハの製造方法

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Publication number Publication date
CN107615445A (zh) 2018-01-19
EP3309820A4 (en) 2019-01-23
US20180144975A1 (en) 2018-05-24
KR20180016394A (ko) 2018-02-14
TW201643938A (zh) 2016-12-16
JP2017005201A (ja) 2017-01-05
WO2016203677A1 (ja) 2016-12-22
CN107615445B (zh) 2020-10-30
US10204824B2 (en) 2019-02-12
EP3309820B1 (en) 2020-01-29
TWI685019B (zh) 2020-02-11
JP6380245B2 (ja) 2018-08-29
EP3309820A1 (en) 2018-04-18
SG11201709420PA (en) 2017-12-28

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