WO2005067053A1 - Soiウェーハの作製方法 - Google Patents
Soiウェーハの作製方法 Download PDFInfo
- Publication number
- WO2005067053A1 WO2005067053A1 PCT/JP2004/019596 JP2004019596W WO2005067053A1 WO 2005067053 A1 WO2005067053 A1 WO 2005067053A1 JP 2004019596 W JP2004019596 W JP 2004019596W WO 2005067053 A1 WO2005067053 A1 WO 2005067053A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wafer
- soi
- soi wafer
- layer
- oxide film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04807951A EP1705704A4 (en) | 2004-01-08 | 2004-12-28 | PROCESS FOR PRODUCING SOI PLATEBOARD |
US10/585,522 US7358147B2 (en) | 2004-01-08 | 2004-12-28 | Process for producing SOI wafer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004003347A JP4285244B2 (ja) | 2004-01-08 | 2004-01-08 | Soiウェーハの作製方法 |
JP2004-003347 | 2004-01-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005067053A1 true WO2005067053A1 (ja) | 2005-07-21 |
Family
ID=34747073
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/019596 WO2005067053A1 (ja) | 2004-01-08 | 2004-12-28 | Soiウェーハの作製方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7358147B2 (ja) |
EP (1) | EP1705704A4 (ja) |
JP (1) | JP4285244B2 (ja) |
WO (1) | WO2005067053A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008004591A1 (fr) * | 2006-07-04 | 2008-01-10 | Sumco Corporation | Procédé de production d'une tranche liée |
JP2009260315A (ja) * | 2008-03-26 | 2009-11-05 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法及び半導体装置の作製方法 |
JP2009260314A (ja) * | 2008-03-26 | 2009-11-05 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法及び該soi基板を用いた半導体装置 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5082299B2 (ja) * | 2006-05-25 | 2012-11-28 | 株式会社Sumco | 半導体基板の製造方法 |
JP5433927B2 (ja) | 2007-03-14 | 2014-03-05 | 株式会社Sumco | 貼り合わせウェーハの製造方法 |
JP5183969B2 (ja) * | 2007-05-29 | 2013-04-17 | 信越半導体株式会社 | Soiウェーハのシリコン酸化膜形成方法 |
JP5466410B2 (ja) * | 2008-02-14 | 2014-04-09 | 信越化学工業株式会社 | Soi基板の表面処理方法 |
JP5478199B2 (ja) * | 2008-11-13 | 2014-04-23 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
US20120045883A1 (en) * | 2010-08-23 | 2012-02-23 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing soi substrate |
FR2987935B1 (fr) * | 2012-03-12 | 2016-07-22 | Soitec Silicon On Insulator | Procede d'amincissement de la couche active de silicium d'un substrat du type "silicium sur isolant" (soi). |
US8962224B2 (en) * | 2012-08-13 | 2015-02-24 | Applied Materials, Inc. | Methods for controlling defects for extreme ultraviolet lithography (EUVL) photomask substrate |
FR3007891B1 (fr) * | 2013-06-28 | 2016-11-25 | Soitec Silicon On Insulator | Procede de fabrication d'une structure composite |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003009386A1 (fr) * | 2001-07-17 | 2003-01-30 | Shin-Etsu Handotai Co.,Ltd. | Procede de production de plaquettes de liaison |
WO2003009366A1 (fr) * | 2001-07-16 | 2003-01-30 | S.O.I. Tec Silicon On Insulator Technologies | Procede d'amelioration de l'etat de surface d'une plaquette semiconductrice |
JP2003224247A (ja) * | 2002-01-29 | 2003-08-08 | Shin Etsu Handotai Co Ltd | Soiウエーハ及びsoiウエーハの製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH112848A (ja) | 1997-06-12 | 1999-01-06 | Mitsubishi Cable Ind Ltd | 分極反転結晶の製造方法 |
JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
FR2827078B1 (fr) * | 2001-07-04 | 2005-02-04 | Soitec Silicon On Insulator | Procede de diminution de rugosite de surface |
KR100511656B1 (ko) * | 2002-08-10 | 2005-09-07 | 주식회사 실트론 | 나노 에스오아이 웨이퍼의 제조방법 및 그에 따라 제조된나노 에스오아이 웨이퍼 |
JP4552858B2 (ja) * | 2003-09-08 | 2010-09-29 | 株式会社Sumco | 貼り合わせウェーハの製造方法 |
US7179719B2 (en) * | 2004-09-28 | 2007-02-20 | Sharp Laboratories Of America, Inc. | System and method for hydrogen exfoliation |
JP2006216826A (ja) * | 2005-02-04 | 2006-08-17 | Sumco Corp | Soiウェーハの製造方法 |
-
2004
- 2004-01-08 JP JP2004003347A patent/JP4285244B2/ja not_active Expired - Lifetime
- 2004-12-28 WO PCT/JP2004/019596 patent/WO2005067053A1/ja active Application Filing
- 2004-12-28 US US10/585,522 patent/US7358147B2/en active Active
- 2004-12-28 EP EP04807951A patent/EP1705704A4/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003009366A1 (fr) * | 2001-07-16 | 2003-01-30 | S.O.I. Tec Silicon On Insulator Technologies | Procede d'amelioration de l'etat de surface d'une plaquette semiconductrice |
WO2003009386A1 (fr) * | 2001-07-17 | 2003-01-30 | Shin-Etsu Handotai Co.,Ltd. | Procede de production de plaquettes de liaison |
JP2003224247A (ja) * | 2002-01-29 | 2003-08-08 | Shin Etsu Handotai Co Ltd | Soiウエーハ及びsoiウエーハの製造方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1705704A4 * |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008004591A1 (fr) * | 2006-07-04 | 2008-01-10 | Sumco Corporation | Procédé de production d'une tranche liée |
JP2008016534A (ja) * | 2006-07-04 | 2008-01-24 | Sumco Corp | 貼り合わせウェーハの製造方法 |
US8048769B2 (en) | 2006-07-04 | 2011-11-01 | Sumco Corporation | Method for producing bonded wafer |
JP2009260315A (ja) * | 2008-03-26 | 2009-11-05 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法及び半導体装置の作製方法 |
JP2009260314A (ja) * | 2008-03-26 | 2009-11-05 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法及び該soi基板を用いた半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US7358147B2 (en) | 2008-04-15 |
JP2005197524A (ja) | 2005-07-21 |
EP1705704A1 (en) | 2006-09-27 |
EP1705704A4 (en) | 2007-07-04 |
JP4285244B2 (ja) | 2009-06-24 |
US20070190737A1 (en) | 2007-08-16 |
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