WO2015136834A1 - 貼り合わせsoiウェーハの製造方法 - Google Patents
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- WO2015136834A1 WO2015136834A1 PCT/JP2015/000575 JP2015000575W WO2015136834A1 WO 2015136834 A1 WO2015136834 A1 WO 2015136834A1 JP 2015000575 W JP2015000575 W JP 2015000575W WO 2015136834 A1 WO2015136834 A1 WO 2015136834A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Definitions
- the present invention relates to a method for manufacturing a bonded SOI wafer using an ion implantation separation method.
- ion implantation separation method a technique also called a smart cut method (registered trademark)
- an oxide film is formed on at least one of two silicon wafers, and gas ions such as hydrogen ions or rare gas ions are implanted from the upper surface of one silicon wafer (bond wafer), A microbubble layer (encapsulation layer) is formed inside the wafer.
- the surface into which the ions are implanted is brought into close contact with the other silicon wafer (base wafer) through an oxide film, and then a heat treatment (peeling heat treatment) is applied to form one microwafer layer as a cleavage plane to form one wafer (bond wafer).
- a heat treatment peeling heat treatment
- bonding heat treatment is applied to firmly bond to form an SOI wafer (see Patent Document 1).
- an SOI wafer having a good mirror surface as a cleavage plane (peeling surface) and high uniformity in the thickness of the SOI layer can be obtained relatively easily.
- a flattening process for improving the surface roughness by performing a high-temperature heat treatment instead of the touch polish has been performed.
- a heat treatment in a reducing atmosphere containing hydrogen rapid thermal annealing (RTA: Rapid Thermal Annealing)
- RTA Rapid Thermal Annealing
- Patent Document 3 after the peeling heat treatment (or after the bonding heat treatment), after forming an oxide film on the SOI layer by heat treatment in an oxidizing atmosphere, the oxide film is removed, and then heat treatment in a reducing atmosphere (rapid heat treatment) Heating / rapid cooling heat treatment (RTA treatment) is described.
- rapid heat treatment Heating / rapid cooling heat treatment
- the SOI wafer after peeling is subjected to sacrificial oxidation treatment after planarization heat treatment in an inert gas, hydrogen gas, or mixed gas atmosphere thereof, thereby planarizing the peeled surface and OSF. Avoidance at the same time.
- a flattening process for improving the surface roughness by performing a high-temperature heat treatment instead of the touch polish is performed, and at present, the film thickness range of the SOI layer with a diameter of 300 mm (maximum in the plane).
- An SOI wafer having excellent film thickness uniformity of 3 nm or less obtained by subtracting the minimum value from the value is obtained at the mass production level by the ion implantation delamination method.
- the uniformity of the SOI layer film thickness distribution can be achieved by a method in which ion implantation is performed in multiple stages, or an oxidation treatment after peeling the SOI layer in addition to the multiple stages in ion implantation.
- a method of offsetting the SOI layer film thickness distribution due to the implantation depth and the in-plane machining allowance due to oxidation by performing temperature-fall oxidation (method of growing an oxide film during temperature drop) This has been achieved (see Patent Document 5).
- Patent Document 6 describes performing heat treatment at a temperature of 1000 ° C. or higher in an atmosphere of hydrogen gas, argon gas, or a mixed gas thereof as a process for reducing the thickness of the buried oxide film of the SOI wafer. Yes.
- the in-plane uniformity of the BOX film thickness a thin BOX type thin film SOI wafer was prototyped and the in-process transition of the in-plane film thickness range of the SOI layer was investigated. It was found that the in-plane distribution of the BOX film thickness deteriorates during heat treatment in a reducing atmosphere. Regarding the deterioration of the BOX film thickness distribution due to the reducing atmosphere, the in-plane film thickness distribution is different because the reducing action when oxygen is reduced from SiO 2 in the BOX film and the BOX film thickness is reduced differs in the plane. By forming.
- the factors that cause the in-plane distribution of the BOX film thickness due to the reducing action of the BOX film thickness include the temperature distribution in the surface during the temperature increase and decrease during the reducing heat treatment process and the high temperature holding, Depending on the distribution of the atmospheric pressure of the diffused oxygen, it can be mentioned that the batch type heat treatment furnace of the vertical furnace tends to have a concentric circular distribution.
- the present invention has been made in view of the above problems, and a method for manufacturing a bonded SOI wafer capable of suppressing variations in the in-plane distribution of the buried oxide film thickness caused by reducing heat treatment performed after the SOI layer is peeled off.
- the purpose is to provide.
- a silicon oxide film is formed on the surface of at least one of a bond wafer made of silicon single crystal and a base wafer by thermal oxidation, and hydrogen is formed on the surface of the bond wafer.
- the silicon oxide film is subjected to thermal oxidation at least during a temperature rise using a batch heat treatment furnace.
- the bonding after peeling is performed by performing the thermal oxidation treatment including any one of thermal oxidation during temperature reduction.
- the buried oxide film of the SOI wafer is formed so as to have a concentric oxide film thickness distribution, and further, the bonded SOI wafer after peeling of the bond wafer is subjected to a reducing heat treatment to thereby form the buried oxide film.
- a method for manufacturing a bonded SOI wafer wherein the thickness range is made smaller than the film thickness range before the reducing heat treatment.
- the buried oxide film thickness tends to have a concentric in-plane distribution. Therefore, by forming an in-plane distribution that offsets the in-plane distribution of the buried oxide film thickness formed by the reducing heat treatment in this way, a bonded SOI wafer with good uniformity can be obtained. You can definitely get it.
- the thickness range of the buried oxide film after the reducing heat treatment can be set to 1.0 nm or less. If it is the method of this invention, the SOI wafer which has such a favorable film thickness range can be obtained reliably.
- the reducing heat treatment can be performed in a 100% argon gas atmosphere, a 100% hydrogen gas atmosphere, or a mixed gas atmosphere thereof.
- the concentric oxide film thickness distribution can be formed into a concave distribution.
- the buried oxide film thickness distribution tends to be concentric convex, so that the buried oxide film thickness distribution is made concave in advance.
- the variation in film thickness distribution can be offset, and a bonded SOI wafer with a good uniformity of the buried oxide film can be obtained more reliably.
- the SOI wafer manufacturing method of the present invention can suppress variations in the in-plane distribution of the buried oxide film thickness caused by the reducing heat treatment performed after the SOI layer peeling.
- the present inventors have formed an in-plane distribution that offsets the in-plane distribution of the buried oxide thickness formed by the reducing heat treatment at the time of silicon oxide film formation, The inventors have conceived that a bonded SOI wafer with high uniformity of oxide film can be obtained reliably.
- the present inventors at the time of silicon oxide film formation, by performing a thermal oxidation treatment including at least one of thermal oxidation during temperature rise and thermal oxidation during temperature fall in a batch type heat treatment furnace, The inventors have conceived that the deterioration of the in-plane distribution formed by the reductive heat treatment can be offset, thereby completing the present invention.
- FIG. 1 shows a process flow diagram of a method for manufacturing a bonded SOI wafer of the present invention using an ion implantation delamination method.
- a mirror-polished silicon single crystal wafer is prepared as a bond wafer and a base wafer to be a support substrate.
- a silicon oxide film is formed on the bond wafer by thermal oxidation using a batch heat treatment furnace.
- This silicon oxide film may be formed only on the base wafer or on both wafers.
- the thermal oxidation treatment process for forming the silicon oxide film including at least one of the thermal oxidation during the temperature rise and the thermal oxidation during the temperature fall is performed.
- a silicon oxide film is formed so that the buried oxide film of the combined SOI wafer has a concentric oxide film thickness distribution.
- a convex oxide film thickness distribution is likely to be formed in the surface when thermal oxidation treatment is performed when the temperature is lowered. This is because the silicon single crystal wafer outer peripheral part is more likely to dissipate heat than the central part during the temperature drop of the batch heat treatment furnace, and the temperature is relatively low. Therefore, if the oxidation treatment is performed while the temperature is lowered, the in-plane distribution of the silicon oxide film (the BOX film after peeling) can be formed into a concentric convex shape.
- the size of the convex shape formed by the temperature drop oxidation is high when the temperature drop oxidation is performed, the temperature difference between the initial temperature and the end of oxidation is large, the temperature gradient is strong, and the gap between the upper surface wafer in the batch
- a concentric concave oxide film thickness distribution can be formed in-plane. This is because the temperature rises from the periphery of the wafer. Also at this time, as described above, a concave oxide film having a desired in-plane distribution can be obtained by appropriately selecting parameters such as temperature, temperature difference, temperature gradient, slot interval, etc. during temperature rising oxidation. . Also at this time, oxidation during isothermal holding may be combined as necessary.
- the concentric convex oxide film thickness distribution can be formed by performing only the temperature-lowering oxidation without performing the temperature-rising oxidation and combining the oxidation during the isothermal holding as necessary, and concentrically
- the concave oxide film thickness distribution can be formed by performing only temperature-raising oxidation without performing temperature-falling oxidation, and combining oxidation during isothermal holding as necessary. Further, if temperature rising oxidation and temperature falling oxidation are appropriately combined, an oxide film having a desired concentric film thickness distribution can be accurately formed.
- step (c) of FIG. 1 gas ions such as hydrogen ions and rare gas ions are implanted to form an ion implantation layer inside the bond wafer.
- the ion-implanted surface of the bond wafer and the surface of the base wafer are bonded together through a silicon oxide film.
- cleaning may be performed before bonding to both wafers.
- the bond wafer is peeled off with the ion implantation layer as a boundary, an embedded silicon oxide film and an SOI layer are formed on the base wafer, and a bonded SOI wafer is obtained.
- the damaged layer of the ion implantation layer may be removed by performing a sacrificial oxidation process (after the thermal oxidation, removing the formed thermal oxide film) after the peeling step (e). .
- step (f) of FIG. 1 heat treatment (reducing heat treatment) is performed in a reducing atmosphere.
- the reducing atmosphere of the present invention means an atmosphere in which oxygen is reduced from SiO 2 in the BOX by heat treatment and a phenomenon in which the BOX film thickness decreases occurs.
- 100% argon A gas atmosphere, a 100% hydrogen gas atmosphere, a mixed gas atmosphere thereof, or the like can be cited as a suitable example, but is not limited thereto.
- the heat treatment conditions at the time of BOX oxidation are as follows:
- the BOX oxide film thickness distribution after the reductive heat treatment can be made uniform by appropriately combining temperature rising oxidation and temperature falling oxidation.
- the BOX film thickness distribution after the reducing heat treatment usually tends to be a concentric convex shape, so the concentric oxide film thickness distribution of the silicon oxide film formed before bonding is concave. It is preferable to form in the distribution. In this way, a bonded SOI wafer having a highly uniform BOX film can be easily obtained.
- FIG. 2 shows the manufacturing method of the present invention in the case where the silicon oxide film is formed so that the BOX film thickness distribution after the peeling step (e) becomes concave in the thermal oxidation treatment step (b) before bonding.
- a silicon oxide film 11 having a concentric concave film thickness distribution is formed on the bond wafer 10 made of silicon single crystal.
- the description has been made on the assumption that the BOX film thickness distribution formed by the reductive heat treatment has a convex shape.
- a thermal oxidation treatment process is performed.
- the silicon oxide film 11 may be formed so that the BOX film thickness distribution after peeling becomes convex.
- the thickness range of the buried oxide film (BOX film) after the reductive heat treatment can be set to 1.0 nm or less.
- a BOX film thickness range of 1 nm or less which is required for a Thin BOX type thin film SOI wafer in recent years, is sufficiently satisfied, and further, 0.5 nm or less is satisfied.
- a high bonded SOI wafer can be obtained.
- a silicon oxide film (a silicon oxide film that becomes a BOX film after peeling) is formed only on a bond wafer made of a silicon single crystal having a diameter of 300 mm with a thickness of 30 nm (FIG. 1B), and then hydrogen ion implantation is performed (FIG. 1). 1 (c)).
- the silicon oxide film is formed by using a batch heat treatment furnace and introducing oxygen gas while raising the temperature from 900 ° C. to 950 ° C. and maintaining the isothermal temperature at 950 ° C., and then performing the dry oxidation temperature raising oxidation. It was.
- the temperature rising rate during temperature rising oxidation at 900 ° C. to 950 ° C. was set to 1 ° C./min. (Note that the temperature when the wafer was put into the oxidation furnace was 600 ° C., and the rate of temperature increase from 600 ° C. to 900 ° C.
- the in-plane distribution of the silicon oxide film after temperature-raising oxidation was 0.8 nm in the in-plane range, and the distribution was a concentric distribution with a concave shape whose outer peripheral part was thicker than the central part as shown in FIG. .
- the hydrogen ion implantation is divided into two divided implantations.
- the first implantation is H + , 30 keV, 2.6e16 cm ⁇ 2 , the implantation angle is 0 degree, and the notch orientation angle is 0 degree.
- the second implantation is H + , 30 keV, The injection was performed at 2.6e16 cm ⁇ 2 , an injection angle of 0 degree, and a notch orientation angle of 90 degrees.
- reducing heat treatment was performed in a 100% Ar atmosphere at 1200 ° C. for 1 hour ((f) in FIG. 1).
- the BOX film thickness after the reducing heat treatment is reduced to 25 nm, and the in-plane distribution of the BOX film thickness is improved to 0.4 nm as compared with the film thickness range: 0.4 nm before the reducing heat treatment, as shown in FIG. A bonded SOI wafer with high uniformity was obtained.
- a pyrogenic oxidation treatment at 950 ° C. is performed to form a 400 nm thermal oxide film (sacrificial oxide film), and then the formed thermal oxide film is removed with a 10% HF aqueous solution to obtain 10 nm ( ⁇ 0.5 nm). ) SOI layer was produced.
- the BOX film thickness after removal of the sacrificial oxide film (after thinning) was a bonded SOI wafer with high uniformity of the BOX film as well as after the reducing heat treatment.
- a bonded SOI wafer was produced under the same conditions as in the example except that the bond wafer was oxidized at a constant temperature of 950 ° C. as in the prior art.
- the in-plane distribution of the silicon oxide film 111 on the surface of the bond wafer 110 was uniform.
- the in-plane distribution of the silicon oxide film 111 was 0.2 nm in the in-plane range.
- the temperature of the wafer input into the thermal oxidation furnace is 600 ° C.
- the rate of temperature increase from 600 ° C. to 950 ° C. is 5 ° C./min
- oxygen gas is introduced after reaching 950 ° C., and dry at a constant temperature. Oxidation was performed.
- the in-plane distribution of the film thickness of the BOX film 113 was worse than that before the reductive heat treatment with a film thickness range: 1.1 nm, as shown in FIG.
- a concentric convex in-plane distribution was obtained.
- a pyrogenic oxidation treatment at 950 ° C. is performed to form a 400 nm thermal oxide film (sacrificial oxide film), and then the formed thermal oxide film is removed with a 10% HF aqueous solution to obtain 10 nm ( ⁇ 0.5 nm). ) SOI layer was produced.
- the film thickness range of the BOX film at this time also exceeded 1 nm.
- Table 1 shows the silicon oxide film formation conditions, ion implantation separation conditions, reducing thermal oxidation treatment conditions, sacrificial oxidation treatment conditions, and results of the above examples and comparative examples.
- the BOX film thickness distribution was less than 0.5 nm in the film thickness range, and a good in-plane distribution was obtained, whereas in the comparative example, the film thickness was 1.1 nm and the recent BOX film thickness range was 1 nm or less. It was found that an in-plane distribution that satisfies the requirements could not be obtained.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.
Abstract
Description
この方法では、劈開面(剥離面)は良好な鏡面となり、SOI層の膜厚の均一性も高いSOIウェーハが比較的容易に得られる。
例えば、特許文献2では、剥離熱処理後又は結合熱処理後に、SOI層の表面を研磨することなく、水素を含む還元性雰囲気下の熱処理(急速加熱・急速冷却熱処理(RTA:Rapid Thermal Annealing))を加えることが記載されている。
このように、タッチポリッシュの代わりに高温熱処理を行って表面粗さを改善する平坦化処理が行われるようになったことによって、現在では、直径300mmでSOI層の膜厚レンジ(面内の最大値から最小値を引いた値)が3nm以下の優れた膜厚均一性を有するSOIウェーハが、イオン注入剥離法によって量産レベルで得られている。
本発明の方法であれば、確実にこのような良好な膜厚レンジを有するSOIウェーハを得ることができる。
本発明の方法において、上記のガス雰囲気下で還元性熱処理を実施することが好適である。
ボンドウェーハの剥離後の貼り合わせSOIウェーハの還元性熱処理において、埋め込み酸化膜の膜厚分布は同心円状の凸形状になりやすいため、予め、埋め込み酸化膜の膜厚分布を凹形状としておくことで膜厚分布のバラツキを相殺でき、埋め込み酸化膜の均一性が良好な貼り合わせSOIウェーハをより確実に得ることができる。
そこで、本発明者等は鋭意検討を重ねた結果、還元性熱処理によって形成される埋め込み酸化膜厚の面内分布を相殺するような面内分布を、シリコン酸化膜形成時に形成することで、埋め込み酸化膜の均一性が高い貼り合わせSOIウェーハを確実に得られることに想到した。
本発明におけるSOIウェーハを製造する方法は、イオン注入剥離法を用いる。図1は、イオン注入剥離法を用いた本発明の貼り合わせSOIウェーハの製造方法の工程フロー図を示す。
まず、図1の工程(a)では、ボンドウェーハと支持基板となるベースウェーハとして例えば鏡面研磨されたシリコン単結晶ウェーハを用意する。
本発明において、このシリコン酸化膜を形成する熱酸化処理工程では、少なくとも昇温中での熱酸化と降温中での熱酸化のいずれか一方を含む熱酸化処理を行うことで、剥離後の貼り合わせSOIウェーハの埋め込み酸化膜が同心円形状の酸化膜厚分布となるようにシリコン酸化膜を形成する。
なお、貼り合わせる前に、ウェーハの表面に付着しているパーティクルおよび有機物を除去するため、両ウェーハに貼り合わせ前に洗浄を行ってもよい。
また図1には記載していないが、剥離工程(e)の後に犠牲酸化処理(熱酸化後、形成した熱酸化膜を除去)等を行い、イオン注入層のダメージ層を除去しても良い。
このようにすれば、均一性の高いBOX膜を有する貼り合わせSOIウェーハを容易に得られる。
この場合、図2の(b)に示すように、シリコン単結晶からなるボンドウェーハ10に同心円状の凹形状の膜厚分布を有するシリコン酸化膜11が形成される。
そして、図2の(e)で得られた貼り合わせSOIウェーハ15に還元性熱処理工程(f)を施すと、この還元性熱処理で形成されるはずの凸形状のBOX膜厚分布が、予め形成されている凹形状のBOX膜厚分布により相殺され、還元性熱処理による均一性の悪化を抑制することができる。その結果、図2の(f)に示すように、BOX膜の均一性が高い貼り合わせSOIウェーハを得ることができる。
このような製造方法であれば、近年、Thin BOX型の薄膜SOIウェーハに要求されているBOX膜厚レンジ1nm以下を十分に満たし、更には、0.5nm以下をも満たした、より均一性の高い貼り合わせSOIウェーハを得ることができる。
直径300mmのシリコン単結晶からなるボンドウェーハのみにシリコン酸化膜(剥離後にBOX膜となるシリコン酸化膜)を厚さ30nmで作製後(図1の(b))、水素イオン注入を行った(図1の(c))。
昇温酸化後のシリコン酸化膜の面内分布は面内レンジで0.8nm、分布は、図2の(b)のように、外周部が中心部より厚い凹形状の同心円形状分布であった。
その後、900℃のパイロジェニック酸化処理を行って剥離面に250nmの熱酸化膜(犠牲酸化膜)を形成した後、形成された酸化膜を10%HF水溶液で除去することによって、イオン注入のダメージ層を除去した。
還元性熱処理後のBOX膜厚は25nmまで薄膜化され、BOX膜厚面内分布は膜厚レンジ:0.4nmと還元性熱処理前よりも改善され、図2の(f)のようなBOX膜の均一性が高い貼り合わせSOIウェーハを得た。
従来のように一定温度950℃によるボンドウェーハの酸化を行ったこと以外、実施例と同様な条件で貼り合わせSOIウェーハを作製した。
このとき、図3の(b)に示すように、ボンドウェーハ110表面のシリコン酸化膜111の面内分布は均一な分布であった。また、シリコン酸化膜111の面内分布は面内レンジで0.2nmであった。(尚、熱酸化処理炉へのウェーハ投入温度は600℃で、600℃~950℃の昇温レートは5℃/minとし、950℃に達した後に酸素ガスを導入して、一定温度でドライ酸化を行った。)
更にその後、950℃のパイロジェニック酸化処理を行って400nmの熱酸化膜(犠牲酸化膜)を形成した後、形成された熱酸化膜を10%HF水溶液で除去して、10nm(±0.5nm)のSOI層を作製した。
このときのBOX膜の膜厚レンジも1nmを超えてしまっていた。
Claims (4)
- シリコン単結晶からなるボンドウェーハとベースウェーハの少なくとも一方のウェーハの表面にシリコン酸化膜を熱酸化処理により形成し、該ボンドウェーハの表面に水素イオン、希ガスイオンの少なくとも一種類のガスイオンをイオン注入してイオン注入層を形成し、該ボンドウェーハのイオン注入した表面と前記ベースウェーハの表面とを、前記シリコン酸化膜を介して貼り合わせた後、前記イオン注入層で前記ボンドウェーハを剥離することにより貼り合わせSOIウェーハを製造する方法において、
前記シリコン酸化膜を、バッチ式熱処理炉を使用して、少なくとも昇温中での熱酸化と降温中での熱酸化のいずれか一方を含む前記熱酸化処理を行うことにより、剥離後の前記貼り合わせSOIウェーハの埋め込み酸化膜が同心円形状の酸化膜厚分布となるように形成し、
さらに、前記ボンドウェーハの剥離後の前記貼り合わせSOIウェーハに還元性熱処理を行うことにより、前記埋め込み酸化膜の膜厚レンジを前記還元性熱処理前の膜厚レンジよりも小さくすることを特徴とする貼り合わせSOIウェーハの製造方法。 - 前記還元性熱処理後の前記埋め込み酸化膜の膜厚レンジを1.0nm以下にすることを特徴とする請求項1に記載の貼り合わせSOIウェーハの製造方法。
- 前記還元性熱処理を100%アルゴンガス雰囲気又は100%水素ガス雰囲気、あるいはこれらの混合ガス雰囲気下で行うことを特徴とする請求項1又は請求項2に記載の貼り合わせSOIウェーハの製造方法。
- 前記同心円形状の酸化膜厚分布を凹形状の分布に形成することを特徴とする請求項1から請求項3のいずれか1項に記載の貼り合わせSOIウェーハの製造方法。
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