SG11201606965QA - Method for manufacturing bonded soi wafer - Google Patents

Method for manufacturing bonded soi wafer

Info

Publication number
SG11201606965QA
SG11201606965QA SG11201606965QA SG11201606965QA SG11201606965QA SG 11201606965Q A SG11201606965Q A SG 11201606965QA SG 11201606965Q A SG11201606965Q A SG 11201606965QA SG 11201606965Q A SG11201606965Q A SG 11201606965QA SG 11201606965Q A SG11201606965Q A SG 11201606965QA
Authority
SG
Singapore
Prior art keywords
soi wafer
bonded soi
manufacturing bonded
manufacturing
wafer
Prior art date
Application number
SG11201606965QA
Inventor
Hiroji Aga
Norihiro Kobayashi
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of SG11201606965QA publication Critical patent/SG11201606965QA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
SG11201606965QA 2014-03-10 2015-02-09 Method for manufacturing bonded soi wafer SG11201606965QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014046098A JP6107709B2 (en) 2014-03-10 2014-03-10 Manufacturing method of bonded SOI wafer
PCT/JP2015/000575 WO2015136834A1 (en) 2014-03-10 2015-02-09 Process for producing bonded soi wafer

Publications (1)

Publication Number Publication Date
SG11201606965QA true SG11201606965QA (en) 2016-10-28

Family

ID=54071297

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201606965QA SG11201606965QA (en) 2014-03-10 2015-02-09 Method for manufacturing bonded soi wafer

Country Status (8)

Country Link
US (1) US9793154B2 (en)
EP (1) EP3118889B1 (en)
JP (1) JP6107709B2 (en)
KR (1) KR102173455B1 (en)
CN (1) CN106062923B (en)
SG (1) SG11201606965QA (en)
TW (1) TWI573173B (en)
WO (1) WO2015136834A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
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FR3034565B1 (en) * 2015-03-30 2017-03-31 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A STRUCTURE HAVING A BIT DIELECTRIC LAYER OF UNIFORM THICKNESS
JP6686962B2 (en) * 2017-04-25 2020-04-22 信越半導体株式会社 Method for manufacturing bonded wafer
JP6747386B2 (en) * 2017-06-23 2020-08-26 信越半導体株式会社 Method for manufacturing SOI wafer
JP6760245B2 (en) * 2017-11-06 2020-09-23 信越半導体株式会社 Method for manufacturing an SOI wafer having a thin film SOI layer
CN110184655B (en) * 2019-04-25 2022-01-11 上海新傲科技股份有限公司 Surface oxidation method of wafer
CN110349843B (en) * 2019-07-26 2021-12-21 京东方科技集团股份有限公司 Thin film transistor, preparation method thereof, biological recognition device and display device
CN111446165A (en) * 2020-04-16 2020-07-24 绍兴同芯成集成电路有限公司 Wafer heat treatment process and wafer double-side electroplating process

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FR2681472B1 (en) 1991-09-18 1993-10-29 Commissariat Energie Atomique PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL.
JP3293736B2 (en) * 1996-02-28 2002-06-17 キヤノン株式会社 Semiconductor substrate manufacturing method and bonded substrate
JPH08274285A (en) 1995-03-29 1996-10-18 Komatsu Electron Metals Co Ltd Soi substrate and manufacture thereof
JPH11307472A (en) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd Soi wafer and manufacture soi by hydrogen ion releasing method
JP2000124092A (en) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd Manufacture of soi wafer by hydrogen-ion implantation stripping method and soi wafer manufactured thereby
WO2003009386A1 (en) 2001-07-17 2003-01-30 Shin-Etsu Handotai Co.,Ltd. Method for producing bonding wafer
US7759254B2 (en) * 2003-08-25 2010-07-20 Panasonic Corporation Method for forming impurity-introduced layer, method for cleaning object to be processed apparatus for introducing impurity and method for producing device
US7563697B2 (en) * 2003-09-05 2009-07-21 Sumco Corporation Method for producing SOI wafer
US20070069335A1 (en) 2003-09-08 2007-03-29 Akihiko Endo Bonded wafer and its manufacturing method
EP1710836A4 (en) * 2004-01-30 2010-08-18 Sumco Corp Method for manufacturing soi wafer
KR101111436B1 (en) 2004-09-13 2012-02-15 신에쯔 한도타이 가부시키가이샤 Soi wafer manufacturing method and soi wafer
DE102004062356A1 (en) * 2004-12-23 2006-07-13 Siltronic Ag Semiconductor wafer with a semiconductor layer and an underlying electrically insulating layer and method for their preparation
JP2007149723A (en) * 2005-11-24 2007-06-14 Sumco Corp Process for manufacturing laminated wafer
US7598153B2 (en) * 2006-03-31 2009-10-06 Silicon Genesis Corporation Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species
KR101440930B1 (en) * 2007-04-20 2014-09-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method of manufacturing soi substrate
JP5135935B2 (en) * 2007-07-27 2013-02-06 信越半導体株式会社 Manufacturing method of bonded wafer
JP5493345B2 (en) * 2008-12-11 2014-05-14 信越半導体株式会社 Manufacturing method of SOI wafer
JP2010153488A (en) * 2008-12-24 2010-07-08 Rohm Co Ltd Manufacturing method of soi wafer, and soi wafer
JP5310004B2 (en) * 2009-01-07 2013-10-09 信越半導体株式会社 Manufacturing method of bonded wafer
FR2941324B1 (en) * 2009-01-22 2011-04-29 Soitec Silicon On Insulator PROCESS FOR DISSOLVING THE OXIDE LAYER IN THE CROWN OF A SEMICONDUCTOR TYPE STRUCTURE ON AN INSULATION
FR2944645B1 (en) * 2009-04-21 2011-09-16 Soitec Silicon On Insulator METHOD FOR SLITTING A SILICON SUBSTRATE ON INSULATION
JP5927894B2 (en) 2011-12-15 2016-06-01 信越半導体株式会社 Manufacturing method of SOI wafer

Also Published As

Publication number Publication date
EP3118889A1 (en) 2017-01-18
WO2015136834A1 (en) 2015-09-17
US20160372363A1 (en) 2016-12-22
KR20160132017A (en) 2016-11-16
US9793154B2 (en) 2017-10-17
JP6107709B2 (en) 2017-04-05
TW201546873A (en) 2015-12-16
CN106062923A (en) 2016-10-26
TWI573173B (en) 2017-03-01
KR102173455B1 (en) 2020-11-03
EP3118889B1 (en) 2019-09-25
EP3118889A4 (en) 2017-10-18
CN106062923B (en) 2019-05-17
JP2015170796A (en) 2015-09-28

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