CN111446165A - Wafer heat treatment process and wafer double-side electroplating process - Google Patents
Wafer heat treatment process and wafer double-side electroplating process Download PDFInfo
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- CN111446165A CN111446165A CN202010300797.2A CN202010300797A CN111446165A CN 111446165 A CN111446165 A CN 111446165A CN 202010300797 A CN202010300797 A CN 202010300797A CN 111446165 A CN111446165 A CN 111446165A
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000010438 heat treatment Methods 0.000 title claims abstract description 39
- 238000009713 electroplating Methods 0.000 title claims abstract description 27
- 239000011521 glass Substances 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000000227 grinding Methods 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 239000007767 bonding agent Substances 0.000 claims abstract description 7
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 239000000956 alloy Substances 0.000 claims abstract description 4
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 4
- 238000007747 plating Methods 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 9
- 229910001873 dinitrogen Inorganic materials 0.000 claims 1
- 238000005498 polishing Methods 0.000 claims 1
- 238000005452 bending Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 100
- 239000007789 gas Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000005342 ion exchange Methods 0.000 description 1
- 150000002500 ions Chemical group 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02697—Forming conducting materials on a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
The invention discloses a wafer heat treatment process and a wafer double-side electroplating process, and belongs to the field of wafer processing. A wafer heat treatment process comprises the following steps: bonding one end face of the wafer and the glass carrying plate together; grinding the other end face of the wafer to thin the wafer; etching the middle part of the wafer to enable the wafer to be thin in the center and thick at the edge; sequentially carrying out yellow light and ion implantation processes on the other end face of the wafer; bonding the glass carrier plate by laser or resistance heating or ultraviolet irradiation, and cleaning to remove the bonding agent; and carrying out a heat treatment process to form the ohmic contact resistance of the alloy. Compared with the prior art, the wafer double-side electroplating and heat treatment process can effectively avoid the bending deformation of the wafer in the heat treatment process or the double-side electroplating process.
Description
Technical Field
The invention relates to the field of wafer processing, in particular to a wafer heat treatment process and a wafer double-side electroplating process.
Background
In the existing chip production process of power devices of MOSFET and IGBT and 3-D devices, in order to produce and manufacture ultrathin wafers, the wafers and a glass carrier plate need to be bonded together, and the wafers are carried on the glass carrier plate, so that the wafers are convenient to process and transmit; or the Taico Wafer (Taico Wafer) is used for thinning the Wafer, and the processes of photoetching pattern, etching, ion implantation, annealing, metal deposition and the like can be carried out after the back surface of the Wafer is thinned.
In the process of bonding the glass carrier, the glass carrier can be thinned, but the double-sided electroplating process cannot be continuously carried out, and the heat treatment process cannot be carried out due to the fact that the glass carrier is not high-temperature resistant.
In the drum process, the wafer does not need to be bonded with a glass carrier plate, but after the wafer is thinned, the wafer is easily deformed and bent by heat and is easily broken in the heat treatment process, so that after the drum process is completed, the bent edge of the wafer is often required to be removed, and material loss is caused. On the other hand, when performing metal deposition (evaporation/sputtering/plating/electroless plating), the wafer also requires special jigs and carriers. Especially in the chemical liquid tank type of the current electroplating equipment, the design of the batch multi-piece type clamp, because the thin wafer is easy to shake or even break due to the plating liquid in the tank and the need of a specific circulating flow field for homogenizing the metal ion density of the plating liquid.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a wafer heat treatment process and a wafer double-sided electroplating process, which can carry out double-sided electroplating and avoid edge deformation in the heat treatment process.
The purpose of the invention can be realized by the following technical scheme:
a wafer heat treatment process comprises the following steps:
bonding one end face of the wafer and the glass carrying plate together;
grinding the other end face of the wafer to thin the wafer;
etching the middle part of the wafer to enable the wafer to be thin in the center and thick at the edge;
sequentially carrying out yellow light and ion implantation processes on the other end face of the wafer;
bonding the glass carrier plate by laser or resistance heating or ultraviolet irradiation, and cleaning to remove the bonding agent;
and carrying out a heat treatment process to form the ohmic contact resistance of the alloy.
Further, after etching, the shape of the wafer is a step shape or a slope shape.
Furthermore, after etching, the thickness of the thinnest part of the wafer is 20-100 microns.
Further, in the heat treatment process, the wafer is placed in a furnace tube device, and is heated after nitrogen is introduced.
Furthermore, the thickness of the glass carrier plate is 400-700 microns.
Furthermore, after the wafer is ground, the thickness of the thickest part of the wafer is 200-400 microns.
A wafer double-sided electroplating process comprises the following steps:
bonding one end face of the wafer and the glass carrying plate together;
grinding the other end face of the wafer to thin the wafer;
etching the middle part of the wafer to enable the wafer to be thin in the center and thick at the edge;
sequentially carrying out yellow light and ion implantation processes on the other end face of the wafer;
bonding the glass carrier plate by laser or resistance heating or ultraviolet irradiation, and cleaning to remove the bonding agent;
and carrying out a double-sided electroplating process.
The invention has the beneficial effects that:
in the double-sided electroplating process of the wafer, the wafer with a thin center and thick edges is obtained firstly, after bonding is released, the wafer can be directly taken down from the glass carrier plate for double-sided electroplating and heat treatment, and the deformation resistance of the wafer is enhanced due to the thick edges, so that the bending deformation in the heat treatment is avoided.
Drawings
The invention will be further described with reference to the accompanying drawings.
Fig. 1 is a schematic structural view of a bonded glass carrier and a wafer according to the present application;
FIG. 2 is a schematic view of a wafer heating method according to an embodiment of the present disclosure;
FIG. 3 is a schematic view of a wafer heating method according to another embodiment of the present application;
FIG. 4 is a schematic view of a wafer heating method according to another embodiment of the present application;
FIG. 5 is a schematic illustration of electroless plating in the present application;
FIG. 6 is a schematic illustration of electroplating in the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "opening," "upper," "lower," "thickness," "top," "middle," "length," "inner," "peripheral," and the like are used in an orientation or positional relationship that is merely for convenience in describing and simplifying the description, and do not indicate or imply that the referenced component or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the present invention.
As shown in fig. 1, a heat treatment process for a wafer 1 includes the following steps:
bonding an end face of the wafer 1 and the glass carrier 2 together, wherein the thickness of the glass carrier 2 is 400-700 μm. And grinding the other end face of the wafer 1 to thin the wafer 1, wherein the thickest part of the wafer 1 is 200-400 microns after thinning. The wafer 1 is then etched to make the wafer 1 have a thin center and a thick edge, wherein the specific shape of the wafer 1 can be, but is not limited to, a step shape or a slope shape, and the thickness of the thinnest portion of the wafer 1 is 20-100 μm. And then, the other end face of the wafer 1 is subjected to yellow light and ion implantation processes in sequence.
Bonding the glass carrier plate 2 by laser or resistance heating or ultraviolet irradiation, and cleaning to remove the bonding agent; finally, heat treatment process is carried out to form the ohmic contact resistance of the alloy.
Through the above process, the wafer 1 with a thin center and a thick edge is obtained by grinding and etching. After debonding, the wafer 1 may be directly fed into a thermal processing apparatus. Because the edge is thick and the thickness is kept between 200 and 400, the wafer 1 has better deformation resistance, and the deformation of the wafer 1 is smaller after heat treatment, so that the bending deformation is avoided after the heat treatment.
For thermal processing, the wafer may be heated by thermal conduction, thermal radiation, and thermal convection. Specifically, the heating Process may be a furnace heating Process, an RTP (Rapid Thermal Process), or a resistance heating Process. More specifically, as shown in fig. 2, in an embodiment of the present invention, the wafer 1 is placed on the support 3 of the furnace apparatus, and the wafer 1 is held by clamping or supporting the edge portion of the wafer 1. Then, high-heat gas is introduced into the equipment to form convection in the equipment, so that the wafer 1 is heated. And such a high heat gas does not chemically react with the wafer 1, such as nitrogen.
As shown in fig. 3, in another embodiment of the present invention, a wafer 1 is clamped and fixed by a clamp, the wafer 1 is sealed around by a protective cover 4 made of transparent material, and a gas which does not react with the wafer, such as nitrogen, is introduced into the protective cover 4. Then, the wafer 1 is irradiated by ultraviolet light to heat the wafer 1 by heat radiation.
In yet another embodiment of the present invention, as shown in fig. 4, the wafer 1 is also clamped by a clamp, the wafer 1 is placed on the resistance wire 5, the wafer 1 is sealed around by the protective cover 4, and a gas which does not react with the wafer 1, such as nitrogen, is introduced into the protective cover 4. Then, the wafer 1 is contacted by the heating wire 5, and the wafer 1 is heated.
In addition, the invention also provides a wafer double-side electroplating process, which comprises the following specific steps.
Firstly, an end face of a wafer 1 is bonded with a glass carrier 2, wherein the thickness of the glass carrier 2 is 400-700 μm. And grinding the other end face of the wafer 1 to thin the wafer 1, wherein the thickest part of the wafer 1 is 200-400 microns after thinning. The wafer 1 is then etched to make the wafer 1 have a thin center and a thick edge, wherein the specific shape of the wafer 1 can be, but is not limited to, a step shape or a slope shape, and the thickness of the thinnest portion of the wafer 1 is 20-100 μm. And then, the other end face of the wafer 1 is subjected to yellow light and ion implantation processes in sequence.
And (3) debonding and bonding the glass carrier plate 2 by laser or resistance heating or ultraviolet irradiation, and cleaning to remove the bonding agent.
And finally, carrying out a double-sided metal plating process, specifically, putting the wafer 1 into a process tank of electroplating equipment, and carrying out the metal plating process on two sides of the wafer 1, wherein the specific mode can be electroplating or chemical plating. In the chemical plating process, as shown in fig. 5, the clamp 3 is required to clamp the thicker edge portion, and put into the chemical plating solution, and the upper metal layer of the wafer 1 is ion exchanged with the chemical plating solution, so that the metal ions in the chemical plating solution are deposited on the metal layer of the wafer 1, thereby performing the chemical plating on the wafer 1.
In the electroplating process, as shown in fig. 6, the clamp 3 provided with the electrode 7 clamps the thicker part of the edge of the wafer 1, the electrolyte 6 is added, and when the power is on, the current in the electroplating device carries out ion exchange through the contact point and the copper seed layer of the wafer 1, so that the anode target material 8 is ion-electroplated on the seed layer, and the electroplating of the wafer 1 is carried out.
In the chemical plating and electroplating process, the process has the advantage that double-sided chemical plating and electroplating can be performed due to the fact that the edge of the wafer 1 is thick and good in rigidity. The wafer 1 is not easily broken in the clamping and transferring process or in the specific circulating flow field of the electroplating solution 6, and the risk of breaking the wafer 1 in electroplating can be effectively reduced without bonding the glass carrier plate 2.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (7)
1. A wafer heat treatment process is characterized by comprising the following steps:
bonding one end face of the wafer and the glass carrying plate together;
grinding the other end face of the wafer to thin the wafer;
etching the middle part of the wafer to enable the wafer to be thin in the center and thick at the edge;
sequentially carrying out yellow light and ion implantation processes on the other end face of the wafer;
bonding the glass carrier plate by laser or resistance heating or ultraviolet irradiation, and cleaning to remove the bonding agent;
and carrying out a heat treatment process to form the ohmic contact resistance of the alloy.
2. The wafer thermal processing process according to claim 1, wherein the wafer has a stepped or sloped shape after etching.
3. The heat treatment process for the wafer as claimed in claim 1, wherein the thinnest part of the wafer after etching has a thickness of 20-100 μm.
4. The wafer heat treatment process as claimed in claim 1, wherein the wafer is placed in a furnace apparatus, and is heated after nitrogen gas is introduced.
5. The wafer thermal processing process according to claim 1, wherein the glass carrier has a thickness of 400 to 700 μm.
6. The wafer thermal processing process of claim 1, wherein the wafer has a thickness of 200-400 μm at the thickest part after polishing.
7. A wafer double-sided electroplating process is characterized by comprising the following steps:
bonding one end face of the wafer and the glass carrying plate together;
grinding the other end face of the wafer to thin the wafer;
etching the middle part of the wafer to enable the wafer to be thin in the center and thick at the edge;
sequentially carrying out yellow light and ion implantation processes on the other end face of the wafer;
bonding the glass carrier plate by laser or resistance heating or ultraviolet irradiation, and cleaning to remove the bonding agent;
and carrying out double-sided electroplating or chemical plating process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010300797.2A CN111446165A (en) | 2020-04-16 | 2020-04-16 | Wafer heat treatment process and wafer double-side electroplating process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010300797.2A CN111446165A (en) | 2020-04-16 | 2020-04-16 | Wafer heat treatment process and wafer double-side electroplating process |
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| CN111446165A true CN111446165A (en) | 2020-07-24 |
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| CN202010300797.2A Pending CN111446165A (en) | 2020-04-16 | 2020-04-16 | Wafer heat treatment process and wafer double-side electroplating process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113149449A (en) * | 2021-03-10 | 2021-07-23 | 凯盛科技股份有限公司 | Preparation method of large-size flexible glass |
| CN116092929A (en) * | 2023-02-16 | 2023-05-09 | 浙江萃锦半导体有限公司 | Double-sided wafer chemical plating process |
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|---|---|---|---|---|
| US20140051224A1 (en) * | 2012-08-14 | 2014-02-20 | Shanghai Hua Hong Nec Electronics Co., Ltd. | Method of back-side patterning |
| CN105225996A (en) * | 2015-09-18 | 2016-01-06 | 江苏中科君芯科技有限公司 | There is the IGBT device back process of diode-built-in |
| CN106062923A (en) * | 2014-03-10 | 2016-10-26 | 信越半导体株式会社 | Process for producing bonded soi wafer |
| US20180061695A1 (en) * | 2016-08-31 | 2018-03-01 | Infineon Technologies Ag | Method for processing a wafer and method for processing a carrier |
| CN109712926A (en) * | 2017-10-25 | 2019-05-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
-
2020
- 2020-04-16 CN CN202010300797.2A patent/CN111446165A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140051224A1 (en) * | 2012-08-14 | 2014-02-20 | Shanghai Hua Hong Nec Electronics Co., Ltd. | Method of back-side patterning |
| CN106062923A (en) * | 2014-03-10 | 2016-10-26 | 信越半导体株式会社 | Process for producing bonded soi wafer |
| CN105225996A (en) * | 2015-09-18 | 2016-01-06 | 江苏中科君芯科技有限公司 | There is the IGBT device back process of diode-built-in |
| US20180061695A1 (en) * | 2016-08-31 | 2018-03-01 | Infineon Technologies Ag | Method for processing a wafer and method for processing a carrier |
| CN109712926A (en) * | 2017-10-25 | 2019-05-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113149449A (en) * | 2021-03-10 | 2021-07-23 | 凯盛科技股份有限公司 | Preparation method of large-size flexible glass |
| CN116092929A (en) * | 2023-02-16 | 2023-05-09 | 浙江萃锦半导体有限公司 | Double-sided wafer chemical plating process |
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Application publication date: 20200724 |