WO2009142077A1 - Process for fabricating semiconductor device - Google Patents
Process for fabricating semiconductor device Download PDFInfo
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- WO2009142077A1 WO2009142077A1 PCT/JP2009/057522 JP2009057522W WO2009142077A1 WO 2009142077 A1 WO2009142077 A1 WO 2009142077A1 JP 2009057522 W JP2009057522 W JP 2009057522W WO 2009142077 A1 WO2009142077 A1 WO 2009142077A1
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- Prior art keywords
- film
- semiconductor device
- metal film
- electrode
- manufacturing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 233
- 238000000034 method Methods 0.000 title claims abstract description 97
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 184
- 239000000758 substrate Substances 0.000 claims abstract description 146
- 238000007747 plating Methods 0.000 claims abstract description 102
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 90
- 239000010936 titanium Substances 0.000 claims abstract description 37
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 35
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 claims abstract description 29
- 239000010931 gold Substances 0.000 claims abstract description 26
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052737 gold Inorganic materials 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims description 109
- 239000002184 metal Substances 0.000 claims description 109
- 238000004519 manufacturing process Methods 0.000 claims description 71
- 229910052782 aluminium Inorganic materials 0.000 claims description 53
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 53
- 229910000679 solder Inorganic materials 0.000 claims description 34
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 claims description 28
- 238000007772 electroless plating Methods 0.000 claims description 24
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 10
- 229910052725 zinc Inorganic materials 0.000 claims description 10
- 239000011701 zinc Substances 0.000 claims description 10
- 230000001681 protective effect Effects 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 230000004913 activation Effects 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 19
- 238000004544 sputter deposition Methods 0.000 abstract description 6
- 238000000151 deposition Methods 0.000 abstract description 5
- 238000006467 substitution reaction Methods 0.000 abstract description 5
- 238000000227 grinding Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000007781 pre-processing Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 37
- 238000006073 displacement reaction Methods 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 10
- 239000000243 solution Substances 0.000 description 8
- 239000002344 surface layer Substances 0.000 description 8
- 230000035882 stress Effects 0.000 description 7
- 239000002585 base Substances 0.000 description 6
- 238000010030 laminating Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 229910000990 Ni alloy Inorganic materials 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 241000209094 Oryza Species 0.000 description 2
- 235000007164 Oryza sativa Nutrition 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 240000007320 Pinus strobus Species 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- -1 and subsequently Substances 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005238 degreasing Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 235000009566 rice Nutrition 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000006479 redox reaction Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Images
Classifications
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1646—Characteristics of the product obtained
- C23C18/165—Multilayered product
- C23C18/1651—Two or more layers only obtained by electroless plating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/18—Pretreatment of the material to be coated
- C23C18/1851—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material
- C23C18/1872—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material by chemical pretreatment
- C23C18/1886—Multistep pretreatment
- C23C18/1889—Multistep pretreatment with use of metal first
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/31—Coating with metals
- C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/54—Contact plating, i.e. electroless electrochemical plating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
- C23C28/02—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
- C23C28/023—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material only coatings of metal elements only
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
- C23C28/02—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
- C23C28/023—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material only coatings of metal elements only
- C23C28/025—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material only coatings of metal elements only with at least one zinc-based layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Definitions
- the present invention relates to a method for manufacturing a semiconductor device, and more particularly to a power semiconductor device used for a power conversion device or the like, and manufacturing a semiconductor device having a thickness of 80 to 200 ⁇ m having electrodes on the front surface and the back surface of the semiconductor device. Regarding the method.
- An IGBT which is one of power semiconductor devices, is a one-chip device having high-speed switching characteristics and voltage driving characteristics of MOSFETs (insulated gate type field effect transistors) and low on-voltage characteristics of bipolar transistors. It is a power device.
- the range of applications has expanded from industrial fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS), or switching power supplies to consumer equipment fields such as microwave ovens, rice cookers, and strobes. Further, IGBTs having a lower on-voltage using a new chip structure have been developed, and reductions in the loss and efficiency of application devices using the IGBT have been achieved.
- IGBT has structures such as punch-through (hereinafter referred to as PT), non-punch-through (hereinafter referred to as NPT), and field stop (hereinafter referred to as FS) types, except for some applications.
- PT punch-through
- NPT non-punch-through
- FS field stop
- An n-channel vertical double diffusion structure is the mainstream. Therefore, in this specification, an n-channel IGBT is described as an example, but the same applies to a p-channel IGBT.
- the PT-type IGBT is formed using an epitaxial substrate obtained by epitaxially growing an n + buffer layer and an n ⁇ active layer on a p + semiconductor substrate. Therefore, for example, in a semiconductor device having a withstand voltage of 600 V, an active layer thickness of about 100 ⁇ m is sufficient, but the total thickness including the p + semiconductor substrate portion is as thick as about 200 to 300 ⁇ m. Further, since an epitaxial substrate is used, the cost is increased.
- NPT type and FS type IGBTs have been developed in which the cost is reduced by using an FZ substrate cut out from a semiconductor ingot manufactured by a floating zone (FZ) method instead of an epitaxial substrate.
- FZ floating zone
- a shallow p + collector layer (low implantation p + collector) with a low dose is formed on the back surface of the semiconductor device.
- FIG. 11 is a cross-sectional view showing a configuration of an NPT type IGBT manufactured using an FZ substrate.
- an n ⁇ semiconductor substrate 1 made of an FZ substrate is used as an active layer, and a p + base region 2 and an n + emitter region 3 are selectively formed on the surface layer.
- a gate electrode 5 is formed on the surface of the n ⁇ semiconductor substrate 1 via a gate oxide film 4.
- Emitter electrode 6 is in contact with n + emitter region 3 and p + base region 2 and is insulated from gate electrode 5 by interlayer insulating film 7.
- a p + collector layer 8 and a collector electrode 9 are formed on the back surface of the n ⁇ semiconductor substrate 1.
- the total thickness of the NPT type IGBT is significantly thinner than that of the PT type IGBT. Since the NPT type IGBT can control the injection rate of holes, high-speed switching is possible without performing lifetime control. In addition, the NPT type IGBT is inexpensive because an FZ substrate is used instead of an epitaxial substrate.
- FIG. 12 is a cross-sectional view showing the configuration of the FS type IGBT.
- the surface structure of the semiconductor substrate is the same as that of the NPT type IGBT shown in FIG. the n - the back surface of semiconductor substrate 1, the n - between the semiconductor substrate 1 and the p + collector layer 8, n buffer layer 10 is provided.
- the FS type IGBT by using the FZ substrate, the total thickness of the substrate becomes 80 to 200 ⁇ m.
- n is an active layer - in order to deplete the semiconductor substrate 1, a semiconductor device 600V breakdown voltage, n - the thickness of the semiconductor substrate 1 is about 100 [mu] m.
- the surface structure of the device is fabricated on the front surface of the semiconductor substrate. Thereafter, back grinding is performed on the back surface of the semiconductor substrate to thin the semiconductor substrate. Subsequently, two types of ions are sequentially implanted into the back surface of the thinned semiconductor substrate and an activation heat treatment is performed, whereby the buffer layer 10 and the collector layer 8 are formed on the back surface of the semiconductor substrate. Then, a collector electrode 9 is formed by depositing or sputtering a metal such as aluminum (Al) on the surface of the collector layer 8.
- a metal such as aluminum (Al)
- the following method has been proposed as a method for manufacturing the semiconductor device as described above.
- the surface structure of the element is formed on the first main surface side of the silicon substrate, the second main surface is ground to thin the substrate, and then the buffer layer and the collector layer are formed on the second main surface side.
- an aluminum silicon film having a thickness of 0.3 ⁇ m or more and 1.0 ⁇ m or less and a silicon concentration of 0.5 wt% or more and 2 wt% or less, preferably 1 wt% or less is formed on the surface of the collector layer.
- a plurality of metals such as titanium, nickel and gold are formed by vapor deposition or sputtering to form a collector electrode.
- the titanium film, nickel film, and gold film are a buffer metal film, a solder joint metal film, and a protective metal film, respectively (see, for example, Patent Document 1 below).
- the aluminum silicon film is formed for the purpose of preventing aluminum spikes.
- the titanium film is formed to prevent nickel diffusion during solder mounting, and the nickel film is formed to solder the back collector electrode.
- the gold film is formed to prevent oxidation of the nickel film.
- the back electrode is joined using solder.
- the front surface electrode formed on the front surface of the semiconductor device is mainly bonded using a wire bonding technique using an aluminum wire, but recently, the front surface electrode is also used. Solder bonding may be used.
- An E heat sink is joined to the surface of each semiconductor chip by solder, a second conductor member is joined to the back surface by solder, and a third conductor member is joined to the surface of the E heat sink by solder.
- the E heat sink is provided with a step portion to form a thin portion, and the bonding area between the E heat sink and the third conductor member is smaller than the bonding area between the E heat sink and each semiconductor chip.
- Each member is resin-sealed with the back surface of the second conductor member and the surface of the third conductor member exposed (see, for example, Patent Document 2 below).
- a semiconductor element As another device, a semiconductor element, a first metal body bonded to the back surface of the semiconductor element and serving as an electrode and heat dissipation, and a second metal body bonded to the surface side of the semiconductor element and serving as an electrode and heat dissipation And a third metal body joined between the surface of the semiconductor element and the second metal body, wherein a shear stress of the surface of the semiconductor element is obtained in a semiconductor device in which almost the entire device is molded with resin.
- the thickness of the semiconductor element is reduced and the entire apparatus is constrained and held by the mold resin so as to reduce a distortion component or the like in a bonding layer that joins the semiconductor element and the metal body.
- a semiconductor device in which the bonding layer is made of Sn-based solder has been proposed (for example, see Patent Document 3 below).
- the plating method an electroplating method or an electroless plating method is generally used.
- the electroplating method is a method for reducing and depositing metal ions in a solution by supplying an external current.
- the electroless plating method is a method in which metal ions in a solution are chemically reduced and deposited without using electricity. Therefore, it is possible to simplify the manufacturing apparatus and the manufacturing process by performing the plating process using the electroless plating method, rather than using the electroplating method that requires an electric circuit such as a counter electrode or a DC power source.
- the adhesion between the front electrode and the plating film can be improved by performing a zincate treatment on the surface of the front electrode.
- the reason is that when the electroless nickel plating is performed on a material having a remarkably low redox potential such as aluminum or magnesium, the plated surface needs to be activated.
- the zincate process is disclosed in, for example, Patent Document 4 below.
- an electroless plating reaction may occur on the back and side surfaces of the semiconductor substrate that are not activated with respect to the electroless plating solution, and nickel may be precipitated abnormally. .
- the concentration of nickel in the plating solution decreases, and it becomes difficult to control the thickness of the plating film.
- a zinc substitution film is deposited on the pad electrode by a zinc substitution method, then washed with pure water, and then a counter electrode is made of a stainless steel rod plated with nickel, and the substrate to be plated with the counter electrode as a negative electrode
- a redox-type electroless nickel plating solution By immersing in a redox-type electroless nickel plating solution while applying a minute positive potential to the semiconductor substrate, it is possible to apply a plating resist on the back and side surfaces of the semiconductor substrate on a plurality of pad electrodes.
- a protruding electrode with an electroless nickel plating film having a uniform thickness can be obtained (for example, see Patent Document 5 below).
- the second surface electrode and the second back electrode are simultaneously formed on the surfaces of the first surface electrode and the first back electrode by a wet plating method.
- Ni is plated on the front and back surfaces of the wafer at the same time.
- the second front electrode is formed on the wafer front side
- the second back electrode is formed on the wafer back side.
- wet plating is simultaneously performed on the front and back surfaces of the wafer to form a plating layer. That is, for example, an Au plating layer is formed on the surface of the second surface electrode and the surface of the second back electrode (see, for example, Patent Document 6 below).
- an aluminum silicon (AlSi) film 11 is formed as a back electrode on the back surface of the semiconductor substrate 1.
- an etching process is performed on the back surface of the semiconductor substrate 1 to form irregularities on the surface of the aluminum silicon film 11.
- the nickel (Ni) plating film 14 and the replacement gold (Au) plating film are formed on the surface of the aluminum silicon film 11 on the back surface of the semiconductor substrate 1.
- 15 are formed in this order.
- a collector electrode 9 (see FIG. 12) formed by laminating the aluminum silicon film 11, the nickel (Ni) plating film 14, and the displacement gold (Au) plating film 15 is formed.
- the aluminum silicon film 11 formed as the back electrode is formed at about 300 to 500 ° C. as in the formation of the front surface electrode. No heat treatment is performed. Therefore, the aluminum silicon film 11 has poor crystallinity and a sparse film quality.
- the etching process is performed on the aluminum silicon film 11 in this state, the surface of the aluminum silicon film 11 is uneven so as to reach the semiconductor substrate 1 as shown in FIG. Therefore, the nickel plating film 14 formed on the surface of the aluminum silicon film 11 and the semiconductor substrate 1 come into contact with each other.
- silicon (Si) which is a component of the semiconductor substrate 1 and nickel which is a component of the nickel plating film 14 have low adhesion. Therefore, as shown in FIG. 15, the collector electrode 9 is easily separated from the semiconductor substrate 1 at the boundary between the back electrode (aluminum silicon film 11) and the semiconductor substrate 1.
- the present invention suppresses the warpage of the semiconductor substrate by canceling the stress of the plating film on both sides of the semiconductor substrate in the method of forming the plating film on both the front and back surfaces of the semiconductor substrate.
- An object of the present invention is to provide a method for manufacturing a semiconductor device.
- Another object of the present invention is to provide a method for manufacturing a semiconductor device in which a metal film laminated as an electrode is difficult to peel off when the semiconductor device is mounted by solder bonding.
- a method for manufacturing a semiconductor device has the following characteristics.
- the second electrode is used as the back electrode.
- a step of forming a first metal film on the surface of the main surface is performed.
- a step of forming a second metal film on the surface of the first metal film as the back electrode is performed.
- a step of simultaneously forming a plating film on the surface electrode and the surface of the second metal film is performed by a wet plating method.
- a method for manufacturing a semiconductor device wherein the surface of the second main surface is used as the back electrode before the first metal film is formed. Forming a metal film containing aluminum as a main component.
- a method for manufacturing a semiconductor device according to the first aspect wherein the first metal film is insoluble in a processing solution capable of dissolving the second metal film. It is characterized by being.
- a method for manufacturing a semiconductor device wherein a solder bonding metal film is formed on the surface of the second metal film as the plating film, and the solder A protective metal film is formed on the surface of the bonding metal film.
- the method for manufacturing a semiconductor device according to the fourth aspect, wherein the second metal film is a film mainly composed of the same material as the solder-bonded metal film.
- the semiconductor device manufacturing method according to the invention of claim 6 is characterized in that, in the invention of claim 4, the second metal film is a nickel film.
- the semiconductor device manufacturing method according to the invention of claim 7 is characterized in that, in the invention of claim 4, the second metal film is a film containing aluminum as a main component.
- the semiconductor device manufacturing method according to the invention of claim 8 is characterized in that, in the invention of claim 4, the second metal film is an aluminum film.
- the method for manufacturing a semiconductor device according to the invention of claim 9 is characterized in that, in the invention of claim 4, the second metal film is an aluminum silicon film.
- the semiconductor device manufacturing method according to the invention of claim 10 is characterized in that, in the invention of claim 4, the second metal film is a zinc film.
- a method for manufacturing a semiconductor device wherein the second metal film is formed after the second metal film is formed and before the plating film forming step.
- the method further includes a back surface activation step of performing a zincate treatment on the film.
- the semiconductor device manufacturing method according to the invention of claim 12 is characterized in that, in the invention of claim 4, the solder joint metal film is formed of nickel.
- the semiconductor device manufacturing method according to the invention of claim 13 is characterized in that, in the invention of claim 4, the solder joint metal film is formed of a metal whose main component is nickel.
- the semiconductor device manufacturing method according to the invention of claim 14 is characterized in that, in the invention of claim 4, the protective metal film is formed of gold.
- the first metal film is formed of molybdenum (Mo) or titanium (Ti). .
- the semiconductor device manufacturing method according to the invention of claim 16 is characterized in that, in the invention of claim 1, the thickness of the first metal film is 0.2 ⁇ m or more.
- the semiconductor device manufacturing method according to the invention of claim 17 is characterized in that, in the invention of claim 1, the front electrode is formed of aluminum or an aluminum alloy.
- the semiconductor device manufacturing method according to the invention of claim 18 is characterized in that, in the invention of claim 17, the aluminum alloy is aluminum silicon.
- a semiconductor device manufacturing method according to the seventeenth aspect of the present invention, wherein the front surface is formed after the second metal film is formed and before the plating film forming step. It further includes a front surface activation step of performing zincate treatment on the electrode.
- the semiconductor device manufacturing method according to a twentieth aspect of the invention is characterized in that, in the invention according to any one of the first to nineteenth aspects, the wet plating method is electroless plating.
- the solder joint metal film is simultaneously formed on the front surface electrode and the back surface electrode of the semiconductor substrate. Therefore, the stress generated by the solder joint metal film formed on the front electrode and the stress generated by the solder joint metal film formed on the back electrode are offset. Thereby, the curvature of a semiconductor substrate can be suppressed.
- the zincate process is performed on the front surface electrode of the semiconductor substrate before the electroless plating process. For this reason, the adhesion between the front surface electrode and the solder-bonded metal film is improved. Thereby, at the time of mounting by solder bonding, it is possible to prevent the front surface electrode from being peeled off from the solder bonding portion of the semiconductor device on which the semiconductor substrate is mounted.
- a first metal film and a second metal film are sequentially stacked as the back electrode of the semiconductor substrate.
- nickel is continuously deposited in the plating tank, and a solder-bonded metal film is easily formed.
- the etching of the zincate process even if the unevenness reaching the lower layer occurs on the surface of the second metal film, the etching can be stopped at the first metal film that is the lower layer of the second metal film. For this reason, the solder-bonded metal film is in close contact with the first metal film, and thus does not come into contact with the semiconductor substrate having low adhesion. Thereby, the adhesive force of a semiconductor substrate and a back surface electrode improves, and it can prevent that a back surface electrode peels from a semiconductor substrate.
- the film mainly composed of aluminum is formed on the surface layer of the back electrode of the semiconductor substrate. Therefore, as a pretreatment for the electroless plating treatment, a solder joint metal film is easily formed by performing a zincate treatment on the back electrode of the semiconductor substrate. Moreover, when performing a double zincate process, it can carry out simultaneously on both the front surface electrode and back surface electrode of a semiconductor substrate.
- the method for manufacturing a semiconductor device according to the present invention it is possible to suppress warpage of the semiconductor substrate in a semiconductor device having electrodes on both the front and back surfaces.
- the metal film stacked as an electrode can be hardly peeled off.
- FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment
- FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment
- FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment
- FIG. 3 is a cross-sectional view showing a back electrode of the semiconductor device according to the first exemplary embodiment
- FIG. 3 is a cross-sectional view showing a back electrode of the semiconductor device according to the first exemplary embodiment
- FIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment
- FIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment; 6 is a cross-sectional view showing a back electrode of a semiconductor device according to a second embodiment; FIG. 6 is a cross-sectional view showing a back electrode of a semiconductor device according to a second embodiment; FIG. It is sectional drawing which shows the structure of NPT type IGBT. It is sectional drawing which shows the structure of FS type IGBT. It is sectional drawing shown about the back surface electrode in the manufacturing method of the semiconductor device concerning a prior art. It is sectional drawing shown about the back surface electrode in the manufacturing method of the semiconductor device concerning a prior art. It is sectional drawing shown about the back surface electrode in the manufacturing method of the semiconductor device concerning a prior art. It is sectional drawing shown about the back surface electrode in the manufacturing method of the semiconductor device concerning a prior art. It is sectional drawing shown about the back surface electrode in the manufacturing method of the semiconductor device concerning a prior art.
- FIG. 1 is a flowchart showing a manufacturing process of a semiconductor device according to the present invention.
- the semiconductor device shown in FIG. 12 will be described as an example.
- the surface structure of the device is formed on the front surface of the semiconductor substrate 1 (step S1).
- the front surface electrode such as the emitter electrode 6 is formed.
- back grinding is performed on the entire back surface of the semiconductor substrate 1, and the semiconductor substrate 1 is thinned to a thickness of 160 ⁇ m, for example (step S2).
- an etching process is performed on the back surface of the semiconductor substrate 1 to make the semiconductor substrate 1 thinner by, for example, 20 ⁇ m (step S3).
- an impurity implantation layer is formed on the back surface of the thinned semiconductor substrate 1 by sequentially implanting, for example, phosphorus and boron (step S4).
- an activation heat treatment is performed on the impurity implantation layer formed in step S4, thereby forming the n buffer layer 10 and the p + collector layer 8 (step S5).
- the natural oxide film on the surface of the p + collector layer 8 is removed with dilute hydrofluoric acid (step S6).
- titanium and nickel are sequentially stacked by vapor deposition or sputtering (step S7). In this step, the back electrode is formed.
- step S8 the electroless nickel plating process and the displacement gold plating process are continuously performed, and a nickel plating film and a displacement gold plating film are simultaneously formed on both the front surface electrode and the back surface electrode of the semiconductor substrate 1 (step S8). .
- the collector electrode 9 is formed.
- FIG. 2 to 4 are sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.
- steps S1 to S3 a base region and an emitter region (not shown) are formed in the surface layer of the semiconductor substrate 1 as shown in FIG.
- an interlayer insulating film 7 is formed on the front surface of the semiconductor substrate 1 on which the device surface structure is formed.
- an emitter electrode 6 hereinafter referred to as an aluminum electrode
- the interlayer insulating film 7 is formed on the front surface of the semiconductor substrate 1 so as to cover a gate electrode (not shown).
- step S3 the damaged layer due to the back grinding process can be removed.
- an etching method for example, dry etching or spin etching is used.
- a buffer layer and a collector layer are formed on the back surface of the semiconductor substrate 1.
- a titanium film 12 and a nickel film 13 are sequentially stacked on the back surface of the semiconductor substrate 1 as a back electrode.
- the film thicknesses of the titanium film 12 and the nickel film 13 are, for example, 0.2 ⁇ m and 0.7 ⁇ m.
- the titanium film 12 corresponds to a first metal film.
- the nickel film 13 corresponds to a second metal film.
- a nickel plating film 14 is simultaneously formed on the surfaces of the aluminum electrode 6 and the nickel film (nickel film 13 in FIG. 3). Then, a displacement gold plating film 15 is formed on the surface of the nickel plating film 14. At this time, in order to improve the adhesion of the nickel plating film 14 to the surface of the aluminum electrode 6 on the front surface of the semiconductor substrate 1, as a pretreatment of the electroless nickel plating treatment, the surface of the aluminum electrode 6 is doubled. Perform zincate treatment. The double zincate process will be described later.
- the film thicknesses of the nickel plating film 14 and the displacement gold plating film 15 are, for example, 5 ⁇ m and 0.03 ⁇ m.
- the collector electrode 9 (see FIG. 12) formed by laminating the back electrode (titanium film 12 and the nickel film 13 in FIG. 3), the nickel plating film 14 and the displacement gold plating film 15 is formed on the back surface of the semiconductor substrate 1. Is done.
- the nickel plating film 14 corresponds to a soldered metal film.
- the displacement gold plating film 15 corresponds to a protective metal film.
- the adhesion between the semiconductor substrate 1 and the back electrode can be improved.
- the reason is as follows. 5 and 6 are cross-sectional views illustrating the back electrode of the semiconductor device according to the first embodiment.
- the titanium film 12 and the nickel film 13 are laminated on the back surface of the semiconductor substrate 1 as the back surface electrodes as shown in FIG. Thereafter, even if the surface of the nickel film 13 is uneven due to the double zincate etching, the etching can be stopped at the titanium film 12 between the nickel film 13 and the semiconductor substrate 1. Thereby, it is possible to prevent the semiconductor substrate 1 from being exposed. Therefore, as shown in FIG.
- the nickel plating film 14 is formed on the surface of the nickel film 13 with the unevenness, the nickel plating film 14 is not in contact with the semiconductor substrate 1 with low adhesion. Adheres to the titanium film 12. Thereby, the adhesive force between the semiconductor substrate 1 and the back electrode is improved, and the collector electrode 9 formed by laminating the back electrode and each plating film is hardly peeled from the semiconductor substrate 1.
- the titanium film 12 is formed in the first embodiment, the same effect can be obtained by forming a molybdenum (Mo) film instead of the titanium film.
- the metal film corresponding to the first metal film may be a titanium film, a molybdenum film, or a degreasing process, an etching with an alkali or an acid, and a zincate process performed as a pretreatment of the electroless plating process.
- it may be formed of a metal film other than a titanium film or a molybdenum film.
- the thickness of the titanium film 12 needs to be 0.2 ⁇ m or more. The reason is as follows. When the thickness of the titanium film 12 is 0.2 ⁇ m or less, the etching cannot be stopped at the titanium film 12, and the adhesion between the semiconductor substrate 1 and the back electrode is reduced. Therefore, the back electrode is peeled off from the semiconductor substrate 1 due to thermal stress during mounting by solder bonding.
- the deposition of the nickel plating film 14 can be promoted.
- the nickel film 13 causes the continuous deposition of nickel in the plating tank to facilitate the formation of the nickel plating film 14. Similar effects can be obtained by forming an aluminum film, an aluminum silicon film or a zinc (Zn) film in place of the nickel film 13.
- the metal film corresponding to the second metal film may be a nickel film, an aluminum film, an aluminum silicon film, or a zinc film, and a redox reaction with a substance that becomes a solder joint metal film in the plating tank. As long as it is a metal that easily occurs, it may be formed of a metal film other than a nickel film, an aluminum film, an aluminum silicon film, or a zinc film.
- the back electrode can be soldered by forming the nickel plating film 14.
- a plating film formed of a nickel alloy may be used.
- An example of the nickel alloy is a nickel alloy containing phosphorus (P) or boron (B). That is, the metal film corresponding to the solder-bonded metal film may be formed of a metal to which solder is easily bonded. Further, by forming the replacement gold plating film 15, the surface oxidation of the nickel plating film 14 can be prevented.
- the metal film corresponding to such a protective metal film is not limited to the gold plating film, and may be formed of a metal that prevents the underlying metal film from being oxidized.
- the procedure for the double zincate process described above will be described. This treatment is performed on the surface of the aluminum electrode 6. First, a degreasing process is performed. Next, a first zincate process is performed after the etching process. Next, after the nitric acid treatment, a second zincate treatment is finally performed. Between a certain process and the next process, the process which wash
- the double zincate treatment aluminum in the aluminum electrode 6 is replaced with zinc, and a zinc film is formed on the surface of the aluminum electrode 6. When the electroless plating process is subsequently performed, the zinc film is replaced with nickel, and subsequently, nickel is continuously deposited to form the nickel plating film 14. That is, the nickel plating film 14 can be reliably and firmly formed on the surface of the aluminum electrode 6 by the double zincate process. In addition, sufficient adhesion can be obtained even with a single zincate treatment.
- the nickel plating film 14 is simultaneously formed on the aluminum electrode 6 and the back electrode of the semiconductor substrate 1. Therefore, the stress generated by the nickel plating film 14 formed on the aluminum electrode 6 and the stress generated by the nickel plating film 14 formed on the back electrode are offset. Thereby, the curvature of the semiconductor substrate 1 can be suppressed. Further, before the electroless plating process, the double zincate process is performed on the aluminum electrode 6 on the front surface of the semiconductor substrate 1. Therefore, the adhesion between the aluminum electrode 6 and the nickel plating film 14 is improved. Thereby, it is possible to prevent the front electrode from being peeled off from the solder joint portion of the semiconductor device on which the semiconductor substrate 1 is mounted at the time of mounting by solder joint.
- a titanium film 12 and a nickel film 13 are sequentially stacked on the back surface of the semiconductor substrate 1 as a back electrode.
- nickel film 13 is formed on the surface layer on the back surface of the semiconductor substrate 1, in the electroless plating process, nickel is continuously deposited in the plating tank, and the nickel plating film 14 is easily formed. Further, in the etching of the double zincate process, even if irregularities reaching the lower layer occur on the surface of the nickel film 13, the etching can be stopped at the titanium film 12 that is the lower layer of the nickel film 13. Therefore, since the nickel plating film 14 is in close contact with the titanium film 12, it is not in contact with the semiconductor substrate 1 having low adhesion.
- the adhesive force between the semiconductor substrate 1 and the back electrode is improved, and the collector electrode 9 formed by laminating the back electrode and each plating film can be prevented from peeling from the semiconductor substrate 1. Therefore, the semiconductor substrate 1 which has an electrode on both front and back surfaces can be manufactured with a high yield rate.
- Embodiment 2 A method for manufacturing the semiconductor device according to the second embodiment will be described. Regarding the description of the second embodiment and the accompanying drawings, the description overlapping with that of the first embodiment is omitted.
- the steps S1 to S8 are performed according to the flowchart shown in FIG. Thereby, the electroless nickel plating process and the displacement gold plating process are continuously performed on both the front and back surfaces of the semiconductor substrate 1 simultaneously.
- the metal that is sequentially laminated on the back surface of the semiconductor substrate 1 by vapor deposition or sputtering in the step S7 is titanium or aluminum.
- FIG. 7 and 8 are cross-sectional views showing the manufacturing process of the semiconductor device according to the second embodiment.
- steps S1 to S3 described above a base region and an emitter region (not shown) are formed in the surface layer of the semiconductor substrate 1 as in the first embodiment.
- an interlayer insulating film 7 and an aluminum electrode 6 are formed on the front surface of the semiconductor substrate 1.
- a buffer layer and a collector layer are formed on the back surface of the semiconductor substrate 1.
- a titanium film 12 and an aluminum film 16 are sequentially stacked on the back surface of the semiconductor substrate 1 as a back electrode.
- the film thicknesses of the titanium film 12 and the aluminum film 16 are, for example, 0.2 ⁇ m and 2.0 ⁇ m.
- the aluminum film 16 corresponds to a second metal film.
- the nickel plating film 14 is simultaneously formed on the surfaces of the aluminum electrode 6 and the aluminum film 16. Then, a displacement gold plating film 15 is formed on the surface of the nickel plating film 14. At this time, a double zincate treatment is performed on the surface of the aluminum electrode 6 as a pretreatment for the electroless nickel plating treatment. The reason is the same as in the first embodiment. The thicknesses of the nickel plating film 14 and the displacement gold plating film 15 are the same as those in the first embodiment. As a result, the collector electrode 9 (see FIG. 12) is formed on the back surface of the semiconductor substrate 1 by laminating the back electrode (titanium film 12 and aluminum film 16), the nickel plating film 14 and the displacement gold plating film 15.
- both the front and back surfaces of the semiconductor substrate 1 can be brought close to the same substrate conditions.
- an aluminum silicon film or a zinc film may be formed.
- the double zincate process is performed on the back surface of the semiconductor substrate 1 in the same manner as the front surface of the semiconductor substrate 1. The reason is the same as that of the aluminum electrode 6. Therefore, the double zincate process and the electroless plating process can be simultaneously performed on both the front and back surfaces of the semiconductor substrate 1. Thereby, the curvature of the semiconductor substrate 1 can be suppressed.
- FIG. 9 and 10 are cross-sectional views illustrating the back electrode of the semiconductor device according to the second embodiment.
- the titanium film 12 and the aluminum film 16 are laminated on the back surface of the semiconductor substrate 1 as a back electrode, as shown in FIG.
- the etching can be stopped at the titanium film 12 between the aluminum film 16 and the semiconductor substrate 1. Therefore, as shown in FIG.
- a molybdenum (Mo) film may be formed instead of the titanium film, as in the first embodiment.
- the same effect as in the first embodiment can be obtained.
- the nickel plating film 14 is easily formed in the electroless plating process by performing the double zincate process on the back surface of the semiconductor substrate 1. .
- aluminum films are formed on both the front and back surfaces of the semiconductor substrate 1, so that the double zincate process can be performed simultaneously on both the front and back surfaces of the semiconductor substrate 1. Thereby, the curvature of the semiconductor substrate 1 can be suppressed. Therefore, the semiconductor substrate 1 which has an electrode on both front and back surfaces can be manufactured with a high yield rate.
- the plating film formed on the surface of the electrode is formed using nickel and gold.
- the present invention is not limited to this, and the plating film is formed with a uniform film thickness on the electrode surface.
- Any metal that can be applied is applicable.
- any metal that can form a plating film having better wettability with respect to solder than a metal that is a component of an electrode can be applied as a plating film.
- a metal for example, cobalt (Co), palladium (Pd), copper (Cu), silver (Ag), platinum (Pt), tin (Sn), and the like are applicable.
- an aluminum silicon film may be formed as a back electrode between the semiconductor substrate 1 and the titanium film 12.
- the aluminum silicon film is formed on the surface of the semiconductor substrate 1 by vapor deposition or sputtering.
- the film thickness of the aluminum silicon film is, for example, 0.5 ⁇ m.
- the silicon concentration of the aluminum silicon film is preferably 0.5 wt% or more and 2 wt% or less, and particularly preferably 1 wt% or less.
- the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a semiconductor device with a thin device thickness.
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Abstract
Provided is a process for fabricating a semiconductor device wherein an electrode is not peeled off easily from a semiconductor substrate. A front-surface electrode or the surface structure of a device is formed on the front surface of the semiconductor substrate (1). The semiconductor substrate (1) is then made thin by performing back grinding and etching on the entire back surface thereof. Subsequently, a buffer layer and a collector layer are formed on the back surface of the semiconductor substrate (1), which has been made thin, by performing ion implantation and heat treatment. Thereafter, a titanium film (12) and a nickel film are formed, as a back-surface electrode, sequentially on the back surface of the semiconductor substrate (1) by deposition or sputtering. Thereafter, electroless nickel plating and substitution gold plating are performed continuously, and a nickel plated film (14) and a substitution gold plated film (15) are formed simultaneously on the opposite sides of the front-surface electrode and the back-surface electrode of the semiconductor substrate (1), thus forming a collector electrode (9). As a preprocessing of electroless nickel plating, double zincate processing is performed on the front-surface electrode of the semiconductor substrate (1).
Description
この発明は、半導体装置の製造方法に関し、特に電力変換装置などに用いられるパワー半導体装置であって、半導体装置のおもて面および裏面に電極を有する８０～２００μｍの厚さの半導体装置の製造方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a power semiconductor device used for a power conversion device or the like, and manufacturing a semiconductor device having a thickness of 80 to 200 μm having electrodes on the front surface and the back surface of the semiconductor device. Regarding the method.
電力用半導体装置の一つであるＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）は、ＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）の高速スイッチング特性および電圧駆動特性と、バイポーラトランジスタの低オン電圧特性を有するワンチップのパワーデバイスである。その応用範囲は、汎用インバータ、ＡＣサーボ、無停電電源（ＵＰＳ）またはスイッチング電源などの産業分野から、電子レンジ、炊飯器またはストロボなどの民生機器分野へと拡大してきている。また、新しいチップ構造を用いた、より低オン電圧のＩＧＢＴが開発されており、ＩＧＢＴを用いた応用装置の低損失化や高効率化が図られてきている。
An IGBT (insulated gate type bipolar transistor), which is one of power semiconductor devices, is a one-chip device having high-speed switching characteristics and voltage driving characteristics of MOSFETs (insulated gate type field effect transistors) and low on-voltage characteristics of bipolar transistors. It is a power device. The range of applications has expanded from industrial fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS), or switching power supplies to consumer equipment fields such as microwave ovens, rice cookers, and strobes. Further, IGBTs having a lower on-voltage using a new chip structure have been developed, and reductions in the loss and efficiency of application devices using the IGBT have been achieved.
ＩＧＢＴには、パンチスルー（以下、ＰＴとする）型、ノンパンチスルー（以下、ＮＰＴとする）型、フィールドストップ（以下、ＦＳとする）型などの構造があり、一部の用途を除いて、ｎチャネル型の縦型二重拡散構造のものが主流である。従って、本明細書では、ｎチャネル型ＩＧＢＴを例にして説明するが、ｐチャネル型ＩＧＢＴでも同様である。
IGBT has structures such as punch-through (hereinafter referred to as PT), non-punch-through (hereinafter referred to as NPT), and field stop (hereinafter referred to as FS) types, except for some applications. An n-channel vertical double diffusion structure is the mainstream. Therefore, in this specification, an n-channel IGBT is described as an example, but the same applies to a p-channel IGBT.
ＰＴ型ＩＧＢＴは、ｐ+半導体基板上にｎ+バッファ層とｎ-活性層をエピタキシャル成長させたエピタキシャル基板を用いて形成される。そのため、例えば耐圧６００Ｖ系の半導体装置では、活性層の厚さは１００μｍ程度で十分であるが、ｐ+半導体基板の部分を含む総厚さは２００～３００μｍ程度と、厚くなる。また、エピタキシャル基板を用いるため、コストが高くなる。
The PT-type IGBT is formed using an epitaxial substrate obtained by epitaxially growing an n + buffer layer and an n − active layer on a p + semiconductor substrate. Therefore, for example, in a semiconductor device having a withstand voltage of 600 V, an active layer thickness of about 100 μm is sufficient, but the total thickness including the p + semiconductor substrate portion is as thick as about 200 to 300 μm. Further, since an epitaxial substrate is used, the cost is increased.
そこで、エピタキシャル基板の代わりに、フローティングゾーン（ＦＺ）法により作製された半導体インゴットから切り出されたＦＺ基板を用いることによって低コスト化を図ったＮＰＴ型やＦＳ型のＩＧＢＴが開発されている。これらのＩＧＢＴでは、半導体装置の裏面に低ドーズ量の浅いｐ+コレクタ層（低注入ｐ+コレクタ）が形成される。
In view of this, NPT type and FS type IGBTs have been developed in which the cost is reduced by using an FZ substrate cut out from a semiconductor ingot manufactured by a floating zone (FZ) method instead of an epitaxial substrate. In these IGBTs, a shallow p + collector layer (low implantation p + collector) with a low dose is formed on the back surface of the semiconductor device.
図１１は、ＦＺ基板を用いて作製されたＮＰＴ型ＩＧＢＴの構成を示す断面図である。図１１に示すように、ＮＰＴ型ＩＧＢＴは、例えばＦＺ基板よりなるｎ-半導体基板１を活性層とし、その表面層にｐ+ベース領域２、ｎ+エミッタ領域３が選択的に形成される。そして、ｎ-半導体基板１の表面には、ゲート酸化膜４を介してゲート電極５が形成される。エミッタ電極６は、ｎ+エミッタ領域３およびｐ+ベース領域２と接触し、かつ層間絶縁膜７によりゲート電極５から絶縁される。また、ｎ-半導体基板１の裏面には、ｐ+コレクタ層８およびコレクタ電極９が形成される。ＮＰＴ型ＩＧＢＴは、ＰＴ型ＩＧＢＴよりも基板の総厚さが大幅に薄くなる。そして、ＮＰＴ型ＩＧＢＴは、正孔の注入率を制御することができるので、ライフタイム制御を行わなくても、高速スイッチングが可能である。また、ＮＰＴ型ＩＧＢＴの製造には、エピタキシャル基板を用いずに、ＦＺ基板を用いるので、安価である。
FIG. 11 is a cross-sectional view showing a configuration of an NPT type IGBT manufactured using an FZ substrate. As shown in FIG. 11, in the NPT type IGBT, for example, an n − semiconductor substrate 1 made of an FZ substrate is used as an active layer, and a p + base region 2 and an n + emitter region 3 are selectively formed on the surface layer. A gate electrode 5 is formed on the surface of the n − semiconductor substrate 1 via a gate oxide film 4. Emitter electrode 6 is in contact with n + emitter region 3 and p + base region 2 and is insulated from gate electrode 5 by interlayer insulating film 7. A p + collector layer 8 and a collector electrode 9 are formed on the back surface of the n − semiconductor substrate 1. The total thickness of the NPT type IGBT is significantly thinner than that of the PT type IGBT. Since the NPT type IGBT can control the injection rate of holes, high-speed switching is possible without performing lifetime control. In addition, the NPT type IGBT is inexpensive because an FZ substrate is used instead of an epitaxial substrate.
図１２は、ＦＳ型ＩＧＢＴの構成を示す断面図である。図１２に示すように、半導体基板の表面構造は、図１１に示すＮＰＴ型ＩＧＢＴと同じである。ｎ-半導体基板１の裏面には、ｎ-半導体基板１とｐ+コレクタ層８との間に、ｎバッファ層１０が設けられる。ＦＳ型ＩＧＢＴでは、ＦＺ基板を用いることによって、基板の総厚さが８０～２００μｍとなる。そして、ＰＴ型ＩＧＢＴと同様に、活性層であるｎ-半導体基板１を空乏化させるため、６００Ｖ耐圧の半導体装置では、ｎ-半導体基板１の厚さは１００μｍ程度である。また、ＮＰＴ型ＩＧＢＴと同様に、ライフタイム制御は不要である。近時、オン電圧のより一層の低減を図るため、チップ表面に狭く深い溝を形成し、この溝の側面にＭＯＳＦＥＴを形成したトレンチ構造と、ＦＳ型構造を組み合わせた構造のＩＧＢＴも提案されている。
FIG. 12 is a cross-sectional view showing the configuration of the FS type IGBT. As shown in FIG. 12, the surface structure of the semiconductor substrate is the same as that of the NPT type IGBT shown in FIG. the n - the back surface of semiconductor substrate 1, the n - between the semiconductor substrate 1 and the p + collector layer 8, n buffer layer 10 is provided. In the FS type IGBT, by using the FZ substrate, the total thickness of the substrate becomes 80 to 200 μm. Similarly to the PT-type IGBT, n is an active layer - in order to deplete the semiconductor substrate 1, a semiconductor device 600V breakdown voltage, n - the thickness of the semiconductor substrate 1 is about 100 [mu] m. In addition, like the NPT type IGBT, lifetime control is unnecessary. Recently, in order to further reduce the on-voltage, a trench structure in which a narrow and deep groove is formed on the chip surface and a MOSFET is formed on the side surface of the groove and an IGBT having a structure combining the FS type structure has been proposed. Yes.
ＦＳ型ＩＧＢＴを製造するにあたっては、まず、半導体基板のおもて面にデバイスの表面構造を作製する。その後に、半導体基板の裏面にバックグラインドを行って、半導体基板を薄くする。ついで、その薄化した半導体基板の裏面に２種類のイオンを順次注入して活性化熱処理を行うことで、半導体基板の裏面にバッファ層１０およびコレクタ層８が形成される。そして、コレクタ層８の表面にアルミニウム（Ａｌ）等の金属を蒸着またはスパッタして、コレクタ電極９が形成される。
In manufacturing the FS type IGBT, first, the surface structure of the device is fabricated on the front surface of the semiconductor substrate. Thereafter, back grinding is performed on the back surface of the semiconductor substrate to thin the semiconductor substrate. Subsequently, two types of ions are sequentially implanted into the back surface of the thinned semiconductor substrate and an activation heat treatment is performed, whereby the buffer layer 10 and the collector layer 8 are formed on the back surface of the semiconductor substrate. Then, a collector electrode 9 is formed by depositing or sputtering a metal such as aluminum (Al) on the surface of the collector layer 8.
上述のような半導体装置を製造する方法として、次のような方法が提案されている。シリコン基板の第１の主面側に素子の表面構造を形成し、第２の主面を研削加工して基板を薄くした後、第２の主面側にバッファ層およびコレクタ層を形成する。その後、コレクタ層の表面に、厚さが０．３μｍ以上１．０μｍ以下で、シリコン濃度が０．５ｗｔ％以上２ｗｔ％以下、好ましくは１ｗｔ％以下のアルミニウムシリコン膜を形成する。そして、アルミニウムシリコン膜の形成に続いて、チタン、ニッケルおよび金などの複数の金属を蒸着またはスパッタにより形成し、コレクタ電極を形成する。チタン膜、ニッケル膜および金膜は、それぞれバッファ金属膜、はんだ接合金属膜および保護金属膜である（例えば、下記特許文献１参照。）。
The following method has been proposed as a method for manufacturing the semiconductor device as described above. The surface structure of the element is formed on the first main surface side of the silicon substrate, the second main surface is ground to thin the substrate, and then the buffer layer and the collector layer are formed on the second main surface side. Thereafter, an aluminum silicon film having a thickness of 0.3 μm or more and 1.0 μm or less and a silicon concentration of 0.5 wt% or more and 2 wt% or less, preferably 1 wt% or less is formed on the surface of the collector layer. Then, following the formation of the aluminum silicon film, a plurality of metals such as titanium, nickel and gold are formed by vapor deposition or sputtering to form a collector electrode. The titanium film, nickel film, and gold film are a buffer metal film, a solder joint metal film, and a protective metal film, respectively (see, for example, Patent Document 1 below).
上述した特許文献１の技術において、アルミニウムシリコン膜は、アルミスパイクを防止する目的で形成される。また、チタン膜ははんだ実装時のニッケルの拡散防止のために形成され、ニッケル膜は裏面コレクタ電極のはんだ接合のために形成される。そして、金膜はニッケル膜の酸化防止のために形成される。
In the technique of Patent Document 1 described above, the aluminum silicon film is formed for the purpose of preventing aluminum spikes. The titanium film is formed to prevent nickel diffusion during solder mounting, and the nickel film is formed to solder the back collector electrode. The gold film is formed to prevent oxidation of the nickel film.
ところで、半導体装置の実装において、裏面電極は、はんだを用いて接合される。また、半導体装置のおもて面に形成されるおもて面電極はアルミワイヤーを用いたワイヤボンディング技術を用いて接合されるのが主流であるが、最近では、おもて面電極においても、はんだ接合が用いられることがある。おもて面電極の接合に、はんだ接合を用いることで、高密度実装化、電流密度向上、スイッチング速度の高速化のための配線容量低減、半導体装置の冷却効率向上などを大幅に改善することができる。
By the way, in mounting a semiconductor device, the back electrode is joined using solder. In addition, the front surface electrode formed on the front surface of the semiconductor device is mainly bonded using a wire bonding technique using an aluminum wire, but recently, the front surface electrode is also used. Solder bonding may be used. By using solder joints for bonding front surface electrodes, it is possible to greatly improve high-density mounting, improved current density, reduced wiring capacity for higher switching speed, improved cooling efficiency of semiconductor devices, etc. Can do.
はんだ接合により実装された半導体装置として、次のような装置が提案されている。各半導体チップの表面にＥヒートシンクがはんだにより接合され、裏面に第２の導体部材がはんだにより接合され、Ｅヒートシンクの表面に第３の導体部材がはんだにより接合されている。Ｅヒートシンクには段差部が設けられて薄肉部が形成されており、Ｅヒートシンクと各半導体チップとの接合面積よりＥヒートシンクと第３の導体部材との接合面積が小さくなっている。第２の導体部材の裏面と第３の導体部材の表面とが露出した状態で、各部材が樹脂封止されている（例えば、下記特許文献２参照。）。
The following devices have been proposed as semiconductor devices mounted by solder bonding. An E heat sink is joined to the surface of each semiconductor chip by solder, a second conductor member is joined to the back surface by solder, and a third conductor member is joined to the surface of the E heat sink by solder. The E heat sink is provided with a step portion to form a thin portion, and the bonding area between the E heat sink and the third conductor member is smaller than the bonding area between the E heat sink and each semiconductor chip. Each member is resin-sealed with the back surface of the second conductor member and the surface of the third conductor member exposed (see, for example, Patent Document 2 below).
また、別の装置として、半導体素子と、この半導体素子の裏面に接合され電極と放熱を兼ねる第１の金属体と、前記半導体素子の表面側に接合され電極と放熱を兼ねる第２の金属体と、前記半導体素子の表面と前記第２の金属体との間に接合された第３の金属体とを備え、装置のほぼ全体を樹脂でモールドした半導体装置において、前記半導体素子表面のせん断応力、または、前記半導体素子と前記金属体とを接合する接合層における歪み成分等を低減させるように、前記半導体素子の厚さを薄くすると共に、前記モールド樹脂により装置全体を拘束保持するように構成したことを特徴とし、前記接合層をＳｎ系はんだで構成する半導体装置が提案されている（例えば、下記特許文献３参照。）。
As another device, a semiconductor element, a first metal body bonded to the back surface of the semiconductor element and serving as an electrode and heat dissipation, and a second metal body bonded to the surface side of the semiconductor element and serving as an electrode and heat dissipation And a third metal body joined between the surface of the semiconductor element and the second metal body, wherein a shear stress of the surface of the semiconductor element is obtained in a semiconductor device in which almost the entire device is molded with resin. Alternatively, the thickness of the semiconductor element is reduced and the entire apparatus is constrained and held by the mold resin so as to reduce a distortion component or the like in a bonding layer that joins the semiconductor element and the metal body. A semiconductor device in which the bonding layer is made of Sn-based solder has been proposed (for example, see Patent Document 3 below).
実際に、おもて面電極のはんだ接合を行う場合、おもて面電極の表面にニッケル（Ｎｉ）等のめっきを施す必要がある。めっき処理法としては、電気めっき法や無電解めっき法などが一般的である。電気めっき法は、外部電流を供給することにより溶液中の金属イオンを還元析出させる方法である。一方、無電解めっき法は、電気を使用することなく、溶液中の金属イオンを化学的に還元析出する方法である。そのため、対極や直流電源などの電気回路を必要とする電気めっき法を用いるよりも、無電解めっき法を用いてめっき処理を行うほうが、製造装置や製造工程を簡略化することができる。また、無電解めっき処理の前処理として、おもて面電極の表面にジンケート処理を行うことで、おもて面電極とめっき皮膜との密着力を向上させることができる。その理由は、めっき面が、例えば、アルミニウムやマグネシウムのような酸化還元電位が著しく卑な物質に対して無電解ニッケルめっきを行う場合、めっき面を活性化させる必要があるからである。ジンケート処理については、例えば、下記特許文献４に開示されている。しかしながら、半導体基板を無電解めっき液に浸漬させた場合、無電解めっき液に対して活性化されていない半導体基板の裏面や側面にも無電解めっき反応が起こり、ニッケルが異常析出する場合がある。ニッケルの異常析出が起こると、めっき液中のニッケルの濃度が低下し、めっき膜の厚さを制御することが困難となる。
Actually, when soldering the front surface electrode, it is necessary to plate the surface of the front surface electrode with nickel (Ni) or the like. As the plating method, an electroplating method or an electroless plating method is generally used. The electroplating method is a method for reducing and depositing metal ions in a solution by supplying an external current. On the other hand, the electroless plating method is a method in which metal ions in a solution are chemically reduced and deposited without using electricity. Therefore, it is possible to simplify the manufacturing apparatus and the manufacturing process by performing the plating process using the electroless plating method, rather than using the electroplating method that requires an electric circuit such as a counter electrode or a DC power source. In addition, as a pretreatment of the electroless plating treatment, the adhesion between the front electrode and the plating film can be improved by performing a zincate treatment on the surface of the front electrode. The reason is that when the electroless nickel plating is performed on a material having a remarkably low redox potential such as aluminum or magnesium, the plated surface needs to be activated. The zincate process is disclosed in, for example, Patent Document 4 below. However, when a semiconductor substrate is immersed in an electroless plating solution, an electroless plating reaction may occur on the back and side surfaces of the semiconductor substrate that are not activated with respect to the electroless plating solution, and nickel may be precipitated abnormally. . When the abnormal precipitation of nickel occurs, the concentration of nickel in the plating solution decreases, and it becomes difficult to control the thickness of the plating film.
無電解めっき処理時のニッケルの異常析出を防ぐ方法として、半導体基板にめっき保護用のレジストを塗布する方法がある。しかしながら、半導体基板とレジスト膜との密着性が低く、８０℃前後でめっきを行う無電解ニッケルめっき処理ではレジスト膜が剥離してしまう。また、レジスト成分が溶解することによる無電解めっき液の汚染や、高価なレジストを使用することによる製造コストの増大、そして、レジスト保護膜の形成によって薄い半導体基板に反りが発生してしまう等の問題も生じる。
As a method for preventing abnormal precipitation of nickel during electroless plating, there is a method of applying a plating protection resist to a semiconductor substrate. However, the adhesion between the semiconductor substrate and the resist film is low, and the resist film peels off in the electroless nickel plating process in which plating is performed at around 80 ° C. In addition, contamination of the electroless plating solution due to dissolution of the resist component, increase in manufacturing cost due to the use of an expensive resist, and warping of a thin semiconductor substrate due to formation of a resist protective film, etc. Problems also arise.
そこで、レジスト膜を用いないで無電解めっきを行う方法として、次のような方法が提案されている。パッド電極上に亜鉛置換法により亜鉛置換皮膜を置換析出させ、ついで、純水で洗浄した後、対極にステンレスの棒材にニッケルめっきを施したものを用い、該対極を負電極として被めっき基板である半導体基板に微小な正電位を印加しながら酸化還元型の無電解ニッケルめっき液に浸漬することにより、半導体基板の裏面及び側面にめっきレジストを塗布することなく、複数個のパッド電極上に均一な膜厚の無電解ニッケルめっき皮膜による突起電極が得られる（例えば、下記特許文献５参照。）。
Therefore, the following method has been proposed as a method for performing electroless plating without using a resist film. A zinc substitution film is deposited on the pad electrode by a zinc substitution method, then washed with pure water, and then a counter electrode is made of a stainless steel rod plated with nickel, and the substrate to be plated with the counter electrode as a negative electrode By immersing in a redox-type electroless nickel plating solution while applying a minute positive potential to the semiconductor substrate, it is possible to apply a plating resist on the back and side surfaces of the semiconductor substrate on a plurality of pad electrodes. A protruding electrode with an electroless nickel plating film having a uniform thickness can be obtained (for example, see Patent Document 5 below).
しかしながら、上述した特許文献５の技術では、８０～２００μｍと薄い半導体基板の場合、半導体基板を治具に取り付ける作業が手作業となり、大量生産に向いていない。そのため、次のような方法が提案されている。半導体素子が形成された半導体基板上に層間絶縁膜が設けられている。そして、この層間絶縁膜上に形成された第１表面電極の表面には、コンタクトホールの形状に応じた凹部が複数設けられ、第１裏面電極の表面はエッチング処理によってでこぼこになっていることで、第１表面電極の表面積と第１裏面電極の表面積との差が小さくされている。また、第２表面電極および第２裏面電極は、第１表面電極および第１裏面電極の表面それぞれに同時に湿式めっきの方法により形成されている。具体的には、ウェハ表裏面に同時に例えばＮｉをめっきする。これにより、ウェハ表面側に第２表面電極を形成し、ウェハ裏面側に第２裏面電極を形成する。そして、ウェハ表裏面に同時に湿式めっきを施し、メッキ層を形成する。すなわち、第２表面電極の表面、第２裏面電極の表面それぞれに例えばＡｕのメッキ層を形成する（例えば、下記特許文献６参照。）。
However, in the technique of Patent Document 5 described above, in the case of a semiconductor substrate as thin as 80 to 200 μm, the operation of attaching the semiconductor substrate to a jig is a manual operation and is not suitable for mass production. Therefore, the following method has been proposed. An interlayer insulating film is provided on the semiconductor substrate on which the semiconductor element is formed. A plurality of recesses corresponding to the shape of the contact hole are provided on the surface of the first front surface electrode formed on the interlayer insulating film, and the surface of the first back surface electrode is uneven due to the etching process. The difference between the surface area of the first surface electrode and the surface area of the first back electrode is reduced. The second surface electrode and the second back electrode are simultaneously formed on the surfaces of the first surface electrode and the first back electrode by a wet plating method. Specifically, for example, Ni is plated on the front and back surfaces of the wafer at the same time. Thus, the second front electrode is formed on the wafer front side, and the second back electrode is formed on the wafer back side. Then, wet plating is simultaneously performed on the front and back surfaces of the wafer to form a plating layer. That is, for example, an Au plating layer is formed on the surface of the second surface electrode and the surface of the second back electrode (see, for example, Patent Document 6 below).
しかしながら、薄い基板の片面にめっき膜を形成すると、このめっき膜による応力によって基板が反ってしまうという問題がある。また、上述した特許文献６に記載された技術に関しては、次のような問題がある。本発明者が、半導体基板の表裏の両面に、同時に無電解めっき処理を行った結果、めっき直後であるにもかかわらず、半導体基板の裏面電極が容易に剥離してしまうことが判明した。その理由は、次に示すとおりである。図１３～図１５は、従来技術にかかる半導体装置の製造方法における裏面電極について示す断面図である。図１３～図１５において、半導体基板の裏面に形成されているバッファ層およびコレクタ層は図示を省略する（図２～図１０においても同じ）。まず、図１３に示すように、半導体基板１の裏面に、裏面電極として、アルミニウムシリコン（ＡｌＳｉ）膜１１を形成する。ついで、半導体基板１の裏面にエッチング処理を行い、アルミニウムシリコン膜１１の表面に凹凸を形成する。その後、半導体基板１の表裏の両面に同時に無電解めっき処理を行うことにより、半導体基板１の裏面では、アルミニウムシリコン膜１１の表面に、ニッケル（Ｎｉ）めっき膜１４および置換金（Ａｕ）めっき膜１５がこの順で形成される。これにより、アルミニウムシリコン膜１１、ニッケル（Ｎｉ）めっき膜１４および置換金（Ａｕ）めっき膜１５が積層されてなるコレクタ電極９（図１２参照）が形成される。
However, when a plating film is formed on one surface of a thin substrate, there is a problem that the substrate is warped by the stress caused by the plating film. Further, the technique described in Patent Document 6 described above has the following problems. As a result of the electroless plating treatment performed simultaneously on both the front and back surfaces of the semiconductor substrate by the present inventor, it has been found that the back electrode of the semiconductor substrate is easily peeled off immediately after plating. The reason is as follows. 13 to 15 are cross-sectional views showing the back electrode in the method of manufacturing a semiconductor device according to the prior art. 13 to 15, the buffer layer and the collector layer formed on the back surface of the semiconductor substrate are not shown (the same applies to FIGS. 2 to 10). First, as shown in FIG. 13, an aluminum silicon (AlSi) film 11 is formed as a back electrode on the back surface of the semiconductor substrate 1. Next, an etching process is performed on the back surface of the semiconductor substrate 1 to form irregularities on the surface of the aluminum silicon film 11. Thereafter, by performing electroless plating on both the front and back surfaces of the semiconductor substrate 1 at the same time, the nickel (Ni) plating film 14 and the replacement gold (Au) plating film are formed on the surface of the aluminum silicon film 11 on the back surface of the semiconductor substrate 1. 15 are formed in this order. As a result, a collector electrode 9 (see FIG. 12) formed by laminating the aluminum silicon film 11, the nickel (Ni) plating film 14, and the displacement gold (Au) plating film 15 is formed.
このとき、上述した特許文献６の技術では、アルミニウムシリコン膜１１の形成後、裏面電極として形成するアルミニウムシリコン膜１１には、おもて面電極の形成時のように３００～５００℃程度での熱処理が行われない。そのため、アルミニウムシリコン膜１１は、結晶性が悪く、疎な膜質となっている。この状態で、アルミニウムシリコン膜１１にエッチング処理を行うと、アルミニウムシリコン膜１１の表面には、図１４に示すように、半導体基板１まで到達するような凹凸が生じる。そのため、アルミニウムシリコン膜１１の表面に形成されるニッケルめっき膜１４と半導体基板１とが接触することになる。しかしながら、半導体基板１の成分であるシリコン（Ｓｉ）とニッケルめっき膜１４の成分であるニッケルは、密着性が低い。そのため、図１５に示すように、コレクタ電極９は、裏面電極（アルミニウムシリコン膜１１）と半導体基板１との境界において、半導体基板１から容易に剥離してしまう。
At this time, in the technique of Patent Document 6 described above, after the formation of the aluminum silicon film 11, the aluminum silicon film 11 formed as the back electrode is formed at about 300 to 500 ° C. as in the formation of the front surface electrode. No heat treatment is performed. Therefore, the aluminum silicon film 11 has poor crystallinity and a sparse film quality. When the etching process is performed on the aluminum silicon film 11 in this state, the surface of the aluminum silicon film 11 is uneven so as to reach the semiconductor substrate 1 as shown in FIG. Therefore, the nickel plating film 14 formed on the surface of the aluminum silicon film 11 and the semiconductor substrate 1 come into contact with each other. However, silicon (Si) which is a component of the semiconductor substrate 1 and nickel which is a component of the nickel plating film 14 have low adhesion. Therefore, as shown in FIG. 15, the collector electrode 9 is easily separated from the semiconductor substrate 1 at the boundary between the back electrode (aluminum silicon film 11) and the semiconductor substrate 1.
この発明は、上述した従来技術による問題点を解消するため、半導体基板の表裏の両面にめっき膜を形成する方法において、めっき膜の応力を半導体基板の両面で相殺し、半導体基板の反りを抑制することができる半導体装置の製造方法を提供することを目的とする。また、この発明は、半導体装置をはんだ接合により実装するに際し、電極として積層された金属膜が剥離しにくい半導体装置の製造方法を提供することを目的とする。
In order to eliminate the problems caused by the prior art described above, the present invention suppresses the warpage of the semiconductor substrate by canceling the stress of the plating film on both sides of the semiconductor substrate in the method of forming the plating film on both the front and back surfaces of the semiconductor substrate. An object of the present invention is to provide a method for manufacturing a semiconductor device. Another object of the present invention is to provide a method for manufacturing a semiconductor device in which a metal film laminated as an electrode is difficult to peel off when the semiconductor device is mounted by solder bonding.
上述した課題を解決し、目的を達成するため、請求項１の発明にかかる半導体装置の製造方法は、以下の特徴を有する。半導体基板の第１の主面におもて面電極を有し、かつ前記半導体基板の第２の主面に裏面電極を有する半導体装置を製造するにあたって、まず、前記裏面電極として、前記第２の主面の表面に第１の金属膜を形成する工程を行う。さらに、前記裏面電極として、前記第１の金属膜の表面に第２の金属膜を形成する工程を行う。その後、湿式めっきの方法により、前記おもて面電極および前記第２の金属膜の表面に、同時にめっき膜を形成する工程を行う。
In order to solve the above-described problems and achieve the object, a method for manufacturing a semiconductor device according to claim 1 has the following characteristics. In manufacturing a semiconductor device having a front electrode on the first main surface of the semiconductor substrate and a back electrode on the second main surface of the semiconductor substrate, first, the second electrode is used as the back electrode. A step of forming a first metal film on the surface of the main surface is performed. Further, a step of forming a second metal film on the surface of the first metal film as the back electrode is performed. Thereafter, a step of simultaneously forming a plating film on the surface electrode and the surface of the second metal film is performed by a wet plating method.
また、請求項２の発明にかかる半導体装置の製造方法は、請求項１に記載の発明において、前記第１の金属膜を形成する前に、前記裏面電極として、前記第２の主面の表面にアルミニウムを主成分とする金属膜を形成する工程、をさらに含むことを特徴とする。
According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect of the present invention, wherein the surface of the second main surface is used as the back electrode before the first metal film is formed. Forming a metal film containing aluminum as a main component.
また、請求項３の発明にかかる半導体装置の製造方法は、請求項１に記載の発明において、前記第１の金属膜は、前記第２の金属膜を溶解し得る処理液に対して不溶性であることを特徴とする。
According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect, wherein the first metal film is insoluble in a processing solution capable of dissolving the second metal film. It is characterized by being.
また、請求項４の発明にかかる半導体装置の製造方法は、請求項３に記載の発明において、前記めっき膜として、前記第２の金属膜の表面に、はんだ接合金属膜を形成し、前記はんだ接合金属膜の表面に保護金属膜を形成することを特徴とする。
According to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the third aspect of the present invention, wherein a solder bonding metal film is formed on the surface of the second metal film as the plating film, and the solder A protective metal film is formed on the surface of the bonding metal film.
また、請求項５の発明にかかる半導体装置の製造方法は、請求項４に記載の発明において、前記第２の金属膜は前記はんだ接合金属膜と同じ物質を主成分とする膜であることを特徴とする。
According to a fifth aspect of the present invention, there is provided the method for manufacturing a semiconductor device according to the fourth aspect, wherein the second metal film is a film mainly composed of the same material as the solder-bonded metal film. Features.
また、請求項６の発明にかかる半導体装置の製造方法は、請求項４に記載の発明において、前記第２の金属膜はニッケル膜であることを特徴とする。
The semiconductor device manufacturing method according to the invention of claim 6 is characterized in that, in the invention of claim 4, the second metal film is a nickel film.
また、請求項７の発明にかかる半導体装置の製造方法は、請求項４に記載の発明において、前記第２の金属膜はアルミニウムを主成分とする膜であることを特徴とする。
The semiconductor device manufacturing method according to the invention of claim 7 is characterized in that, in the invention of claim 4, the second metal film is a film containing aluminum as a main component.
また、請求項８の発明にかかる半導体装置の製造方法は、請求項４に記載の発明において、前記第２の金属膜はアルミニウム膜であることを特徴とする。
Also, the semiconductor device manufacturing method according to the invention of claim 8 is characterized in that, in the invention of claim 4, the second metal film is an aluminum film.
また、請求項９の発明にかかる半導体装置の製造方法は、請求項４に記載の発明において、前記第２の金属膜はアルミニウムシリコン膜であることを特徴とする。
Further, the method for manufacturing a semiconductor device according to the invention of claim 9 is characterized in that, in the invention of claim 4, the second metal film is an aluminum silicon film.
また、請求項１０の発明にかかる半導体装置の製造方法は、請求項４に記載の発明において、前記第２の金属膜は亜鉛膜であることを特徴とする。
Also, the semiconductor device manufacturing method according to the invention of claim 10 is characterized in that, in the invention of claim 4, the second metal film is a zinc film.
また、請求項１１の発明にかかる半導体装置の製造方法は、請求項７に記載の発明において、前記第２の金属膜を形成した後、前記めっき膜形成工程の前に、前記第２の金属膜にジンケート処理を行う裏面活性化工程をさらに含むことを特徴とする。
According to an eleventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the seventh aspect of the present invention, wherein the second metal film is formed after the second metal film is formed and before the plating film forming step. The method further includes a back surface activation step of performing a zincate treatment on the film.
また、請求項１２の発明にかかる半導体装置の製造方法は、請求項４に記載の発明において、前記はんだ接合金属膜はニッケルで形成されることを特徴とする。
Also, the semiconductor device manufacturing method according to the invention of claim 12 is characterized in that, in the invention of claim 4, the solder joint metal film is formed of nickel.
また、請求項１３の発明にかかる半導体装置の製造方法は、請求項４に記載の発明において、前記はんだ接合金属膜はニッケルを主成分とする金属で形成されることを特徴とする。
The semiconductor device manufacturing method according to the invention of claim 13 is characterized in that, in the invention of claim 4, the solder joint metal film is formed of a metal whose main component is nickel.
また、請求項１４の発明にかかる半導体装置の製造方法は、請求項４に記載の発明において、前記保護金属膜は金で形成されることを特徴とする。
The semiconductor device manufacturing method according to the invention of claim 14 is characterized in that, in the invention of claim 4, the protective metal film is formed of gold.
また、請求項１５の発明にかかる半導体装置の製造方法は、請求項１に記載の発明において、前記第１の金属膜はモリブデン（Ｍｏ）またはチタン（Ｔｉ）で形成されることを特徴とする。
According to a fifteenth aspect of the present invention, in the semiconductor device manufacturing method according to the first aspect, the first metal film is formed of molybdenum (Mo) or titanium (Ti). .
また、請求項１６の発明にかかる半導体装置の製造方法は、請求項１に記載の発明において、前記第１の金属膜の膜厚は０．２μｍ以上であることを特徴とする。
Also, the semiconductor device manufacturing method according to the invention of claim 16 is characterized in that, in the invention of claim 1, the thickness of the first metal film is 0.2 μm or more.
また、請求項１７の発明にかかる半導体装置の製造方法は、請求項１に記載の発明において、前記おもて面電極はアルミニウムまたはアルミニウム合金で形成されることを特徴とする。
The semiconductor device manufacturing method according to the invention of claim 17 is characterized in that, in the invention of claim 1, the front electrode is formed of aluminum or an aluminum alloy.
また、請求項１８の発明にかかる半導体装置の製造方法は、請求項１７に記載の発明において、前記アルミニウム合金はアルミニウムシリコンであることを特徴とする。
Also, the semiconductor device manufacturing method according to the invention of claim 18 is characterized in that, in the invention of claim 17, the aluminum alloy is aluminum silicon.
また、請求項１９の発明にかかる半導体装置の製造方法は、請求項１７に記載の発明において、前記第２の金属膜を形成した後、前記めっき膜形成工程の前に、前記おもて面電極にジンケート処理を行うおもて面活性化工程をさらに含むことを特徴とする。
According to a nineteenth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the seventeenth aspect of the present invention, wherein the front surface is formed after the second metal film is formed and before the plating film forming step. It further includes a front surface activation step of performing zincate treatment on the electrode.
また、請求項２０の発明にかかる半導体装置の製造方法は、請求項１～１９のいずれか一つに記載の発明において、前記湿式めっきの方法は無電解めっきであることを特徴とする。
The semiconductor device manufacturing method according to a twentieth aspect of the invention is characterized in that, in the invention according to any one of the first to nineteenth aspects, the wet plating method is electroless plating.
また、上述した発明によれば、半導体基板のおもて面電極および裏面電極に、同時にはんだ接合金属膜が形成される。そのため、おもて面電極に形成されたはんだ接合金属膜により生じる応力と、裏面電極に形成されたはんだ接合金属膜により生じる応力とが相殺される。これにより、半導体基板の反りを抑制することができる。また、無電解めっき処理を行う前に、半導体基板のおもて面電極にジンケート処理を行っている。そのため、おもて面電極と、はんだ接合金属膜との密着力が向上する。これにより、はんだ接合による実装時に、この半導体基板を実装する半導体装置のはんだ接合部からおもて面電極が剥離することを防ぐことができる。また、半導体基板の裏面電極として、第１の金属膜および第２の金属膜が順次積層される。半導体基板の裏面電極の表面層に第２の金属膜が形成されることで、無電解めっき処理において、めっき槽の中でニッケルの連続的な析出が起き、はんだ接合金属膜が形成されやすくなる。また、ジンケート処理のエッチングにおいて、第２の金属膜の表面に下層まで達する凹凸が生じたとしても、第２の金属膜の下層である第１の金属膜でエッチングを止めることができる。そのため、はんだ接合金属膜は、第１の金属膜と密着するので、密着力の低い半導体基板とは接触しない。これにより、半導体基板と裏面電極との密着力が向上し、半導体基板から裏面電極が剥離することを防止することができる。
Further, according to the above-described invention, the solder joint metal film is simultaneously formed on the front surface electrode and the back surface electrode of the semiconductor substrate. Therefore, the stress generated by the solder joint metal film formed on the front electrode and the stress generated by the solder joint metal film formed on the back electrode are offset. Thereby, the curvature of a semiconductor substrate can be suppressed. In addition, the zincate process is performed on the front surface electrode of the semiconductor substrate before the electroless plating process. For this reason, the adhesion between the front surface electrode and the solder-bonded metal film is improved. Thereby, at the time of mounting by solder bonding, it is possible to prevent the front surface electrode from being peeled off from the solder bonding portion of the semiconductor device on which the semiconductor substrate is mounted. In addition, a first metal film and a second metal film are sequentially stacked as the back electrode of the semiconductor substrate. By forming the second metal film on the surface layer of the back electrode of the semiconductor substrate, in the electroless plating process, nickel is continuously deposited in the plating tank, and a solder-bonded metal film is easily formed. . Further, in the etching of the zincate process, even if the unevenness reaching the lower layer occurs on the surface of the second metal film, the etching can be stopped at the first metal film that is the lower layer of the second metal film. For this reason, the solder-bonded metal film is in close contact with the first metal film, and thus does not come into contact with the semiconductor substrate having low adhesion. Thereby, the adhesive force of a semiconductor substrate and a back surface electrode improves, and it can prevent that a back surface electrode peels from a semiconductor substrate.
また、上述した請求項７または８の発明によれば、半導体基板の裏面電極の表面層にアルミニウムを主成分とする膜が形成される。そのため、無電解めっき処理の前処理として、半導体基板の裏面電極にもジンケート処理を行うことで、はんだ接合金属膜が形成されやすくなる。また、ダブルジンケート処理を行うに際し、半導体基板のおもて面電極および裏面電極の両面に同時に行うことができる。
Further, according to the above-described invention of claim 7 or 8, the film mainly composed of aluminum is formed on the surface layer of the back electrode of the semiconductor substrate. Therefore, as a pretreatment for the electroless plating treatment, a solder joint metal film is easily formed by performing a zincate treatment on the back electrode of the semiconductor substrate. Moreover, when performing a double zincate process, it can carry out simultaneously on both the front surface electrode and back surface electrode of a semiconductor substrate.
本発明にかかる半導体装置の製造方法によれば、表裏両面に電極を有する半導体装置において、半導体基板の反りを抑制することができるという効果を奏する。また、半導体装置をはんだ接合により実装するに際し、電極として積層された金属膜が剥離しにくくすることができるという効果を奏する。
According to the method for manufacturing a semiconductor device according to the present invention, it is possible to suppress warpage of the semiconductor substrate in a semiconductor device having electrodes on both the front and back surfaces. In addition, when the semiconductor device is mounted by soldering, the metal film stacked as an electrode can be hardly peeled off.
以下に添付図面を参照して、この発明にかかる半導体装置およびその製造方法の好適な実施の形態を詳細に説明する。なお、以下の実施の形態の説明およびすべての添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。
Hereinafter, preferred embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and all the attached drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.
（実施の形態１）
図１は、本発明にかかる半導体装置の製造過程を示すフローチャートである。図１２に示す半導体装置を例に説明する。まず、図１に示すように、半導体基板１のおもて面にデバイスの表面構造を形成する（ステップＳ１）。この工程で、エミッタ電極６などの、おもて面電極が形成される。ついで、半導体基板１の裏面全体にバックグラインドを行って、例えば１６０μｍの厚さになるまで半導体基板１を薄くする（ステップＳ２）。さらに、半導体基板１の裏面にエッチング処理を行い、半導体基板１を、例えば２０μｍ薄くする（ステップＳ３）。ついで、薄膜化した半導体基板１の裏面に、例えば、リンおよびボロンを順次イオン注入して不純物注入層を形成する（ステップＳ４）。ついで、ステップＳ４で形成された不純物注入層に活性化熱処理を行うことで、ｎバッファ層１０およびｐ+コレクタ層８を形成する（ステップＳ５）。ついで、ｐ+コレクタ層８の表面の自然酸化膜を希フッ酸で除去する（ステップＳ６）。その後、チタン、ニッケルを蒸着またはスパッタで順次積層する（ステップＳ７）。この工程で、裏面電極が形成される。ついで、無電解ニッケルめっき処理および置換金めっき処理を連続して行い、半導体基板１のおもて面電極および裏面電極の両面に、同時にニッケルめっき膜および置換金めっき膜を形成する（ステップＳ８）。この工程で、コレクタ電極９が形成される。 (Embodiment 1)
FIG. 1 is a flowchart showing a manufacturing process of a semiconductor device according to the present invention. The semiconductor device shown in FIG. 12 will be described as an example. First, as shown in FIG. 1, the surface structure of the device is formed on the front surface of the semiconductor substrate 1 (step S1). In this step, the front surface electrode such as theemitter electrode 6 is formed. Next, back grinding is performed on the entire back surface of the semiconductor substrate 1, and the semiconductor substrate 1 is thinned to a thickness of 160 μm, for example (step S2). Further, an etching process is performed on the back surface of the semiconductor substrate 1 to make the semiconductor substrate 1 thinner by, for example, 20 μm (step S3). Next, an impurity implantation layer is formed on the back surface of the thinned semiconductor substrate 1 by sequentially implanting, for example, phosphorus and boron (step S4). Next, an activation heat treatment is performed on the impurity implantation layer formed in step S4, thereby forming the n buffer layer 10 and the p + collector layer 8 (step S5). Next, the natural oxide film on the surface of the p + collector layer 8 is removed with dilute hydrofluoric acid (step S6). Thereafter, titanium and nickel are sequentially stacked by vapor deposition or sputtering (step S7). In this step, the back electrode is formed. Next, the electroless nickel plating process and the displacement gold plating process are continuously performed, and a nickel plating film and a displacement gold plating film are simultaneously formed on both the front surface electrode and the back surface electrode of the semiconductor substrate 1 (step S8). . In this step, the collector electrode 9 is formed.
図１は、本発明にかかる半導体装置の製造過程を示すフローチャートである。図１２に示す半導体装置を例に説明する。まず、図１に示すように、半導体基板１のおもて面にデバイスの表面構造を形成する（ステップＳ１）。この工程で、エミッタ電極６などの、おもて面電極が形成される。ついで、半導体基板１の裏面全体にバックグラインドを行って、例えば１６０μｍの厚さになるまで半導体基板１を薄くする（ステップＳ２）。さらに、半導体基板１の裏面にエッチング処理を行い、半導体基板１を、例えば２０μｍ薄くする（ステップＳ３）。ついで、薄膜化した半導体基板１の裏面に、例えば、リンおよびボロンを順次イオン注入して不純物注入層を形成する（ステップＳ４）。ついで、ステップＳ４で形成された不純物注入層に活性化熱処理を行うことで、ｎバッファ層１０およびｐ+コレクタ層８を形成する（ステップＳ５）。ついで、ｐ+コレクタ層８の表面の自然酸化膜を希フッ酸で除去する（ステップＳ６）。その後、チタン、ニッケルを蒸着またはスパッタで順次積層する（ステップＳ７）。この工程で、裏面電極が形成される。ついで、無電解ニッケルめっき処理および置換金めっき処理を連続して行い、半導体基板１のおもて面電極および裏面電極の両面に、同時にニッケルめっき膜および置換金めっき膜を形成する（ステップＳ８）。この工程で、コレクタ電極９が形成される。 (Embodiment 1)
FIG. 1 is a flowchart showing a manufacturing process of a semiconductor device according to the present invention. The semiconductor device shown in FIG. 12 will be described as an example. First, as shown in FIG. 1, the surface structure of the device is formed on the front surface of the semiconductor substrate 1 (step S1). In this step, the front surface electrode such as the
図２～図４は、実施の形態１にかかる半導体装置の製造過程を示す断面図である。上述したステップＳ１～Ｓ３までの工程において、図２に示すように、半導体基板１の表面層に、図示省略したベース領域およびエミッタ領域が形成される。そして、デバイスの表面構造が形成された半導体基板１のおもて面に、層間絶縁膜７が形成される。さらに、層間絶縁膜７の表面に、おもて面電極として、アルミニウムを主成分としたエミッタ電極（以下、アルミニウム電極とする）６が形成される。このとき、層間絶縁膜７は、半導体基板１のおもて面に形成され図示省略するゲート電極を覆うように形成される。そのため、半導体基板１のおもて面には、層間絶縁膜７が形成される部分と、層間絶縁膜７が形成されずに、ベース領域およびエミッタ領域の表面層の一部が露出する部分とで形成される凹凸が生じる。これにより、アルミニウム電極６は、ベース領域およびエミッタ領域の一部と接触して形成される。そして、アルミニウム電極６の表面には、半導体基板１のおもて面の凹凸に応じた凹凸が生じる。なお、上述したステップＳ３のエッチング処理では、バックグラインド工程によるダメージ層を除去することができる。エッチングの方法としては、例えば、ドライエッチングやスピンエッチングが用いられる。
2 to 4 are sectional views showing the manufacturing process of the semiconductor device according to the first embodiment. In the above-described steps S1 to S3, a base region and an emitter region (not shown) are formed in the surface layer of the semiconductor substrate 1 as shown in FIG. Then, an interlayer insulating film 7 is formed on the front surface of the semiconductor substrate 1 on which the device surface structure is formed. Further, an emitter electrode 6 (hereinafter referred to as an aluminum electrode) 6 mainly composed of aluminum is formed on the surface of the interlayer insulating film 7 as a front surface electrode. At this time, the interlayer insulating film 7 is formed on the front surface of the semiconductor substrate 1 so as to cover a gate electrode (not shown). Therefore, a portion where the interlayer insulating film 7 is formed on the front surface of the semiconductor substrate 1 and a portion where a part of the surface layer of the base region and the emitter region is exposed without the interlayer insulating film 7 being formed. The unevenness formed by Thereby, the aluminum electrode 6 is formed in contact with a part of the base region and the emitter region. Then, unevenness corresponding to the unevenness of the front surface of the semiconductor substrate 1 occurs on the surface of the aluminum electrode 6. In the above-described etching process in step S3, the damaged layer due to the back grinding process can be removed. As an etching method, for example, dry etching or spin etching is used.
上述したステップＳ４～Ｓ７までの工程において、半導体基板１の裏面に、図示省略するバッファ層およびコレクタ層が形成される。そして、図３に示すように、半導体基板１の裏面に、裏面電極として、チタン膜１２およびニッケル膜１３が順次積層される。チタン膜１２およびニッケル膜１３の各膜厚は、例えば０．２μｍ、０．７μｍとする。チタン膜１２は、第１の金属膜に相当する。ニッケル膜１３は、第２の金属膜に相当する。
In the steps S4 to S7 described above, a buffer layer and a collector layer (not shown) are formed on the back surface of the semiconductor substrate 1. As shown in FIG. 3, a titanium film 12 and a nickel film 13 are sequentially stacked on the back surface of the semiconductor substrate 1 as a back electrode. The film thicknesses of the titanium film 12 and the nickel film 13 are, for example, 0.2 μm and 0.7 μm. The titanium film 12 corresponds to a first metal film. The nickel film 13 corresponds to a second metal film.
上述したステップＳ８の工程において、図４に示すように、アルミニウム電極６およびニッケル膜（図３のニッケル膜１３）の表面に、同時にニッケルめっき膜１４が形成される。そして、そのニッケルめっき膜１４の表面に置換金めっき膜１５が形成される。このとき、半導体基板１のおもて面において、アルミニウム電極６の表面へのニッケルめっき膜１４の密着性を改善するために、無電解ニッケルめっき処理の前処理として、アルミニウム電極６の表面にダブルジンケート処理を行う。ダブルジンケート処理については後述する。ニッケルめっき膜１４および置換金めっき膜１５の膜厚は、例えば、５μｍ、０．０３μｍとする。これにより、半導体基板１の裏面に、裏面電極（チタン膜１２および図３のニッケル膜１３）、ニッケルめっき膜１４および置換金めっき膜１５が積層されてなるコレクタ電極９（図１２参照）が形成される。ニッケルめっき膜１４は、はんだ接合金属膜に相当する。置換金めっき膜１５は、保護金属膜に相当する。
In the step S8 described above, as shown in FIG. 4, a nickel plating film 14 is simultaneously formed on the surfaces of the aluminum electrode 6 and the nickel film (nickel film 13 in FIG. 3). Then, a displacement gold plating film 15 is formed on the surface of the nickel plating film 14. At this time, in order to improve the adhesion of the nickel plating film 14 to the surface of the aluminum electrode 6 on the front surface of the semiconductor substrate 1, as a pretreatment of the electroless nickel plating treatment, the surface of the aluminum electrode 6 is doubled. Perform zincate treatment. The double zincate process will be described later. The film thicknesses of the nickel plating film 14 and the displacement gold plating film 15 are, for example, 5 μm and 0.03 μm. As a result, the collector electrode 9 (see FIG. 12) formed by laminating the back electrode (titanium film 12 and the nickel film 13 in FIG. 3), the nickel plating film 14 and the displacement gold plating film 15 is formed on the back surface of the semiconductor substrate 1. Is done. The nickel plating film 14 corresponds to a soldered metal film. The displacement gold plating film 15 corresponds to a protective metal film.
チタン膜１２を形成することにより、半導体基板１と裏面電極との密着性を向上させることができる。その理由は、次に示すとおりである。図５および図６は、実施の形態１にかかる半導体装置の裏面電極について示す断面図である。上述したステップＳ７の工程により、半導体基板１の裏面には、図５に示すように、裏面電極として、チタン膜１２およびニッケル膜１３が積層される。その後、ダブルジンケート処理のエッチングによって、ニッケル膜１３の表面に、下層に達する凹凸が生じたとしても、ニッケル膜１３と半導体基板１との間にあるチタン膜１２でエッチングを止めることができる。これにより、半導体基板１が露出するのを防ぐことができる。そのため、図６に示すように、凹凸が生じたニッケル膜１３の表面にニッケルめっき膜１４が形成されたとしても、ニッケルめっき膜１４は、密着力の低い半導体基板１とは接触せずに、チタン膜１２と密着する。これにより、半導体基板１と裏面電極との密着力が向上し、半導体基板１から、裏面電極および各めっき膜が積層されてなるコレクタ電極９が剥離しにくくなる。本実施の形態１ではチタン膜１２を形成しているが、チタン膜の代わりにモリブデン（Ｍｏ）膜を形成しても同様の効果が得られる。つまり、第１の金属膜に相当する金属膜は、チタン膜でもよいし、モリブデン膜でもよいし、無電解めっき処理の前処理として行われる例えば脱脂処理、アルカリや酸などによるエッチング、およびジンケート処理により溶解しにくい金属であれば、チタン膜やモリブデン膜以外の金属膜で形成されていても良い。
By forming the titanium film 12, the adhesion between the semiconductor substrate 1 and the back electrode can be improved. The reason is as follows. 5 and 6 are cross-sectional views illustrating the back electrode of the semiconductor device according to the first embodiment. As a result of the above-described step S7, the titanium film 12 and the nickel film 13 are laminated on the back surface of the semiconductor substrate 1 as the back surface electrodes as shown in FIG. Thereafter, even if the surface of the nickel film 13 is uneven due to the double zincate etching, the etching can be stopped at the titanium film 12 between the nickel film 13 and the semiconductor substrate 1. Thereby, it is possible to prevent the semiconductor substrate 1 from being exposed. Therefore, as shown in FIG. 6, even if the nickel plating film 14 is formed on the surface of the nickel film 13 with the unevenness, the nickel plating film 14 is not in contact with the semiconductor substrate 1 with low adhesion. Adheres to the titanium film 12. Thereby, the adhesive force between the semiconductor substrate 1 and the back electrode is improved, and the collector electrode 9 formed by laminating the back electrode and each plating film is hardly peeled from the semiconductor substrate 1. Although the titanium film 12 is formed in the first embodiment, the same effect can be obtained by forming a molybdenum (Mo) film instead of the titanium film. That is, the metal film corresponding to the first metal film may be a titanium film, a molybdenum film, or a degreasing process, an etching with an alkali or an acid, and a zincate process performed as a pretreatment of the electroless plating process. As long as it is a metal that is difficult to dissolve, it may be formed of a metal film other than a titanium film or a molybdenum film.
また、チタン膜１２の膜厚は、０．２μｍ以上である必要がある。その理由は、次に示すとおりである。チタン膜１２の膜厚が０．２μｍ以下の場合、チタン膜１２でエッチングを止めることができず、半導体基板１と裏面電極との密着力が低下する。そのため、はんだ接合による実装時の熱ストレスによって、半導体基板１から裏面電極が剥離してしまうことになるからである。
Further, the thickness of the titanium film 12 needs to be 0.2 μm or more. The reason is as follows. When the thickness of the titanium film 12 is 0.2 μm or less, the etching cannot be stopped at the titanium film 12, and the adhesion between the semiconductor substrate 1 and the back electrode is reduced. Therefore, the back electrode is peeled off from the semiconductor substrate 1 due to thermal stress during mounting by solder bonding.
また、ニッケル膜１３を形成することにより、ニッケルめっき膜１４の析出を促進させることができる。ニッケル膜１３により、めっき槽の中でニッケルの連続的な析出が始まり、ニッケルめっき膜１４が形成されやすくなる。ニッケル膜１３に代えて、アルミニウム膜、アルミニウムシリコン膜または亜鉛（Ｚｎ）膜を形成しても同様の効果が得られる。つまり、第２の金属膜に相当する金属膜は、ニッケル膜でもよいし、アルミニウム膜、アルミニウムシリコン膜または亜鉛膜でもよいし、めっき槽中の、はんだ接合金属膜となる物質と酸化還元反応が起こりやすい金属であれば、ニッケル膜やアルミニウム膜、アルミニウムシリコン膜、亜鉛膜以外の金属膜で形成されていても良い。
Further, by forming the nickel film 13, the deposition of the nickel plating film 14 can be promoted. The nickel film 13 causes the continuous deposition of nickel in the plating tank to facilitate the formation of the nickel plating film 14. Similar effects can be obtained by forming an aluminum film, an aluminum silicon film or a zinc (Zn) film in place of the nickel film 13. In other words, the metal film corresponding to the second metal film may be a nickel film, an aluminum film, an aluminum silicon film, or a zinc film, and a redox reaction with a substance that becomes a solder joint metal film in the plating tank. As long as it is a metal that easily occurs, it may be formed of a metal film other than a nickel film, an aluminum film, an aluminum silicon film, or a zinc film.
また、ニッケルめっき膜１４を形成することにより、裏面電極をはんだ結合することができる。ニッケルめっき膜１４に代えて、ニッケル合金で形成されためっき膜としても良い。ニッケル合金の一例として、リン（Ｐ）やボロン（Ｂ）を含有するニッケル合金が挙げられる。つまり、はんだ接合金属膜に相当する金属膜は、はんだが接着されやすい金属で形成されていれば良い。また、置換金めっき膜１５を形成することにより、ニッケルめっき膜１４の表面酸化を防止することができる。このような保護金属膜に相当する金属膜は、金めっき膜に限らず、その下層である金属膜が酸化することを防止する金属で形成されていれば良い。
Also, the back electrode can be soldered by forming the nickel plating film 14. Instead of the nickel plating film 14, a plating film formed of a nickel alloy may be used. An example of the nickel alloy is a nickel alloy containing phosphorus (P) or boron (B). That is, the metal film corresponding to the solder-bonded metal film may be formed of a metal to which solder is easily bonded. Further, by forming the replacement gold plating film 15, the surface oxidation of the nickel plating film 14 can be prevented. The metal film corresponding to such a protective metal film is not limited to the gold plating film, and may be formed of a metal that prevents the underlying metal film from being oxidized.
上述したダブルジンケート処理の手順について説明する。この処理は、アルミニウム電極６の表面に行っている。まず、脱脂処理を行う。ついで、エッチング処理の後に第１のジンケート処理を行う。ついで、硝酸処理を行った後、最後に第２のジンケート処理を行う。ある処理と次の処理の間には、半導体基板１のおもて面電極の表面を水で洗う処理が含まれる。ダブルジンケート処理を行うことで、アルミニウム電極６のアルミニウムが亜鉛に置換され、アルミニウム電極６の表面に亜鉛膜が形成される。その後続けて無電解めっき処理を行うと、亜鉛膜がニッケルに置換され、これに引き続いてニッケルが連続的に析出されてニッケルめっき膜１４が形成される。つまり、ダブルジンケート処理によって、ニッケルめっき膜１４を確実にかつ強固な密着力でアルミニウム電極６の表面に形成することができる。なお、１回のジンケート処理でも十分な密着力を得ることができる。
The procedure for the double zincate process described above will be described. This treatment is performed on the surface of the aluminum electrode 6. First, a degreasing process is performed. Next, a first zincate process is performed after the etching process. Next, after the nitric acid treatment, a second zincate treatment is finally performed. Between a certain process and the next process, the process which wash | cleans the surface of the front surface electrode of the semiconductor substrate 1 with water is included. By performing the double zincate treatment, aluminum in the aluminum electrode 6 is replaced with zinc, and a zinc film is formed on the surface of the aluminum electrode 6. When the electroless plating process is subsequently performed, the zinc film is replaced with nickel, and subsequently, nickel is continuously deposited to form the nickel plating film 14. That is, the nickel plating film 14 can be reliably and firmly formed on the surface of the aluminum electrode 6 by the double zincate process. In addition, sufficient adhesion can be obtained even with a single zincate treatment.
以上、説明したように、実施の形態１によれば、半導体基板１のアルミニウム電極６および裏面電極に、同時にニッケルめっき膜１４が形成される。そのため、アルミニウム電極６に形成されたニッケルめっき膜１４により生じる応力と、裏面電極に形成されたニッケルめっき膜１４により生じる応力とが相殺される。これにより、半導体基板１の反りを抑制することができる。また、無電解めっき処理を行う前に、半導体基板１のおもて面のアルミニウム電極６にダブルジンケート処理を行っている。そのため、アルミニウム電極６とニッケルめっき膜１４との密着力が向上する。これにより、はんだ接合による実装時に、この半導体基板１が実装された半導体装置のはんだ接合部からおもて面電極が剥離することを防ぐことができる。また、半導体基板１の裏面に、裏面電極として、チタン膜１２およびニッケル膜１３が順次積層される。半導体基板１の裏面の表面層にニッケル膜１３が形成されることで、無電解めっき処理において、めっき槽の中でニッケルの連続的な析出が起き、ニッケルめっき膜１４が形成されやすくなる。また、ダブルジンケート処理のエッチングにおいて、ニッケル膜１３の表面に下層まで達する凹凸が生じたとしても、ニッケル膜１３の下層であるチタン膜１２でエッチングを止めることができる。そのため、ニッケルめっき膜１４は、チタン膜１２と密着するので、密着力の低い半導体基板１とは接触しない。これにより、半導体基板１と裏面電極との密着力が向上し、半導体基板１から、裏面電極と各めっき膜とが積層されてなるコレクタ電極９が剥離することを防止することができる。したがって、表裏両面に電極を有する半導体基板１を、高い良品率で製造することができる。
As described above, according to the first embodiment, the nickel plating film 14 is simultaneously formed on the aluminum electrode 6 and the back electrode of the semiconductor substrate 1. Therefore, the stress generated by the nickel plating film 14 formed on the aluminum electrode 6 and the stress generated by the nickel plating film 14 formed on the back electrode are offset. Thereby, the curvature of the semiconductor substrate 1 can be suppressed. Further, before the electroless plating process, the double zincate process is performed on the aluminum electrode 6 on the front surface of the semiconductor substrate 1. Therefore, the adhesion between the aluminum electrode 6 and the nickel plating film 14 is improved. Thereby, it is possible to prevent the front electrode from being peeled off from the solder joint portion of the semiconductor device on which the semiconductor substrate 1 is mounted at the time of mounting by solder joint. Further, a titanium film 12 and a nickel film 13 are sequentially stacked on the back surface of the semiconductor substrate 1 as a back electrode. By forming the nickel film 13 on the surface layer on the back surface of the semiconductor substrate 1, in the electroless plating process, nickel is continuously deposited in the plating tank, and the nickel plating film 14 is easily formed. Further, in the etching of the double zincate process, even if irregularities reaching the lower layer occur on the surface of the nickel film 13, the etching can be stopped at the titanium film 12 that is the lower layer of the nickel film 13. Therefore, since the nickel plating film 14 is in close contact with the titanium film 12, it is not in contact with the semiconductor substrate 1 having low adhesion. Thereby, the adhesive force between the semiconductor substrate 1 and the back electrode is improved, and the collector electrode 9 formed by laminating the back electrode and each plating film can be prevented from peeling from the semiconductor substrate 1. Therefore, the semiconductor substrate 1 which has an electrode on both front and back surfaces can be manufactured with a high yield rate.
（実施の形態２）
実施の形態２にかかる半導体装置の製造方法について説明する。実施の形態２の説明および添付図面について、実施の形態１と重複する説明は省略する。実施の形態２では、実施の形態１と同様に、図１に示すフローチャートにしたがい、ステップＳ１～ステップＳ８の工程を行う。これにより、半導体基板１の表裏両面に、同時に無電解ニッケルめっき処理および置換金めっき処理を連続して行う。また、実施の形態２において、ステップＳ７の工程で半導体基板１の裏面に蒸着またはスパッタで順次積層する金属は、チタン、アルミニウムである。 (Embodiment 2)
A method for manufacturing the semiconductor device according to the second embodiment will be described. Regarding the description of the second embodiment and the accompanying drawings, the description overlapping with that of the first embodiment is omitted. In the second embodiment, similarly to the first embodiment, the steps S1 to S8 are performed according to the flowchart shown in FIG. Thereby, the electroless nickel plating process and the displacement gold plating process are continuously performed on both the front and back surfaces of thesemiconductor substrate 1 simultaneously. In the second embodiment, the metal that is sequentially laminated on the back surface of the semiconductor substrate 1 by vapor deposition or sputtering in the step S7 is titanium or aluminum.
実施の形態２にかかる半導体装置の製造方法について説明する。実施の形態２の説明および添付図面について、実施の形態１と重複する説明は省略する。実施の形態２では、実施の形態１と同様に、図１に示すフローチャートにしたがい、ステップＳ１～ステップＳ８の工程を行う。これにより、半導体基板１の表裏両面に、同時に無電解ニッケルめっき処理および置換金めっき処理を連続して行う。また、実施の形態２において、ステップＳ７の工程で半導体基板１の裏面に蒸着またはスパッタで順次積層する金属は、チタン、アルミニウムである。 (Embodiment 2)
A method for manufacturing the semiconductor device according to the second embodiment will be described. Regarding the description of the second embodiment and the accompanying drawings, the description overlapping with that of the first embodiment is omitted. In the second embodiment, similarly to the first embodiment, the steps S1 to S8 are performed according to the flowchart shown in FIG. Thereby, the electroless nickel plating process and the displacement gold plating process are continuously performed on both the front and back surfaces of the
図７および図８は、実施の形態２にかかる半導体装置の製造過程を示す断面図である。上述したステップＳ１～Ｓ３までの工程では、実施の形態１と同様に、半導体基板１の表面層に、図示省略したベース領域およびエミッタ領域が形成される。そして、図２に示すように、半導体基板１のおもて面に、層間絶縁膜７およびアルミニウム電極６が形成される。
7 and 8 are cross-sectional views showing the manufacturing process of the semiconductor device according to the second embodiment. In the steps S1 to S3 described above, a base region and an emitter region (not shown) are formed in the surface layer of the semiconductor substrate 1 as in the first embodiment. Then, as shown in FIG. 2, an interlayer insulating film 7 and an aluminum electrode 6 are formed on the front surface of the semiconductor substrate 1.
上述したステップＳ４～Ｓ７までの工程において、半導体基板１の裏面に、図示省略するバッファ層およびコレクタ層が形成される。そして、図７に示すように、半導体基板１の裏面に、裏面電極として、チタン膜１２およびアルミニウム膜１６が順次積層される。チタン膜１２およびアルミニウム膜１６の各膜厚は、例えば０．２μｍ、２．０μｍとする。アルミニウム膜１６は、第２の金属膜に相当する。
In the steps S4 to S7 described above, a buffer layer and a collector layer (not shown) are formed on the back surface of the semiconductor substrate 1. As shown in FIG. 7, a titanium film 12 and an aluminum film 16 are sequentially stacked on the back surface of the semiconductor substrate 1 as a back electrode. The film thicknesses of the titanium film 12 and the aluminum film 16 are, for example, 0.2 μm and 2.0 μm. The aluminum film 16 corresponds to a second metal film.
上述したステップＳ８の工程において、図８に示すように、アルミニウム電極６およびアルミニウム膜１６の表面に、同時にニッケルめっき膜１４が形成される。そして、そのニッケルめっき膜１４の表面に置換金めっき膜１５が形成される。このとき、アルミニウム電極６の表面に、無電解ニッケルめっき処理の前処理としてダブルジンケート処理を行う。その理由は、実施の形態１と同様である。また、ニッケルめっき膜１４および置換金めっき膜１５の膜厚は、実施の形態１と同様である。これにより、半導体基板１の裏面に、裏面電極（チタン膜１２およびアルミニウム膜１６）、ニッケルめっき膜１４および置換金めっき膜１５が積層されてなるコレクタ電極９（図１２参照）が形成される。
In the step S8 described above, as shown in FIG. 8, the nickel plating film 14 is simultaneously formed on the surfaces of the aluminum electrode 6 and the aluminum film 16. Then, a displacement gold plating film 15 is formed on the surface of the nickel plating film 14. At this time, a double zincate treatment is performed on the surface of the aluminum electrode 6 as a pretreatment for the electroless nickel plating treatment. The reason is the same as in the first embodiment. The thicknesses of the nickel plating film 14 and the displacement gold plating film 15 are the same as those in the first embodiment. As a result, the collector electrode 9 (see FIG. 12) is formed on the back surface of the semiconductor substrate 1 by laminating the back electrode (titanium film 12 and aluminum film 16), the nickel plating film 14 and the displacement gold plating film 15.
アルミニウム膜１６を形成することにより、半導体基板１の表裏両面を同じ基板条件に近づけることができる。アルミニウム膜１６に代えて、アルミニウムシリコン膜または亜鉛膜を形成しても良い。半導体基板１の裏面にアルミニウム膜１６を形成することで、半導体基板１の裏面にも、半導体基板１のおもて面と同様にダブルジンケート処理を行う。その理由は、アルミニウム電極６と同様である。そのため、ダブルジンケート処理および無電解めっき処理を、半導体基板１の表裏両面に同時に行うことができる。これにより、半導体基板１の反りを抑制することができる。
By forming the aluminum film 16, both the front and back surfaces of the semiconductor substrate 1 can be brought close to the same substrate conditions. Instead of the aluminum film 16, an aluminum silicon film or a zinc film may be formed. By forming the aluminum film 16 on the back surface of the semiconductor substrate 1, the double zincate process is performed on the back surface of the semiconductor substrate 1 in the same manner as the front surface of the semiconductor substrate 1. The reason is the same as that of the aluminum electrode 6. Therefore, the double zincate process and the electroless plating process can be simultaneously performed on both the front and back surfaces of the semiconductor substrate 1. Thereby, the curvature of the semiconductor substrate 1 can be suppressed.
また、このような構成で裏面電極を形成することで、実施の形態１と同様に、半導体基板１と裏面電極との密着性を向上させることができる。その理由は、次に示すとおりである。図９および図１０は、実施の形態２にかかる半導体装置の裏面電極について示す断面図である。上述したステップＳ７の工程により、半導体基板１の裏面には、図９に示すように、裏面電極として、チタン膜１２およびアルミニウム膜１６が積層される。その後、ダブルジンケート処理中のエッチングによって、アルミニウム膜１６の表面に下層に達する凹凸が生じたとしても、アルミニウム膜１６と半導体基板１との間にあるチタン膜１２でエッチングを止めることができる。そのため、図１０に示すように、凹凸が生じたアルミニウム膜１６の表面にニッケルめっき膜１４が形成されたとしても、ニッケルめっき膜１４は、密着力の低い半導体基板１とは接触せずに、チタン膜１２と密着する。これにより、半導体基板１と裏面電極との密着力が向上し、半導体基板１から、裏面電極と各めっき膜とが積層されてなるコレクタ電極９が剥離しにくくなる。また、本実施の形態２においても、実施の形態１と同様に、チタン膜の代わりにモリブデン（Ｍｏ）膜を形成してもよい。
Further, by forming the back electrode with such a configuration, the adhesion between the semiconductor substrate 1 and the back electrode can be improved as in the first embodiment. The reason is as follows. 9 and 10 are cross-sectional views illustrating the back electrode of the semiconductor device according to the second embodiment. As a result of the above-described step S7, the titanium film 12 and the aluminum film 16 are laminated on the back surface of the semiconductor substrate 1 as a back electrode, as shown in FIG. Thereafter, even if the surface of the aluminum film 16 has irregularities reaching the lower layer due to etching during the double zincate process, the etching can be stopped at the titanium film 12 between the aluminum film 16 and the semiconductor substrate 1. Therefore, as shown in FIG. 10, even if the nickel plating film 14 is formed on the surface of the aluminum film 16 with the unevenness, the nickel plating film 14 does not come into contact with the semiconductor substrate 1 with low adhesion. Adheres to the titanium film 12. Thereby, the adhesive force between the semiconductor substrate 1 and the back electrode is improved, and the collector electrode 9 formed by laminating the back electrode and each plating film is hardly peeled from the semiconductor substrate 1. Also in the second embodiment, a molybdenum (Mo) film may be formed instead of the titanium film, as in the first embodiment.
以上、説明したように、実施の形態２によれば、実施の形態１と同様の効果が得られる。また、半導体基板１の裏面の表面層にアルミニウム膜１６が形成されるため、半導体基板１の裏面にもダブルジンケート処理を行うことで、無電解めっき処理において、ニッケルめっき膜１４が形成されやすくなる。さらに、無電解めっき処理を行う直前には、半導体基板１の表裏両面にアルミニウム膜が形成されていることになり、ダブルジンケート処理を行うに際し、半導体基板１の表裏両面に同時に行うことができる。これにより、半導体基板１の反りを抑制することができる。したがって、表裏両面に電極を有する半導体基板１を、高い良品率で製造することができる。
As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained. Further, since the aluminum film 16 is formed on the surface layer on the back surface of the semiconductor substrate 1, the nickel plating film 14 is easily formed in the electroless plating process by performing the double zincate process on the back surface of the semiconductor substrate 1. . Further, immediately before the electroless plating process is performed, aluminum films are formed on both the front and back surfaces of the semiconductor substrate 1, so that the double zincate process can be performed simultaneously on both the front and back surfaces of the semiconductor substrate 1. Thereby, the curvature of the semiconductor substrate 1 can be suppressed. Therefore, the semiconductor substrate 1 which has an electrode on both front and back surfaces can be manufactured with a high yield rate.
上述した各実施の形態では、電極の表面に形成されるめっき膜を、ニッケルおよび金を用いて形成しているが、これに限らず、電極表面に均一な膜厚でめっき膜を形成することができる金属であれば適用可能である。また、電極の成分である金属と比べて、はんだに対する濡れ性が良いめっき膜を形成することができる金属であればめっき膜として適用可能である。そのような金属として、例えば、コバルト（Ｃｏ），パラジウム（Ｐｄ），銅（Ｃｕ），銀（Ａｇ），白金（Ｐｔ），スズ（Ｓｎ）などが適用可能である。
In each embodiment described above, the plating film formed on the surface of the electrode is formed using nickel and gold. However, the present invention is not limited to this, and the plating film is formed with a uniform film thickness on the electrode surface. Any metal that can be applied is applicable. Further, any metal that can form a plating film having better wettability with respect to solder than a metal that is a component of an electrode can be applied as a plating film. As such a metal, for example, cobalt (Co), palladium (Pd), copper (Cu), silver (Ag), platinum (Pt), tin (Sn), and the like are applicable.
以上において本発明は、上述した実施の形態に限らず、裏面電極として複数の金属膜を形成することが可能である。例えば、半導体基板１とチタン膜１２との間に、裏面電極として、アルミニウムシリコン膜を形成してもよい。その際、アルミニウムシリコン膜は、半導体基板１の表面に、蒸着またはスパッタにより形成される。アルミニウムシリコン膜を形成することにより、はんだ接合における実装に際し、基板温度が上昇することにより発生するアルミスパイクの影響を低減させることができる。特に、半導体基板１中のｎバッファ層が１μｍ以下の半導体装置において、その効果が大きく発揮される。このとき、アルミニウムシリコン膜の膜厚は、例えば０．５μｍとする。また、アルミニウムシリコン膜のシリコン濃度は、０．５ｗｔ％以上２ｗｔ％以下であるのがよく、特に１ｗｔ％以下であるのが好ましい。
As described above, the present invention is not limited to the above-described embodiment, and a plurality of metal films can be formed as the back electrode. For example, an aluminum silicon film may be formed as a back electrode between the semiconductor substrate 1 and the titanium film 12. At that time, the aluminum silicon film is formed on the surface of the semiconductor substrate 1 by vapor deposition or sputtering. By forming the aluminum silicon film, it is possible to reduce the influence of aluminum spikes that are generated when the substrate temperature rises during mounting in solder bonding. In particular, the effect is greatly exhibited in a semiconductor device in which the n buffer layer in the semiconductor substrate 1 is 1 μm or less. At this time, the film thickness of the aluminum silicon film is, for example, 0.5 μm. The silicon concentration of the aluminum silicon film is preferably 0.5 wt% or more and 2 wt% or less, and particularly preferably 1 wt% or less.
以上のように、本発明にかかる半導体装置の製造方法は、デバイス厚の薄い半導体装置を製造するのに有用であり、特に、汎用インバータ、ＡＣサーボ、無停電電源（ＵＰＳ）またはスイッチング電源などの産業分野や、電子レンジ、炊飯器またはストロボなどの民生機器分野に用いられるＩＧＢＴ等の電力用半導体装置の製造に適している。
As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a semiconductor device with a thin device thickness. In particular, a general-purpose inverter, AC servo, uninterruptible power supply (UPS), switching power supply, etc. It is suitable for the manufacture of power semiconductor devices such as IGBTs used in the industrial field and consumer electronics fields such as microwave ovens, rice cookers or strobes.
１ 半導体基板
６ アルミニウム電極
７ 層間絶縁膜
１２ チタン膜
１４ ニッケルめっき膜
１５ 置換金めっき膜 DESCRIPTION OFSYMBOLS 1 Semiconductor substrate 6 Aluminum electrode 7 Interlayer insulation film 12 Titanium film 14 Nickel plating film 15 Substitution gold plating film
６ アルミニウム電極
７ 層間絶縁膜
１２ チタン膜
１４ ニッケルめっき膜
１５ 置換金めっき膜 DESCRIPTION OF
Claims (20)
- 半導体基板の第１の主面におもて面電極を有し、かつ前記半導体基板の第２の主面に裏面電極を有する半導体装置を製造するにあたって、
前記裏面電極として、前記第２の主面の表面に第１の金属膜を形成する工程と、
前記裏面電極として、前記第１の金属膜の表面に第２の金属膜を形成する工程と、
湿式めっきの方法により、前記おもて面電極および前記第２の金属膜の表面に、同時にめっき膜を形成するめっき膜形成工程と、
を含むことを特徴とする半導体装置の製造方法。 In manufacturing a semiconductor device having a front electrode on the first main surface of the semiconductor substrate and a back electrode on the second main surface of the semiconductor substrate,
Forming a first metal film on the surface of the second main surface as the back electrode;
Forming a second metal film on the surface of the first metal film as the back electrode;
A plating film forming step of simultaneously forming a plating film on the surface of the front surface electrode and the second metal film by a wet plating method;
A method for manufacturing a semiconductor device, comprising: - 前記第１の金属膜を形成する前に、
前記裏面電極として、前記第２の主面の表面にアルミニウムを主成分とする金属膜を形成する工程、
をさらに含むことを特徴とする請求項１に記載の半導体装置の製造方法。 Before forming the first metal film,
Forming a metal film mainly composed of aluminum on the surface of the second main surface as the back electrode;
The method of manufacturing a semiconductor device according to claim 1, further comprising: - 前記第１の金属膜は、前記第２の金属膜を溶解し得る処理液に対して不溶性であることを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal film is insoluble in a processing solution capable of dissolving the second metal film.
- 前記めっき膜として、前記第２の金属膜の表面に、はんだ接合金属膜を形成し、前記はんだ接合金属膜の表面に保護金属膜を形成することを特徴とする請求項３に記載の半導体装置の製造方法。 4. The semiconductor device according to claim 3, wherein a solder joint metal film is formed on the surface of the second metal film as the plating film, and a protective metal film is formed on the surface of the solder joint metal film. Manufacturing method.
- 前記第２の金属膜は前記はんだ接合金属膜と同じ物質を主成分とする膜であることを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein the second metal film is a film mainly composed of the same material as the solder joint metal film.
- 前記第２の金属膜はニッケル膜であることを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein the second metal film is a nickel film.
- 前記第２の金属膜はアルミニウムを主成分とする膜であることを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein the second metal film is a film containing aluminum as a main component.
- 前記第２の金属膜はアルミニウム膜であることを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein the second metal film is an aluminum film.
- 前記第２の金属膜はアルミニウムシリコン膜であることを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein the second metal film is an aluminum silicon film.
- 前記第２の金属膜は亜鉛膜であることを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein the second metal film is a zinc film.
- 前記第２の金属膜を形成した後、前記めっき膜形成工程の前に、前記第２の金属膜にジンケート処理を行う裏面活性化工程をさらに含むことを特徴とする請求項７に記載の半導体装置の製造方法。 The semiconductor according to claim 7, further comprising a back surface activation step of performing a zincate process on the second metal film after forming the second metal film and before the plating film forming step. Device manufacturing method.
- 前記はんだ接合金属膜はニッケルで形成されることを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein the solder joint metal film is formed of nickel.
- 前記はんだ接合金属膜はニッケルを主成分とする金属で形成されることを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein the solder joint metal film is formed of a metal having nickel as a main component.
- 前記保護金属膜は金で形成されることを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein the protective metal film is formed of gold.
- 前記第１の金属膜はモリブデン（Ｍｏ）またはチタン（Ｔｉ）で形成されることを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal film is formed of molybdenum (Mo) or titanium (Ti).
- 前記第１の金属膜の膜厚は０．２μｍ以上であることを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the film thickness of the first metal film is 0.2 [mu] m or more.
- 前記おもて面電極はアルミニウムまたはアルミニウム合金で形成されることを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the front surface electrode is formed of aluminum or an aluminum alloy.
- 前記アルミニウム合金はアルミニウムシリコンであることを特徴とする請求項１７に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 17, wherein the aluminum alloy is aluminum silicon.
- 前記第２の金属膜を形成した後、前記めっき膜形成工程の前に、前記おもて面電極にジンケート処理を行うおもて面活性化工程をさらに含むことを特徴とする請求項１７に記載の半導体装置の製造方法。 18. The method according to claim 17, further comprising a front surface activation step of performing a zincate process on the front surface electrode after forming the second metal film and before the plating film formation step. The manufacturing method of the semiconductor device of description.
- 前記湿式めっきの方法は無電解めっきであることを特徴とする請求項１～１９のいずれか一つに記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to any one of claims 1 to 19, wherein the wet plating method is electroless plating.
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