SG11201709420PA - Method for producing soi wafer - Google Patents

Method for producing soi wafer

Info

Publication number
SG11201709420PA
SG11201709420PA SG11201709420PA SG11201709420PA SG11201709420PA SG 11201709420P A SG11201709420P A SG 11201709420PA SG 11201709420P A SG11201709420P A SG 11201709420PA SG 11201709420P A SG11201709420P A SG 11201709420PA SG 11201709420P A SG11201709420P A SG 11201709420PA
Authority
SG
Singapore
Prior art keywords
soi wafer
producing soi
producing
wafer
soi
Prior art date
Application number
SG11201709420PA
Inventor
Isao Yokokawa
Hiroji Aga
Norihiro Kobayashi
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of SG11201709420PA publication Critical patent/SG11201709420PA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
SG11201709420PA 2015-06-15 2016-03-08 Method for producing soi wafer SG11201709420PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015120424A JP6380245B2 (en) 2015-06-15 2015-06-15 Manufacturing method of SOI wafer
PCT/JP2016/001235 WO2016203677A1 (en) 2015-06-15 2016-03-08 Method of manufacturing soi wafer

Publications (1)

Publication Number Publication Date
SG11201709420PA true SG11201709420PA (en) 2017-12-28

Family

ID=57545735

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201709420PA SG11201709420PA (en) 2015-06-15 2016-03-08 Method for producing soi wafer

Country Status (8)

Country Link
US (1) US10204824B2 (en)
EP (1) EP3309820B1 (en)
JP (1) JP6380245B2 (en)
KR (1) KR102327330B1 (en)
CN (1) CN107615445B (en)
SG (1) SG11201709420PA (en)
TW (1) TWI685019B (en)
WO (1) WO2016203677A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6473970B2 (en) * 2015-10-28 2019-02-27 信越半導体株式会社 Manufacturing method of bonded SOI wafer
CN109037031B (en) * 2018-07-11 2021-11-19 华东师范大学 Nickel-doped copper oxide thin film transistor and preparation method thereof
CN110739285A (en) * 2019-10-30 2020-01-31 北京工业大学 Structure and preparation method of silicon-based metal interlayer compound semiconductor wafer
KR102456461B1 (en) 2020-11-26 2022-10-19 현대제철 주식회사 Analysis method and system for micro structures of steel using deep learning
CN112582332A (en) * 2020-12-08 2021-03-30 上海新昇半导体科技有限公司 Silicon-on-insulator structure and method thereof

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (en) 1991-09-18 1993-10-29 Commissariat Energie Atomique PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL.
JPH11307472A (en) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd Soi wafer and manufacture soi by hydrogen ion releasing method
JP2000124092A (en) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd Manufacture of soi wafer by hydrogen-ion implantation stripping method and soi wafer manufactured thereby
JP4304879B2 (en) * 2001-04-06 2009-07-29 信越半導体株式会社 Method for determining the implantation amount of hydrogen ions or rare gas ions
JP4123861B2 (en) * 2002-08-06 2008-07-23 株式会社Ｓｕｍｃｏ Manufacturing method of semiconductor substrate
FR2860842B1 (en) * 2003-10-14 2007-11-02 Tracit Technologies PROCESS FOR PREPARING AND ASSEMBLING SUBSTRATES
JP4603865B2 (en) * 2004-12-01 2010-12-22 信越化学工業株式会社 Manufacturing method of silicon substrate with oxide film and silicon substrate with oxide film
FR2880184B1 (en) * 2004-12-28 2007-03-30 Commissariat Energie Atomique METHOD OF SORTING A STRUCTURE OBTAINED BY ASSEMBLING TWO PLATES
JP2007317988A (en) 2006-05-29 2007-12-06 Shin Etsu Handotai Co Ltd Manufacturing method of laminated wafer
JP2008028070A (en) 2006-07-20 2008-02-07 Sumco Corp Method for manufacturing laminated wafer
JP5245380B2 (en) * 2007-06-21 2013-07-24 信越半導体株式会社 Manufacturing method of SOI wafer
JP5135935B2 (en) 2007-07-27 2013-02-06 信越半導体株式会社 Manufacturing method of bonded wafer
JP5531642B2 (en) 2010-01-22 2014-06-25 信越半導体株式会社 Manufacturing method of bonded wafer
JP5477277B2 (en) * 2010-12-20 2014-04-23 信越半導体株式会社 Manufacturing method of SOI wafer
JP5704039B2 (en) 2011-10-06 2015-04-22 信越半導体株式会社 Manufacturing method of bonded SOI wafer
JP2013143407A (en) * 2012-01-06 2013-07-22 Shin Etsu Handotai Co Ltd Method of manufacturing laminated soi wafer
JP5673572B2 (en) 2012-01-24 2015-02-18 信越半導体株式会社 Manufacturing method of bonded SOI wafer

Also Published As

Publication number Publication date
EP3309820A1 (en) 2018-04-18
US10204824B2 (en) 2019-02-12
JP6380245B2 (en) 2018-08-29
US20180144975A1 (en) 2018-05-24
EP3309820A4 (en) 2019-01-23
EP3309820B1 (en) 2020-01-29
JP2017005201A (en) 2017-01-05
CN107615445B (en) 2020-10-30
KR102327330B1 (en) 2021-11-17
WO2016203677A1 (en) 2016-12-22
TWI685019B (en) 2020-02-11
TW201643938A (en) 2016-12-16
KR20180016394A (en) 2018-02-14
CN107615445A (en) 2018-01-19

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