SG11201709420PA - Method for producing soi wafer - Google Patents

Method for producing soi wafer

Info

Publication number
SG11201709420PA
SG11201709420PA SG11201709420PA SG11201709420PA SG11201709420PA SG 11201709420P A SG11201709420P A SG 11201709420PA SG 11201709420P A SG11201709420P A SG 11201709420PA SG 11201709420P A SG11201709420P A SG 11201709420PA SG 11201709420P A SG11201709420P A SG 11201709420PA
Authority
SG
Singapore
Prior art keywords
soi wafer
producing soi
producing
wafer
soi
Prior art date
Application number
SG11201709420PA
Other languages
English (en)
Inventor
Isao Yokokawa
Hiroji Aga
Norihiro Kobayashi
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of SG11201709420PA publication Critical patent/SG11201709420PA/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/60Wet etching
    • H10P50/64Wet etching of semiconductor materials
    • H10P50/642Chemical etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1924Preparing SOI wafers with separation/delamination along a porous layer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90Thermal treatments, e.g. annealing or sintering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
SG11201709420PA 2015-06-15 2016-03-08 Method for producing soi wafer SG11201709420PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015120424A JP6380245B2 (ja) 2015-06-15 2015-06-15 Soiウェーハの製造方法
PCT/JP2016/001235 WO2016203677A1 (ja) 2015-06-15 2016-03-08 Soiウェーハの製造方法

Publications (1)

Publication Number Publication Date
SG11201709420PA true SG11201709420PA (en) 2017-12-28

Family

ID=57545735

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201709420PA SG11201709420PA (en) 2015-06-15 2016-03-08 Method for producing soi wafer

Country Status (8)

Country Link
US (1) US10204824B2 (https=)
EP (1) EP3309820B1 (https=)
JP (1) JP6380245B2 (https=)
KR (1) KR102327330B1 (https=)
CN (1) CN107615445B (https=)
SG (1) SG11201709420PA (https=)
TW (1) TWI685019B (https=)
WO (1) WO2016203677A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6473970B2 (ja) * 2015-10-28 2019-02-27 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
CN109037031B (zh) * 2018-07-11 2021-11-19 华东师范大学 一种掺镍氧化铜薄膜晶体管及制备方法
CN110739285A (zh) * 2019-10-30 2020-01-31 北京工业大学 硅基金属中间层化合物半导体晶圆的结构及制备方法
JP7354420B2 (ja) * 2020-04-02 2023-10-02 東京エレクトロン株式会社 基板処理方法及び基板処理装置
FR3110282B1 (fr) * 2020-05-18 2022-04-15 Soitec Silicon On Insulator Procédé de fabrication d’un substrat semi-conducteur sur isolant pour applications radiofréquences
KR102456461B1 (ko) 2020-11-26 2022-10-19 현대제철 주식회사 딥러닝을 이용한 철강 미세 조직 분석 방법 및 시스템
CN112582332A (zh) * 2020-12-08 2021-03-30 上海新昇半导体科技有限公司 一种绝缘体上硅结构及其方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH11307472A (ja) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ
JP4304879B2 (ja) * 2001-04-06 2009-07-29 信越半導体株式会社 水素イオンまたは希ガスイオンの注入量の決定方法
JP4123861B2 (ja) * 2002-08-06 2008-07-23 株式会社Sumco 半導体基板の製造方法
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
JP4603865B2 (ja) * 2004-12-01 2010-12-22 信越化学工業株式会社 酸化膜付きシリコン基板の製造方法及び酸化膜付きシリコン基板
FR2880184B1 (fr) * 2004-12-28 2007-03-30 Commissariat Energie Atomique Procede de detourage d'une structure obtenue par assemblage de deux plaques
JP2007317988A (ja) 2006-05-29 2007-12-06 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
JP2008028070A (ja) 2006-07-20 2008-02-07 Sumco Corp 貼り合わせウェーハの製造方法
JP5245380B2 (ja) * 2007-06-21 2013-07-24 信越半導体株式会社 Soiウェーハの製造方法
JP5135935B2 (ja) 2007-07-27 2013-02-06 信越半導体株式会社 貼り合わせウエーハの製造方法
JP5531642B2 (ja) 2010-01-22 2014-06-25 信越半導体株式会社 貼り合わせウェーハの製造方法
JP5477277B2 (ja) * 2010-12-20 2014-04-23 信越半導体株式会社 Soiウェーハの製造方法
JP5704039B2 (ja) * 2011-10-06 2015-04-22 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
JP2013143407A (ja) * 2012-01-06 2013-07-22 Shin Etsu Handotai Co Ltd 貼り合わせsoiウェーハの製造方法
JP5673572B2 (ja) 2012-01-24 2015-02-18 信越半導体株式会社 貼り合わせsoiウェーハの製造方法

Also Published As

Publication number Publication date
CN107615445A (zh) 2018-01-19
EP3309820A4 (en) 2019-01-23
US20180144975A1 (en) 2018-05-24
KR102327330B1 (ko) 2021-11-17
KR20180016394A (ko) 2018-02-14
TW201643938A (zh) 2016-12-16
JP2017005201A (ja) 2017-01-05
WO2016203677A1 (ja) 2016-12-22
CN107615445B (zh) 2020-10-30
US10204824B2 (en) 2019-02-12
EP3309820B1 (en) 2020-01-29
TWI685019B (zh) 2020-02-11
JP6380245B2 (ja) 2018-08-29
EP3309820A1 (en) 2018-04-18

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