KR101607725B1 - 와이드 밴드 갭 반도체를 적층한 복합 기판의 제조 방법 - Google Patents

와이드 밴드 갭 반도체를 적층한 복합 기판의 제조 방법 Download PDF

Info

Publication number
KR101607725B1
KR101607725B1 KR1020117012761A KR20117012761A KR101607725B1 KR 101607725 B1 KR101607725 B1 KR 101607725B1 KR 1020117012761 A KR1020117012761 A KR 1020117012761A KR 20117012761 A KR20117012761 A KR 20117012761A KR 101607725 B1 KR101607725 B1 KR 101607725B1
Authority
KR
South Korea
Prior art keywords
substrate
visible light
ion
handle substrate
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020117012761A
Other languages
English (en)
Korean (ko)
Other versions
KR20110099008A (ko
Inventor
쇼지 아끼야마
Original Assignee
신에쓰 가가꾸 고교 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 신에쓰 가가꾸 고교 가부시끼가이샤 filed Critical 신에쓰 가가꾸 고교 가부시끼가이샤
Publication of KR20110099008A publication Critical patent/KR20110099008A/ko
Application granted granted Critical
Publication of KR101607725B1 publication Critical patent/KR101607725B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • H10P10/12Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
KR1020117012761A 2008-12-11 2009-12-10 와이드 밴드 갭 반도체를 적층한 복합 기판의 제조 방법 Expired - Fee Related KR101607725B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008315566 2008-12-11
JPJP-P-2008-315566 2008-12-11
JP2009278561A JP5389627B2 (ja) 2008-12-11 2009-12-08 ワイドバンドギャップ半導体を積層した複合基板の製造方法
JPJP-P-2009-278561 2009-12-08

Publications (2)

Publication Number Publication Date
KR20110099008A KR20110099008A (ko) 2011-09-05
KR101607725B1 true KR101607725B1 (ko) 2016-03-30

Family

ID=42242822

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020117012761A Expired - Fee Related KR101607725B1 (ko) 2008-12-11 2009-12-10 와이드 밴드 갭 반도체를 적층한 복합 기판의 제조 방법

Country Status (8)

Country Link
US (1) US8546245B2 (https=)
EP (1) EP2357660B1 (https=)
JP (1) JP5389627B2 (https=)
KR (1) KR101607725B1 (https=)
CN (1) CN102246267B (https=)
AU (1) AU2009325425B2 (https=)
TW (1) TWI482198B (https=)
WO (1) WO2010067835A1 (https=)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2961719B1 (fr) * 2010-06-24 2013-09-27 Soitec Silicon On Insulator Procede de traitement d'une piece en un materiau compose
RU2469433C1 (ru) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты)
JP5417399B2 (ja) 2011-09-15 2014-02-12 信越化学工業株式会社 複合ウェーハの製造方法
FR2984597B1 (fr) * 2011-12-20 2016-07-29 Commissariat Energie Atomique Fabrication d’une structure souple par transfert de couches
JP5884585B2 (ja) * 2012-03-21 2016-03-15 住友電気工業株式会社 炭化珪素半導体装置の製造方法
KR101436289B1 (ko) * 2012-07-18 2014-08-29 엔지케이 인슐레이터 엘티디 복합 웨이퍼 및 그 제조 방법
JP6160617B2 (ja) * 2012-07-25 2017-07-12 信越化学工業株式会社 ハイブリッド基板の製造方法及びハイブリッド基板
JP6265915B2 (ja) * 2012-12-26 2018-01-24 日本碍子株式会社 複合基板の製法
WO2014192597A1 (ja) * 2013-05-31 2014-12-04 日本碍子株式会社 複合基板用支持基板および複合基板
JP6165127B2 (ja) * 2014-12-22 2017-07-19 三菱重工工作機械株式会社 半導体装置及び半導体装置の製造方法
JP6396853B2 (ja) 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6396854B2 (ja) * 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6454606B2 (ja) * 2015-06-02 2019-01-16 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6396852B2 (ja) * 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6632462B2 (ja) * 2016-04-28 2020-01-22 信越化学工業株式会社 複合ウェーハの製造方法
JP6387375B2 (ja) 2016-07-19 2018-09-05 株式会社サイコックス 半導体基板
CN107785235A (zh) * 2016-08-31 2018-03-09 沈阳硅基科技有限公司 一种在基板上制造薄膜的方法
RU2699606C1 (ru) * 2016-11-28 2019-09-06 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Нижегородский государственный университет им. Н.И. Лобачевского" Способ ионно-лучевого синтеза нитрида галлия в кремнии
CN107326435A (zh) * 2017-07-28 2017-11-07 西安交通大学 一种生长GaN的SiC衬底的剥离方法
US10510532B1 (en) * 2018-05-29 2019-12-17 Industry-University Cooperation Foundation Hanyang University Method for manufacturing gallium nitride substrate using the multi ion implantation
KR101969679B1 (ko) * 2018-07-27 2019-04-16 한양대학교 산학협력단 Soi 웨이퍼와 열처리 공정을 이용한 박막 형성 및 전사 방법
JP7416935B2 (ja) * 2019-11-14 2024-01-17 ファーウェイ デジタル パワー テクノロジーズ カンパニー リミテッド 半導体基板、その製造方法、及び半導体装置
CN111883651A (zh) * 2020-07-23 2020-11-03 奥趋光电技术(杭州)有限公司 一种制备高质量氮化铝模板的方法
US20250059676A1 (en) 2021-12-21 2025-02-20 Shin-Etsu Handotai Co., Ltd. Nitride semiconductor substrate and method for producing nitride semiconductor substrate
KR20240169017A (ko) * 2022-03-23 2024-12-02 치글러, 졸탄 복합 기판 형성 방법
TWI912574B (zh) * 2023-01-10 2026-01-21 中國砂輪企業股份有限公司 複合式基板及複合式基板之製備方法
CN117476831B (zh) * 2023-12-20 2024-03-19 青禾晶元(晋城)半导体材料有限公司 Led外延片及其制备方法、led芯片及其制备方法
US20250254943A1 (en) * 2024-02-02 2025-08-07 Wolfspeed, Inc. Power Semiconductor Devices with Stacked Layers
US12610767B2 (en) 2024-03-07 2026-04-21 Wolfspeed, Inc. Additives for grinding semiconductor workpieces
DE102024203093A1 (de) * 2024-04-04 2025-10-09 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen einer Driftzone mit p-dotierten Bereichen eines Superjunction-Leistungshalbleiterbauelements und ein Superjunction-Leistungshalbleiterbauelement

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347176A (ja) * 2002-03-20 2003-12-05 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
JP2004140266A (ja) * 2002-10-18 2004-05-13 Ishikawajima Harima Heavy Ind Co Ltd 薄膜層ウェハ製造方法、及び薄膜層ウェハ

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6071795A (en) 1998-01-23 2000-06-06 The Regents Of The University Of California Separation of thin films from transparent substrates by selective optical processing
JP3655547B2 (ja) * 2000-05-10 2005-06-02 株式会社イオン工学研究所 半導体薄膜の形成方法
FR2817395B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
US6562127B1 (en) * 2002-01-16 2003-05-13 The United States Of America As Represented By The Secretary Of The Navy Method of making mosaic array of thin semiconductor material of large substrates
EP1482548B1 (en) * 2003-05-26 2016-04-13 Soitec A method of manufacturing a wafer
JP5110772B2 (ja) * 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
JP5358159B2 (ja) 2004-02-03 2013-12-04 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
WO2006082467A1 (en) * 2005-02-01 2006-08-10 S.O.I.Tec Silicon On Insulator Technologies Substrate for crystal growing a nitride semiconductor
JP2007019482A (ja) * 2005-06-07 2007-01-25 Fujifilm Holdings Corp 機能性膜含有構造体、及び、機能性膜の製造方法
WO2006132381A2 (en) 2005-06-07 2006-12-14 Fujifilm Corporation Functional film containing structure and method of manufacturing functional film
JP5042506B2 (ja) * 2006-02-16 2012-10-03 信越化学工業株式会社 半導体基板の製造方法
JP5064695B2 (ja) 2006-02-16 2012-10-31 信越化学工業株式会社 Soi基板の製造方法
JP4995626B2 (ja) * 2007-04-27 2012-08-08 信越化学工業株式会社 貼り合わせ基板の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347176A (ja) * 2002-03-20 2003-12-05 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
JP2004140266A (ja) * 2002-10-18 2004-05-13 Ishikawajima Harima Heavy Ind Co Ltd 薄膜層ウェハ製造方法、及び薄膜層ウェハ

Also Published As

Publication number Publication date
CN102246267B (zh) 2016-04-27
CN102246267A (zh) 2011-11-16
US8546245B2 (en) 2013-10-01
AU2009325425B2 (en) 2014-10-02
EP2357660A4 (en) 2012-06-20
TW201104726A (en) 2011-02-01
US20110227068A1 (en) 2011-09-22
EP2357660B1 (en) 2014-09-03
WO2010067835A1 (ja) 2010-06-17
KR20110099008A (ko) 2011-09-05
TWI482198B (zh) 2015-04-21
AU2009325425A1 (en) 2010-06-17
JP2010161355A (ja) 2010-07-22
EP2357660A1 (en) 2011-08-17
JP5389627B2 (ja) 2014-01-15

Similar Documents

Publication Publication Date Title
KR101607725B1 (ko) 와이드 밴드 갭 반도체를 적층한 복합 기판의 제조 방법
JP5455595B2 (ja) 貼り合わせウェーハの製造方法
JP5420968B2 (ja) 貼り合わせウェーハの製造方法
JP5496608B2 (ja) Soi基板の作製方法
KR102599962B1 (ko) 산화물 단결정 박막을 구비한 복합 웨이퍼의 제조 방법
KR101750580B1 (ko) 응력을 저감한 sos 기판
KR101685727B1 (ko) 표면 결함 밀도가 적은 sos기판
KR101652144B1 (ko) 계면 근방에 있어서의 결함 밀도가 낮은 sos 기판
JP4594121B2 (ja) Soiウエーハの製造方法及びsoiウエーハ

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20190305

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20250325

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

H13 Ip right lapsed

Free format text: ST27 STATUS EVENT CODE: N-4-6-H10-H13-OTH-PC1903 (AS PROVIDED BY THE NATIONAL OFFICE); TERMINATION CATEGORY : DEFAULT_OF_REGISTRATION_FEE

Effective date: 20250325

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20250325

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000