FR2961719B1 - Procede de traitement d'une piece en un materiau compose - Google Patents

Procede de traitement d'une piece en un materiau compose

Info

Publication number
FR2961719B1
FR2961719B1 FR1055058A FR1055058A FR2961719B1 FR 2961719 B1 FR2961719 B1 FR 2961719B1 FR 1055058 A FR1055058 A FR 1055058A FR 1055058 A FR1055058 A FR 1055058A FR 2961719 B1 FR2961719 B1 FR 2961719B1
Authority
FR
France
Prior art keywords
piece
processing
compound material
compound
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1055058A
Other languages
English (en)
Other versions
FR2961719A1 (fr
Inventor
Michel Bruel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR1055058A priority Critical patent/FR2961719B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to PCT/EP2011/059440 priority patent/WO2011160950A1/fr
Priority to JP2013515809A priority patent/JP5832531B2/ja
Priority to US13/700,435 priority patent/US8759196B2/en
Priority to CN201180030389.9A priority patent/CN102986019B/zh
Priority to KR1020137000353A priority patent/KR101770678B1/ko
Priority to EP11725696.6A priority patent/EP2586054A1/fr
Publication of FR2961719A1 publication Critical patent/FR2961719A1/fr
Application granted granted Critical
Publication of FR2961719B1 publication Critical patent/FR2961719B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
FR1055058A 2010-06-24 2010-06-24 Procede de traitement d'une piece en un materiau compose Active FR2961719B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR1055058A FR2961719B1 (fr) 2010-06-24 2010-06-24 Procede de traitement d'une piece en un materiau compose
JP2013515809A JP5832531B2 (ja) 2010-06-24 2011-06-08 注入および照射により基板を調製する方法
US13/700,435 US8759196B2 (en) 2010-06-24 2011-06-08 Method for preparing a substrate by implantation and irradiation
CN201180030389.9A CN102986019B (zh) 2010-06-24 2011-06-08 通过注入和照射制备衬底的方法
PCT/EP2011/059440 WO2011160950A1 (fr) 2010-06-24 2011-06-08 Procédé de préparation d'un substrat par implantation et irradiation
KR1020137000353A KR101770678B1 (ko) 2010-06-24 2011-06-08 주입 및 조사에 의해 기판을 제조하는 방법
EP11725696.6A EP2586054A1 (fr) 2010-06-24 2011-06-08 Procédé de préparation d'un substrat par implantation et irradiation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1055058A FR2961719B1 (fr) 2010-06-24 2010-06-24 Procede de traitement d'une piece en un materiau compose

Publications (2)

Publication Number Publication Date
FR2961719A1 FR2961719A1 (fr) 2011-12-30
FR2961719B1 true FR2961719B1 (fr) 2013-09-27

Family

ID=43038072

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1055058A Active FR2961719B1 (fr) 2010-06-24 2010-06-24 Procede de traitement d'une piece en un materiau compose

Country Status (7)

Country Link
US (1) US8759196B2 (fr)
EP (1) EP2586054A1 (fr)
JP (1) JP5832531B2 (fr)
KR (1) KR101770678B1 (fr)
CN (1) CN102986019B (fr)
FR (1) FR2961719B1 (fr)
WO (1) WO2011160950A1 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2961948B1 (fr) * 2010-06-23 2012-08-03 Soitec Silicon On Insulator Procede de traitement d'une piece en materiau compose
FR2978600B1 (fr) 2011-07-25 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de fabrication de couche de materiau semi-conducteur
CN103966551B (zh) * 2013-01-27 2016-11-23 常州国成新材料科技有限公司 一种解决高温下衬底原子蒸发影响平整度的方法及装置
FR3007892B1 (fr) * 2013-06-27 2015-07-31 Commissariat Energie Atomique Procede de transfert d'une couche mince avec apport d'energie thermique a une zone fragilisee via une couche inductive
JP6396854B2 (ja) * 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6396852B2 (ja) 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6396853B2 (ja) 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6454606B2 (ja) * 2015-06-02 2019-01-16 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
FR3079657B1 (fr) * 2018-03-29 2024-03-15 Soitec Silicon On Insulator Structure composite demontable par application d'un flux lumineux, et procede de separation d'une telle structure
KR102562239B1 (ko) * 2018-04-27 2023-07-31 글로벌웨이퍼스 씨오., 엘티디. 반도체 도너 기판으로부터의 층 전이를 용이하게 하는 광 지원형 소판 형성

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6958093B2 (en) * 1994-01-27 2005-10-25 Cree, Inc. Free-standing (Al, Ga, In)N and parting method for forming same
FR2748850B1 (fr) * 1996-05-15 1998-07-24 Commissariat Energie Atomique Procede de realisation d'un film mince de materiau solide et applications de ce procede
EP0858110B1 (fr) * 1996-08-27 2006-12-13 Seiko Epson Corporation Methode de separation, procede de transfert d'un dispositif a film mince, et dispositif d'affichage a cristaux liquides obtenu par application du procede de transfert
JP4192430B2 (ja) 2001-02-28 2008-12-10 日立電線株式会社 窒化物半導体エピタキシャルウェハの製造方法
JP3962282B2 (ja) * 2002-05-23 2007-08-22 松下電器産業株式会社 半導体装置の製造方法
JP5110772B2 (ja) * 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
FR2870988B1 (fr) 2004-06-01 2006-08-11 Michel Bruel Procede de realisation d'une structure multi-couches comportant, en profondeur, une couche de separation
KR101319468B1 (ko) * 2005-12-02 2013-10-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치의 제조방법
JP5064695B2 (ja) * 2006-02-16 2012-10-31 信越化学工業株式会社 Ｓｏｉ基板の製造方法
WO2008098404A2 (fr) * 2007-02-16 2008-08-21 ETH Zürich Procédé de fabrication d'un film monocristallin, et dispositif optique intégré incorporant un tel film monocristallin
FR2920589B1 (fr) * 2007-09-04 2010-12-03 Soitec Silicon On Insulator "procede d'obtention d'un substrat hybride comprenant au moins une couche d'un materiau nitrure"
JP5336101B2 (ja) * 2008-04-01 2013-11-06 信越化学工業株式会社 Ｓｏｉ基板の製造方法
JP5389627B2 (ja) * 2008-12-11 2014-01-15 信越化学工業株式会社 ワイドバンドギャップ半導体を積層した複合基板の製造方法

Also Published As

Publication number Publication date
KR20130083429A (ko) 2013-07-22
CN102986019B (zh) 2016-05-25
WO2011160950A1 (fr) 2011-12-29
JP2013533621A (ja) 2013-08-22
US8759196B2 (en) 2014-06-24
US20130072009A1 (en) 2013-03-21
KR101770678B1 (ko) 2017-08-23
JP5832531B2 (ja) 2015-12-16
EP2586054A1 (fr) 2013-05-01
CN102986019A (zh) 2013-03-20
FR2961719A1 (fr) 2011-12-30

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