KR100933897B1 - 분리가능 기판 또는 분리가능 구조체 및 그 생산방법 - Google Patents
분리가능 기판 또는 분리가능 구조체 및 그 생산방법 Download PDFInfo
- Publication number
- KR100933897B1 KR100933897B1 KR1020037013311A KR20037013311A KR100933897B1 KR 100933897 B1 KR100933897 B1 KR 100933897B1 KR 1020037013311 A KR1020037013311 A KR 1020037013311A KR 20037013311 A KR20037013311 A KR 20037013311A KR 100933897 B1 KR100933897 B1 KR 100933897B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- substrate
- region
- interface
- creating
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 240
- 238000004519 manufacturing process Methods 0.000 title description 23
- 238000002360 preparation method Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 102
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 57
- 238000000926 separation method Methods 0.000 claims description 44
- 229910052710 silicon Inorganic materials 0.000 claims description 36
- 239000010703 silicon Substances 0.000 claims description 34
- 238000005530 etching Methods 0.000 claims description 33
- 239000000126 substance Substances 0.000 claims description 31
- 238000005498 polishing Methods 0.000 claims description 22
- 238000005520 cutting process Methods 0.000 claims description 21
- 238000011282 treatment Methods 0.000 claims description 20
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 239000002253 acid Substances 0.000 claims description 8
- 230000000694 effects Effects 0.000 claims description 8
- 238000004377 microelectronic Methods 0.000 claims description 8
- 230000002829 reductive effect Effects 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 6
- 238000007788 roughening Methods 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 5
- 230000005855 radiation Effects 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000012634 fragment Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 219
- 239000000463 material Substances 0.000 description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 35
- 235000012431 wafers Nutrition 0.000 description 27
- 229910004298 SiO 2 Inorganic materials 0.000 description 26
- 238000012546 transfer Methods 0.000 description 23
- 238000010438 heat treatment Methods 0.000 description 17
- 238000000151 deposition Methods 0.000 description 15
- 238000000137 annealing Methods 0.000 description 14
- 230000027455 binding Effects 0.000 description 14
- 238000003486 chemical etching Methods 0.000 description 14
- 150000004767 nitrides Chemical class 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 13
- 230000008901 benefit Effects 0.000 description 12
- 230000008569 process Effects 0.000 description 11
- 239000007789 gas Substances 0.000 description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 10
- 229910010271 silicon carbide Inorganic materials 0.000 description 10
- 230000008021 deposition Effects 0.000 description 9
- 239000010408 film Substances 0.000 description 9
- 238000002513 implantation Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 8
- 230000010070 molecular adhesion Effects 0.000 description 8
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 7
- 239000002344 surface layer Substances 0.000 description 7
- 239000011241 protective layer Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 238000005304 joining Methods 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 230000036961 partial effect Effects 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 4
- 230000000712 assembly Effects 0.000 description 4
- 238000000429 assembly Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 229910003465 moissanite Inorganic materials 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 229910017214 AsGa Inorganic materials 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- 238000005452 bending Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 230000001934 delay Effects 0.000 description 3
- 238000005868 electrolysis reaction Methods 0.000 description 3
- 239000012530 fluid Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000000696 magnetic material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910013641 LiNbO 3 Inorganic materials 0.000 description 2
- 229910003327 LiNbO3 Inorganic materials 0.000 description 2
- 229910012463 LiTaO3 Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- -1 buried defects Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021426 porous silicon Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 230000003313 weakening effect Effects 0.000 description 2
- 229910004613 CdTe Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000009172 bursting Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 238000012993 chemical processing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 238000005108 dry cleaning Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 238000007521 mechanical polishing technique Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000009149 molecular binding Effects 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 235000011007 phosphoric acid Nutrition 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229910052950 sphalerite Inorganic materials 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000002470 thermal conductor Substances 0.000 description 1
- 238000002054 transplantation Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052984 zinc sulfide Inorganic materials 0.000 description 1
- 238000013316 zoning Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/84—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
- H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/11—Methods of delaminating, per se; i.e., separating at bonding face
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Weting (AREA)
- Laminated Bodies (AREA)
- Materials For Medical Uses (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
Claims (42)
- 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법에 있어서, 상기 인터페이스는 적어도, 0이 아닌 제 1 레벨의 기계 강도를 가지는 제 1 영역(Z1, Z1') 및 상기 제 1 레벨의 기계 강도보다 큰 제 2 레벨의 기계 강도를 가지는 제 2 영역(Z2, Z2')을 포함하도록 결합에 의해 생성되고, 상기 제 1 영역은 상기 제 2 영역에 의해 둘러싸이고, 상기 제 1 영역(Z1, Z1') 및 제 2 영역(Z2, Z2') 모두 상기 기판과 접촉하고 있는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 1 항에 있어서, 상기 분리가능 인터페이스의 적어도 일 부분이 제 1 영역 및 제 2 영역의 적어도 일부에 대해 분리되어 있고, 상기 일 부분이 상기 인터페이스의 전부나 일부를 나타내고, 상기 일 부분의 외면이 제 2 영역을 따라 뻗어있는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 1 항에 있어서, 상기 제 2 영역은 상기 제 1 영역이 코어를 구성하는 웨이퍼의 외면을 구성하는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 1 항 내지 제 3 항 중 어느 한 항에 있어서, 상기 제 1 영역은 그 각각의 조각이 상기 제 2 영역에 의하여 둘러싸여있는 상기 조각들로 나누어진 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 1 항 내지 제 3 항 중 어느 한 항에 있어서, 상기 인터페이스는 상기 기판의 표면 및 상기 층의 표면사이에 생성되고 상기 인터페이스를 생성하는 상기 단계는 상기 표면중 적어도 하나를 준비하는 단계 및 상기 준비된 표면이 분자 부착 결합에 의하여 다른 표면에 결합되는 결합 단계를 포함하는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 5 항에 있어서, 상기 인터페이스를 생성하는 단계는 상기 기판의 표면 및 상기 층의 표면의 각각을 준비하는 단계를 포함하는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 5 항에 있어서, 상기 표면 준비 단계는 상기 제 1 영역에서 상기 표면의 거칠기를 국소적으로 증가시키기위한 처리 단계를 포함하는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 7 항에 있어서, 상기 처리 단계는 상기 제 1 영역에 상기 표면의 국소적 산 에칭을 포함하는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 8 항에 있어서, 산 에칭은 플루오르화수소산으로 효과를 나타내고, 상기 제 2 영역에서의 표면은 에칭후에 제거되는 층에 의하여 상기 에칭으로 부터 보호되고 있는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 5 항에 있어서, 상기 표면 준비 단계는 상기 표면이 전체적으로 거칠기되는 단계 및, 상기 전체 표면의 일부가 상기 전체 표면의 나머지에서 보다 큰 결합력을 얻기 위하여 상기 일부의 거칠기가 증대되는 단계를 포함하는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 10 항에 있어서, 상기의 일부의 거칠기는 화학적 연마, 기계적 처리 또는 화학기계적 처리, 또는 드라이 에칭에 의하여 감소되는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 삭제
- 삭제
- 삭제
- 삭제
- 제 1 항 내지 제 3 항 중 어느 한 항에 있어서, 상기 인터페이스를 생성하는 상기 단계는 상기 기판으로 부터 상기 층을 분리하는 단계가 뒤따라 수행되는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 16 항에 있어서, 상기 인터페이스를 생성하는 상기 단계 이후에, 상기 제 2 영역(Z2')의 부분이 1 조각의 외면에서 상기 제1 영역의 부분을 따라 뻗도록 적어도 상기 제 1 영역(Z1')의 부분 및 상기 제 2 영역(Z2')의 부분을 포함하는 상기 층의 1 조각을 커팅하는 단계와 이어서 상기 기판 및 상기 박층이 리프트오프되는 분리 단계가 수행되는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 16 항에 있어서, 상기 인터페이스를 생성하는 상기 단계 및 상기 분리 단계사이에, 상기 제 1 영역에 대하여 상기 제 2 영역을 커팅하는 단계가 있는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 16 항에 있어서, 상기 인터페이스를 생성하는 단계 및 상기 분리 단계사이에서, 상기 층 내에 마이크로전자적, 광학적 또는 기계적 구성요소의 전부 또는 일부를 생성하는 단계를 포함하는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 19 항에 있어서, 각각의 구성요소는 상기 제 2 영역에 의하여 둘러싸이고 상기 제2 영역의 기계 강도 보다 낮은 기계 강도를 갖는 상기 제 1 영역과 마주하여 생성되는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 16 항에 있어서, 상기 인터페이스를 생성하는 상기 단계 및 상기 분리 단계사이에, 상기 층이 제 2 기판(16, 16')에 결합되는 결합 단계가 있는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 21 항에 있어서, 상기 결합 단계는 분자 부착 결합을 포함하는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 21 항에 있어서, 상기 결합 단계는 부착 결합을 포함하는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 23 항에 있어서, 상기 부착 결합은 UV방사에 의하여 경화되는 접착제를 사용하는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 16 항에 있어서, 상기 분리 단계는 산 에칭 및 기계압력의 인가에 의하여 수행되는 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 제 1 항 내지 제 3 항 중 어느 한 항에 있어서, 상기 층은 실리콘인 것을 특징으로 하는 박층의 일부를 형성하기 위한 층 및 기판간의 분리가능 인터페이스를 생성하는 단계를 포함하는 상기 박층을 준비하는 방법.
- 기판상에 층을 포함하는 어셈블리에 있어서, 상기 층(13+14, 13'+14', 23)은 적어도 선택된 제 1 영역(Z1, Z1')이 0이 아닌 제 1 레벨의 기계 강도를 가지고 있고 그리고 선택된 제 2 영역(Z2, Z2')이 상기 제 1 레벨보다 큰 제 2 레벨의 기계 강도를 가지는 분리가능 결합된 인터페이스에서 상기 기판(11+12, 11'+12', 21)에 연결되어 있고, 상기 제 1 영역(Z1, Z1')은 상기 제 2 영역(Z2, Z2')에 포함되고, 상기 제 1 영역(Z1, Z1') 및 제 2 영역(Z2, Z2') 모두 상기 기판과 접촉하고 있는 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 제 27 항에 있어서, 상기 제 2 영역은 상기 어셈블리의 외면을 따라 뻗은 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 제 27 항에 있어서, 상기 제 2 영역은 상기 제 1 영역이 코어를 구성하는 웨이퍼의 외면을 구성하는 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 제 27 항 또는 제 28 항에 있어서, 상기 제 1 영역은 그 각각의 조각이 상기 제 2 영역에 의하여 둘러싸인 상기 조각으로 나누어지는 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 제 27 항 또는 제 28 항에 있어서, 상기 층에서 커팅된 조각은 상기 제 2 영역이 상기 조각의 외면을 따라 뻗도록 상기 제 1 영역 및 상기 제 2 영역을 포함하는 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 제 27 항 내지 제 29 항 중 어느 한 항에 있어서, 상기 층은 마이크로전자, 광학 또는 기계 구성요소의 전부 또는 일부를 포함하는 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 제 32 항에 있어서, 상기 구성요소는 상기 제 2 영역에 의하여 둘러싸이고 상기 제2 영역의 기계 강도 보다 낮은 기계 강도를 갖는 상기 제 1 영역과 마주하는 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 제 27 항 내지 제 29 항 중 어느 한 항에 있어서, 상기 인터페이스는 상기 기판의 표면 및 분자 부착 결합된 상기 층의 표면사이에 생성되는 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 제 27 항 내지 제 29 항 중 어느 한 항에 있어서, 상기 인터페이스의 적어도 1 표면은 상기 제 2 영역에서 보다 상기 제 1 영역에서 보다 큰 거칠기를 가지는 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 삭제
- 삭제
- 제 27 항 내지 제 29 항 중 어느 한 항에 있어서, 상기층은 제 2 기판(16, 16')에 부가적으로 결합되는 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 제 38 항에 있어서, 상기 제 2 기판은 분자 부착 결합되는 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 제 38 항에 있어서, 상기 제 2 기판은 부착 결합되는 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 제 40 항에 있어서, 상기 부착 결합은 UV방사에 의하여 경화되는 접착제를 사용하는 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
- 제 27 항 내지 제 29 항 중 어느 한 항에 있어서, 상기 층은 실리콘인 것을 특징으로 하는 기판상에 층을 포함하는 어셈블리.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0105129A FR2823596B1 (fr) | 2001-04-13 | 2001-04-13 | Substrat ou structure demontable et procede de realisation |
FR01/05129 | 2001-04-13 | ||
PCT/FR2002/001266 WO2002084721A2 (fr) | 2001-04-13 | 2002-04-11 | Substrat ou structure demontable et procede de realisation |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040000425A KR20040000425A (ko) | 2004-01-03 |
KR100933897B1 true KR100933897B1 (ko) | 2009-12-28 |
Family
ID=8862351
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020037013311A KR100933897B1 (ko) | 2001-04-13 | 2002-04-11 | 분리가능 기판 또는 분리가능 구조체 및 그 생산방법 |
Country Status (9)
Country | Link |
---|---|
US (1) | US7713369B2 (ko) |
EP (1) | EP1378003B1 (ko) |
JP (2) | JP4540933B2 (ko) |
KR (1) | KR100933897B1 (ko) |
CN (1) | CN100355025C (ko) |
AU (1) | AU2002304525A1 (ko) |
FR (1) | FR2823596B1 (ko) |
TW (1) | TW577102B (ko) |
WO (1) | WO2002084721A2 (ko) |
Families Citing this family (114)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2748851B1 (fr) | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
FR2773261B1 (fr) * | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2823599B1 (fr) * | 2001-04-13 | 2004-12-17 | Commissariat Energie Atomique | Substrat demomtable a tenue mecanique controlee et procede de realisation |
FR2823596B1 (fr) | 2001-04-13 | 2004-08-20 | Commissariat Energie Atomique | Substrat ou structure demontable et procede de realisation |
FR2846788B1 (fr) * | 2002-10-30 | 2005-06-17 | Procede de fabrication de substrats demontables | |
FR2847077B1 (fr) | 2002-11-12 | 2006-02-17 | Soitec Silicon On Insulator | Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation |
FR2848336B1 (fr) * | 2002-12-09 | 2005-10-28 | Commissariat Energie Atomique | Procede de realisation d'une structure contrainte destinee a etre dissociee |
FR2892228B1 (fr) * | 2005-10-18 | 2008-01-25 | Soitec Silicon On Insulator | Procede de recyclage d'une plaquette donneuse epitaxiee |
US20090325362A1 (en) * | 2003-01-07 | 2009-12-31 | Nabil Chhaimi | Method of recycling an epitaxied donor wafer |
EP1437426A1 (de) * | 2003-01-10 | 2004-07-14 | Siemens Aktiengesellschaft | Verfahren zum Herstellen von einkristallinen Strukturen |
US6759277B1 (en) * | 2003-02-27 | 2004-07-06 | Sharp Laboratories Of America, Inc. | Crystalline silicon die array and method for assembling crystalline silicon sheets onto substrates |
US7122095B2 (en) | 2003-03-14 | 2006-10-17 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Methods for forming an assembly for transfer of a useful layer |
FR2852445B1 (fr) * | 2003-03-14 | 2005-05-20 | Soitec Silicon On Insulator | Procede de realisation de substrats ou composants sur substrats avec transfert de couche utile, pour la microelectronique, l'optoelectronique ou l'optique |
JP4794810B2 (ja) | 2003-03-20 | 2011-10-19 | シャープ株式会社 | 半導体装置の製造方法 |
FR2856844B1 (fr) * | 2003-06-24 | 2006-02-17 | Commissariat Energie Atomique | Circuit integre sur puce de hautes performances |
JP4581349B2 (ja) * | 2003-08-29 | 2010-11-17 | 株式会社Sumco | 貼合せsoiウェーハの製造方法 |
US8475693B2 (en) | 2003-09-30 | 2013-07-02 | Soitec | Methods of making substrate structures having a weakened intermediate layer |
FR2860249B1 (fr) | 2003-09-30 | 2005-12-09 | Michel Bruel | Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium |
JP4809600B2 (ja) * | 2003-10-28 | 2011-11-09 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
FR2861497B1 (fr) * | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
FR2871291B1 (fr) * | 2004-06-02 | 2006-12-08 | Tracit Technologies | Procede de transfert de plaques |
JP4838504B2 (ja) * | 2004-09-08 | 2011-12-14 | キヤノン株式会社 | 半導体装置の製造方法 |
FR2876220B1 (fr) * | 2004-10-06 | 2007-09-28 | Commissariat Energie Atomique | Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees. |
US7405108B2 (en) * | 2004-11-20 | 2008-07-29 | International Business Machines Corporation | Methods for forming co-planar wafer-scale chip packages |
FR2878648B1 (fr) * | 2004-11-30 | 2007-02-02 | Commissariat Energie Atomique | Support semi-conducteur rectangulaire pour la microelectronique et procede de realisation d'un tel support |
FR2880189B1 (fr) | 2004-12-24 | 2007-03-30 | Tracit Technologies Sa | Procede de report d'un circuit sur un plan de masse |
JP2006216891A (ja) * | 2005-02-07 | 2006-08-17 | Tokyo Univ Of Agriculture & Technology | 薄膜素子構造の作製方法、及び薄膜素子構造作製用の機能性基体 |
JPWO2006118033A1 (ja) * | 2005-04-27 | 2008-12-18 | リンテック株式会社 | シート状アンダーフィル材および半導体装置の製造方法 |
FR2888400B1 (fr) * | 2005-07-08 | 2007-10-19 | Soitec Silicon On Insulator | Procede de prelevement de couche |
FR2889887B1 (fr) * | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | Procede de report d'une couche mince sur un support |
FR2891281B1 (fr) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
EP1777735A3 (fr) * | 2005-10-18 | 2009-08-19 | S.O.I.Tec Silicon on Insulator Technologies | Procédé de recyclage d'une plaquette donneuse épitaxiée |
FR2893750B1 (fr) * | 2005-11-22 | 2008-03-14 | Commissariat Energie Atomique | Procede de fabrication d'un dispositif electronique flexible du type ecran comportant une pluralite de composants en couches minces. |
EP1801870A1 (en) * | 2005-12-22 | 2007-06-27 | Princo Corp. | Partial adherent temporary substrate and method of using the same |
US7829436B2 (en) | 2005-12-22 | 2010-11-09 | Sumco Corporation | Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer |
US7781309B2 (en) * | 2005-12-22 | 2010-08-24 | Sumco Corporation | Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method |
TWI285424B (en) * | 2005-12-22 | 2007-08-11 | Princo Corp | Substrate including a multi-layer interconnection structure, methods of manufacturing and recycling the same, method of packaging electronic devices by using the same, and method of manufacturing an interconnection device |
CN1996582B (zh) * | 2006-01-06 | 2012-02-15 | 巨擘科技股份有限公司 | 包含多层内连线结构的载板及其制造、回收以及应用方法 |
EP2002475B1 (de) * | 2006-03-14 | 2016-05-04 | Institut Für Mikroelektronik Stuttgart | Verfahren zum herstellen einer integrierten schaltung |
DE102006059394B4 (de) * | 2006-12-08 | 2019-11-21 | Institut Für Mikroelektronik Stuttgart | Integrierte Schaltung und Verfahren zu deren Herstellung |
DE102006013419B4 (de) * | 2006-03-14 | 2008-05-29 | Institut Für Mikroelektronik Stuttgart | Verfahren zum Herstellen einer integrierten Schaltung |
US8051557B2 (en) | 2006-03-31 | 2011-11-08 | Princo Corp. | Substrate with multi-layer interconnection structure and method of manufacturing the same |
US20080057678A1 (en) * | 2006-08-31 | 2008-03-06 | Kishor Purushottam Gadkaree | Semiconductor on glass insulator made using improved hydrogen reduction process |
FR2910179B1 (fr) | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
FR2912839B1 (fr) * | 2007-02-16 | 2009-05-15 | Soitec Silicon On Insulator | Amelioration de la qualite de l'interface de collage par nettoyage froid et collage a chaud |
FR2913968B1 (fr) * | 2007-03-23 | 2009-06-12 | Soitec Silicon On Insulator | Procede de realisation de membranes autoportees. |
WO2008123117A1 (en) * | 2007-03-26 | 2008-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Soi substrate and method for manufacturing soi substrate |
FR2914493B1 (fr) | 2007-03-28 | 2009-08-07 | Soitec Silicon On Insulator | Substrat demontable. |
US7605054B2 (en) | 2007-04-18 | 2009-10-20 | S.O.I.Tec Silicon On Insulator Technologies | Method of forming a device wafer with recyclable support |
FR2922359B1 (fr) * | 2007-10-12 | 2009-12-18 | Commissariat Energie Atomique | Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire |
FR2925221B1 (fr) * | 2007-12-17 | 2010-02-19 | Commissariat Energie Atomique | Procede de transfert d'une couche mince |
FR2926671B1 (fr) * | 2008-01-17 | 2010-04-02 | Soitec Silicon On Insulator | Procede de traitement de defauts lors de collage de plaques |
FR2926672B1 (fr) * | 2008-01-21 | 2010-03-26 | Soitec Silicon On Insulator | Procede de fabrication de couches de materiau epitaxie |
KR101096142B1 (ko) * | 2008-01-24 | 2011-12-19 | 브레우어 사이언스 인코포레이션 | 캐리어 기판에 디바이스 웨이퍼를 가역적으로 장착하는 방법 |
FR2929758B1 (fr) * | 2008-04-07 | 2011-02-11 | Commissariat Energie Atomique | Procede de transfert a l'aide d'un substrat ferroelectrique |
TWI424587B (zh) * | 2008-06-30 | 2014-01-21 | Luxtaltek Corp | Light emitting diodes with nanoscale surface structure and embossing molds forming nanometer scale surface structures |
JP5478199B2 (ja) * | 2008-11-13 | 2014-04-23 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
FR2947098A1 (fr) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
US9847243B2 (en) | 2009-08-27 | 2017-12-19 | Corning Incorporated | Debonding a glass substrate from carrier using ultrasonic wave |
US8187901B2 (en) | 2009-12-07 | 2012-05-29 | Micron Technology, Inc. | Epitaxial formation support structures and associated methods |
EP2529394A4 (en) | 2010-01-27 | 2017-11-15 | Yale University | Conductivity based selective etch for gan devices and applications thereof |
CN102812546B (zh) * | 2010-03-31 | 2015-08-26 | Ev集团E·索尔纳有限责任公司 | 制造双面装备有芯片的晶片的方法 |
US8852391B2 (en) * | 2010-06-21 | 2014-10-07 | Brewer Science Inc. | Method and apparatus for removing a reversibly mounted device wafer from a carrier substrate |
US20130119519A1 (en) * | 2010-07-30 | 2013-05-16 | Kyocera Corporation | Composite substrate, electronic component, and method for manufacturing composite substrate, and method for manufacturing electronic component |
US9263314B2 (en) | 2010-08-06 | 2016-02-16 | Brewer Science Inc. | Multiple bonding layers for thin-wafer handling |
JP5902917B2 (ja) * | 2010-11-12 | 2016-04-13 | 株式会社半導体エネルギー研究所 | 半導体基板の作製方法 |
JP5926527B2 (ja) * | 2011-10-17 | 2016-05-25 | 信越化学工業株式会社 | 透明soiウェーハの製造方法 |
US10543662B2 (en) | 2012-02-08 | 2020-01-28 | Corning Incorporated | Device modified substrate article and methods for making |
US8975157B2 (en) | 2012-02-08 | 2015-03-10 | Advanced Semiconductor Engineering, Inc. | Carrier bonding and detaching processes for a semiconductor wafer |
CN104471360B (zh) * | 2012-06-18 | 2016-04-20 | 松下知识产权经营株式会社 | 红外线检测装置 |
WO2014004261A1 (en) | 2012-06-28 | 2014-01-03 | Yale University | Lateral electrochemical etching of iii-nitride materials for microfabrication |
WO2014020387A1 (en) | 2012-07-31 | 2014-02-06 | Soitec | Methods of forming semiconductor structures including mems devices and integrated circuits on opposing sides of substrates, and related structures and devices |
WO2014026292A1 (en) * | 2012-08-15 | 2014-02-20 | Mcmaster University | Arbitrarily thin ultra smooth film with built-in separation ability and method of forming the same |
KR101392133B1 (ko) * | 2012-08-20 | 2014-05-07 | 세종대학교산학협력단 | 서로 다른 젖음성을 갖는 영역들을 구비하는 캐리어 기판, 이를 사용한 소자 기판 처리 방법 |
FR2995445B1 (fr) * | 2012-09-07 | 2016-01-08 | Soitec Silicon On Insulator | Procede de fabrication d'une structure en vue d'une separation ulterieure |
FR2995447B1 (fr) | 2012-09-07 | 2014-09-05 | Soitec Silicon On Insulator | Procede de separation d'au moins deux substrats selon une interface choisie |
US10086584B2 (en) | 2012-12-13 | 2018-10-02 | Corning Incorporated | Glass articles and methods for controlled bonding of glass sheets with carriers |
US10014177B2 (en) | 2012-12-13 | 2018-07-03 | Corning Incorporated | Methods for processing electronic devices |
TWI617437B (zh) | 2012-12-13 | 2018-03-11 | 康寧公司 | 促進控制薄片與載體間接合之處理 |
US9340443B2 (en) | 2012-12-13 | 2016-05-17 | Corning Incorporated | Bulk annealing of glass sheets |
DE102012112989A1 (de) * | 2012-12-21 | 2014-06-26 | Ev Group E. Thallner Gmbh | Verfahren zum Aufbringen einer Temporärbondschicht |
US9028628B2 (en) | 2013-03-14 | 2015-05-12 | International Business Machines Corporation | Wafer-to-wafer oxide fusion bonding |
US9058974B2 (en) | 2013-06-03 | 2015-06-16 | International Business Machines Corporation | Distorting donor wafer to corresponding distortion of host wafer |
JP2015035453A (ja) * | 2013-08-07 | 2015-02-19 | アズビル株式会社 | ウエハ |
US10510576B2 (en) | 2013-10-14 | 2019-12-17 | Corning Incorporated | Carrier-bonding methods and articles for semiconductor and interposer processing |
WO2017034645A2 (en) * | 2015-06-09 | 2017-03-02 | ARIZONA BOARD OF REGENTS, a body corporate for THE STATE OF ARIZONA for and on behalf of ARIZONA STATE UNIVERSITY | Method of providing an electronic device and electronic device thereof |
US10381224B2 (en) * | 2014-01-23 | 2019-08-13 | Arizona Board Of Regents On Behalf Of Arizona State University | Method of providing an electronic device and electronic device thereof |
JP6770432B2 (ja) | 2014-01-27 | 2020-10-14 | コーニング インコーポレイテッド | 薄いシートの担体との制御された結合のための物品および方法 |
FR3019374A1 (fr) * | 2014-03-28 | 2015-10-02 | Soitec Silicon On Insulator | Procede de separation et de transfert de couches |
SG11201608442TA (en) | 2014-04-09 | 2016-11-29 | Corning Inc | Device modified substrate article and methods for making |
US11095096B2 (en) | 2014-04-16 | 2021-08-17 | Yale University | Method for a GaN vertical microcavity surface emitting laser (VCSEL) |
US11043792B2 (en) | 2014-09-30 | 2021-06-22 | Yale University | Method for GaN vertical microcavity surface emitting laser (VCSEL) |
US11018231B2 (en) | 2014-12-01 | 2021-05-25 | Yale University | Method to make buried, highly conductive p-type III-nitride layers |
US10554017B2 (en) | 2015-05-19 | 2020-02-04 | Yale University | Method and device concerning III-nitride edge emitting laser diode of high confinement factor with lattice matched cladding layer |
WO2016187186A1 (en) | 2015-05-19 | 2016-11-24 | Corning Incorporated | Articles and methods for bonding sheets with carriers |
CN117534339A (zh) | 2015-06-26 | 2024-02-09 | 康宁股份有限公司 | 包含板材和载体的方法和制品 |
KR20170033163A (ko) | 2015-09-16 | 2017-03-24 | 임종순 | 수로관 및 이의 시공방법 |
DE102016106351A1 (de) * | 2016-04-07 | 2017-10-12 | Ev Group E. Thallner Gmbh | Verfahren und Vorrichtung zum Bonden zweier Substrate |
US20180019169A1 (en) * | 2016-07-12 | 2018-01-18 | QMAT, Inc. | Backing substrate stabilizing donor substrate for implant or reclamation |
TW202216444A (zh) | 2016-08-30 | 2022-05-01 | 美商康寧公司 | 用於片材接合的矽氧烷電漿聚合物 |
TWI810161B (zh) | 2016-08-31 | 2023-08-01 | 美商康寧公司 | 具以可控制式黏結的薄片之製品及製作其之方法 |
FR3063176A1 (fr) * | 2017-02-17 | 2018-08-24 | Soitec | Masquage d'une zone au bord d'un substrat donneur lors d'une etape d'implantation ionique |
TWI756384B (zh) * | 2017-03-16 | 2022-03-01 | 美商康寧公司 | 用於大量轉移微型led的方法及製程 |
KR102179165B1 (ko) | 2017-11-28 | 2020-11-16 | 삼성전자주식회사 | 캐리어 기판 및 상기 캐리어 기판을 이용한 반도체 패키지의 제조방법 |
FR3074960B1 (fr) | 2017-12-07 | 2019-12-06 | Soitec | Procede de transfert d'une couche utilisant une structure demontable |
JP7431160B2 (ja) | 2017-12-15 | 2024-02-14 | コーニング インコーポレイテッド | 基板を処理するための方法および結合されたシートを含む物品を製造するための方法 |
CN111819662B (zh) * | 2018-03-14 | 2024-03-26 | 东京毅力科创株式会社 | 基板处理系统、基板处理方法以及计算机存储介质 |
TWI791099B (zh) * | 2018-03-29 | 2023-02-01 | 日商日本碍子股份有限公司 | 接合體及彈性波元件 |
US10964664B2 (en) | 2018-04-20 | 2021-03-30 | Invensas Bonding Technologies, Inc. | DBI to Si bonding for simplified handle wafer |
US11101158B1 (en) * | 2018-08-08 | 2021-08-24 | United States Of America As Represented By The Administrator Of Nasa | Wafer-scale membrane release laminates, devices and processes |
US11081392B2 (en) * | 2018-09-28 | 2021-08-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dicing method for stacked semiconductor devices |
FR3108439B1 (fr) | 2020-03-23 | 2022-02-11 | Soitec Silicon On Insulator | Procede de fabrication d’une structure empilee |
FR3109016B1 (fr) | 2020-04-01 | 2023-12-01 | Soitec Silicon On Insulator | Structure demontable et procede de transfert d’une couche mettant en œuvre ladite structure demontable |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10163166A (ja) * | 1996-11-28 | 1998-06-19 | Mitsubishi Electric Corp | 半導体装置の製造方法及び製造装置 |
JPH11317577A (ja) * | 1997-12-02 | 1999-11-16 | Commiss Energ Atom | 第一基板上に形成された微細構造部の最終基板への選択的なトランスファープロセス |
KR20000070432A (ko) * | 1997-01-27 | 2000-11-25 | 쉔느 필립 | 이온주입을 수반하여, 이온으로부터 보호된 영역을 구비하는 박막, 특히 반도체막을 얻는 방법 |
Family Cites Families (95)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4121334A (en) | 1974-12-17 | 1978-10-24 | P. R. Mallory & Co. Inc. | Application of field-assisted bonding to the mass production of silicon type pressure transducers |
JPS53104156A (en) | 1977-02-23 | 1978-09-11 | Hitachi Ltd | Manufacture for semiconductor device |
US4179324A (en) | 1977-11-28 | 1979-12-18 | Spire Corporation | Process for fabricating thin film and glass sheet laminate |
JPS5831519A (ja) | 1981-08-18 | 1983-02-24 | Toshiba Corp | 半導体装置の製造方法 |
SU1282757A1 (ru) | 1983-12-30 | 2000-06-27 | Институт Ядерной Физики Ан Казсср | Способ изготовления тонких пластин кремния |
JPS62265717A (ja) | 1986-05-13 | 1987-11-18 | Nippon Telegr & Teleph Corp <Ntt> | ガリウムひ素集積回路用基板の熱処理方法 |
GB8725497D0 (en) | 1987-10-30 | 1987-12-02 | Atomic Energy Authority Uk | Isolation of silicon |
JP2927277B2 (ja) | 1988-12-05 | 1999-07-28 | 住友電気工業株式会社 | 車載ナビゲータ |
JPH0355822A (ja) | 1989-07-25 | 1991-03-11 | Shin Etsu Handotai Co Ltd | 半導体素子形成用基板の製造方法 |
US5013681A (en) | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
US5310446A (en) | 1990-01-10 | 1994-05-10 | Ricoh Company, Ltd. | Method for producing semiconductor film |
US5034343A (en) | 1990-03-08 | 1991-07-23 | Harris Corporation | Manufacturing ultra-thin wafer using a handle wafer |
JPH0719739B2 (ja) | 1990-09-10 | 1995-03-06 | 信越半導体株式会社 | 接合ウェーハの製造方法 |
US5618739A (en) | 1990-11-15 | 1997-04-08 | Seiko Instruments Inc. | Method of making light valve device using semiconductive composite substrate |
JPH04199504A (ja) | 1990-11-28 | 1992-07-20 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2812405B2 (ja) | 1991-03-15 | 1998-10-22 | 信越半導体株式会社 | 半導体基板の製造方法 |
US5256581A (en) | 1991-08-28 | 1993-10-26 | Motorola, Inc. | Silicon film with improved thickness control |
JP3416163B2 (ja) | 1992-01-31 | 2003-06-16 | キヤノン株式会社 | 半導体基板及びその作製方法 |
JPH05235312A (ja) | 1992-02-19 | 1993-09-10 | Fujitsu Ltd | 半導体基板及びその製造方法 |
JP3352118B2 (ja) * | 1992-08-25 | 2002-12-03 | キヤノン株式会社 | 半導体装置及びその製造方法 |
US5234535A (en) | 1992-12-10 | 1993-08-10 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
JPH07211876A (ja) * | 1994-01-21 | 1995-08-11 | Canon Inc | 半導体基体の作成方法 |
FR2715501B1 (fr) | 1994-01-26 | 1996-04-05 | Commissariat Energie Atomique | Procédé de dépôt de lames semiconductrices sur un support. |
FR2715502B1 (fr) | 1994-01-26 | 1996-04-05 | Commissariat Energie Atomique | Structure présentant des cavités et procédé de réalisation d'une telle structure. |
FR2715503B1 (fr) * | 1994-01-26 | 1996-04-05 | Commissariat Energie Atomique | Substrat pour composants intégrés comportant une couche mince et son procédé de réalisation. |
JP3293736B2 (ja) * | 1996-02-28 | 2002-06-17 | キヤノン株式会社 | 半導体基板の作製方法および貼り合わせ基体 |
JP3257580B2 (ja) | 1994-03-10 | 2002-02-18 | キヤノン株式会社 | 半導体基板の作製方法 |
JPH0817777A (ja) | 1994-07-01 | 1996-01-19 | Mitsubishi Materials Shilicon Corp | シリコンウェーハの洗浄方法 |
JPH0851103A (ja) | 1994-08-08 | 1996-02-20 | Fuji Electric Co Ltd | 薄膜の生成方法 |
US5567654A (en) | 1994-09-28 | 1996-10-22 | International Business Machines Corporation | Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging |
JPH08133878A (ja) | 1994-11-11 | 1996-05-28 | Mitsubishi Materials Corp | グレーズドセラミック基板の製造方法 |
EP0717437B1 (en) | 1994-12-12 | 2002-04-24 | Advanced Micro Devices, Inc. | Method of forming buried oxide layers |
JP3381443B2 (ja) | 1995-02-02 | 2003-02-24 | ソニー株式会社 | 基体から半導体層を分離する方法、半導体素子の製造方法およびsoi基板の製造方法 |
CN1132223C (zh) | 1995-10-06 | 2003-12-24 | 佳能株式会社 | 半导体衬底及其制造方法 |
FR2744285B1 (fr) | 1996-01-25 | 1998-03-06 | Commissariat Energie Atomique | Procede de transfert d'une couche mince d'un substrat initial sur un substrat final |
FR2747506B1 (fr) | 1996-04-11 | 1998-05-15 | Commissariat Energie Atomique | Procede d'obtention d'un film mince de materiau semiconducteur comprenant notamment des composants electroniques |
FR2748851B1 (fr) | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
FR2748850B1 (fr) | 1996-05-15 | 1998-07-24 | Commissariat Energie Atomique | Procede de realisation d'un film mince de materiau solide et applications de ce procede |
JP4001650B2 (ja) | 1996-05-16 | 2007-10-31 | 株式会社リコー | 画像形成装置 |
US6054363A (en) | 1996-11-15 | 2000-04-25 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor article |
SG65697A1 (en) | 1996-11-15 | 1999-06-22 | Canon Kk | Process for producing semiconductor article |
DE19648501A1 (de) | 1996-11-22 | 1998-05-28 | Max Planck Gesellschaft | Verfahren für die lösbare Verbindung und anschließende Trennung reversibel gebondeter und polierter Scheiben sowie eine Waferstruktur und Wafer |
KR100232886B1 (ko) | 1996-11-23 | 1999-12-01 | 김영환 | Soi 웨이퍼 제조방법 |
DE19648759A1 (de) | 1996-11-25 | 1998-05-28 | Max Planck Gesellschaft | Verfahren zur Herstellung von Mikrostrukturen sowie Mikrostruktur |
FR2756847B1 (fr) | 1996-12-09 | 1999-01-08 | Commissariat Energie Atomique | Procede de separation d'au moins deux elements d'une structure en contact entre eux par implantation ionique |
KR100304161B1 (ko) | 1996-12-18 | 2001-11-30 | 미다라이 후지오 | 반도체부재의제조방법 |
JP3962465B2 (ja) | 1996-12-18 | 2007-08-22 | キヤノン株式会社 | 半導体部材の製造方法 |
JP3114643B2 (ja) | 1997-02-20 | 2000-12-04 | 日本電気株式会社 | 半導体基板の構造および製造方法 |
US6033974A (en) | 1997-05-12 | 2000-03-07 | Silicon Genesis Corporation | Method for controlled cleaving process |
US6146979A (en) | 1997-05-12 | 2000-11-14 | Silicon Genesis Corporation | Pressurized microbubble thin film separation process using a reusable substrate |
US5877070A (en) | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
US6054369A (en) | 1997-06-30 | 2000-04-25 | Intersil Corporation | Lifetime control for semiconductor devices |
WO1999001893A2 (de) | 1997-06-30 | 1999-01-14 | MAX-PLANCK-Gesellschaft zur Förderung der Wissenschaften e.V. | Verfahren zur herstellung von schichtartigen gebilden auf einem substrat, substrat sowie mittels des verfahrens hergestellte halbleiterbauelemente |
US6534380B1 (en) | 1997-07-18 | 2003-03-18 | Denso Corporation | Semiconductor substrate and method of manufacturing the same |
JPH1145862A (ja) | 1997-07-24 | 1999-02-16 | Denso Corp | 半導体基板の製造方法 |
US6103599A (en) | 1997-07-25 | 2000-08-15 | Silicon Genesis Corporation | Planarizing technique for multilayered substrates |
FR2767416B1 (fr) | 1997-08-12 | 1999-10-01 | Commissariat Energie Atomique | Procede de fabrication d'un film mince de materiau solide |
FR2767604B1 (fr) * | 1997-08-19 | 2000-12-01 | Commissariat Energie Atomique | Procede de traitement pour le collage moleculaire et le decollage de deux structures |
JPH1174208A (ja) | 1997-08-27 | 1999-03-16 | Denso Corp | 半導体基板の製造方法 |
JP3412470B2 (ja) | 1997-09-04 | 2003-06-03 | 三菱住友シリコン株式会社 | Soi基板の製造方法 |
US5981400A (en) | 1997-09-18 | 1999-11-09 | Cornell Research Foundation, Inc. | Compliant universal substrate for epitaxial growth |
JP2998724B2 (ja) | 1997-11-10 | 2000-01-11 | 日本電気株式会社 | 張り合わせsoi基板の製造方法 |
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2774510B1 (fr) | 1998-02-02 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats, notamment semi-conducteurs |
JP3031904B2 (ja) * | 1998-02-18 | 2000-04-10 | キヤノン株式会社 | 複合部材とその分離方法、及びそれを利用した半導体基体の製造方法 |
TW437078B (en) * | 1998-02-18 | 2001-05-28 | Canon Kk | Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof |
JP3809733B2 (ja) | 1998-02-25 | 2006-08-16 | セイコーエプソン株式会社 | 薄膜トランジスタの剥離方法 |
US6057212A (en) | 1998-05-04 | 2000-05-02 | International Business Machines Corporation | Method for making bonded metal back-plane substrates |
US6054370A (en) * | 1998-06-30 | 2000-04-25 | Intel Corporation | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer |
US6118181A (en) | 1998-07-29 | 2000-09-12 | Agilent Technologies, Inc. | System and method for bonding wafers |
US6271101B1 (en) | 1998-07-29 | 2001-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Process for production of SOI substrate and process for production of semiconductor device |
FR2781925B1 (fr) | 1998-07-30 | 2001-11-23 | Commissariat Energie Atomique | Transfert selectif d'elements d'un support vers un autre support |
EP0989593A3 (en) | 1998-09-25 | 2002-01-02 | Canon Kabushiki Kaisha | Substrate separating apparatus and method, and substrate manufacturing method |
FR2784795B1 (fr) | 1998-10-16 | 2000-12-01 | Commissariat Energie Atomique | Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure |
FR2789518B1 (fr) | 1999-02-10 | 2003-06-20 | Commissariat Energie Atomique | Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure |
WO2000063965A1 (en) | 1999-04-21 | 2000-10-26 | Silicon Genesis Corporation | Treatment method of cleaved film for the manufacture of substrates |
JP2001015721A (ja) | 1999-04-30 | 2001-01-19 | Canon Inc | 複合部材の分離方法及び薄膜の製造方法 |
US6664169B1 (en) | 1999-06-08 | 2003-12-16 | Canon Kabushiki Kaisha | Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus |
US6362082B1 (en) * | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
FR2796491B1 (fr) * | 1999-07-12 | 2001-08-31 | Commissariat Energie Atomique | Procede de decollement de deux elements et dispositif pour sa mise en oeuvre |
WO2001011930A2 (en) | 1999-08-10 | 2001-02-15 | Silicon Genesis Corporation | A cleaving process to fabricate multilayered substrates using low implantation doses |
DE19958803C1 (de) | 1999-12-07 | 2001-08-30 | Fraunhofer Ges Forschung | Verfahren und Vorrichtung zum Handhaben von Halbleitersubstraten bei der Prozessierung und/oder Bearbeitung |
FR2811807B1 (fr) | 2000-07-12 | 2003-07-04 | Commissariat Energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
FR2818010B1 (fr) | 2000-12-08 | 2003-09-05 | Commissariat Energie Atomique | Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses |
US6774010B2 (en) | 2001-01-25 | 2004-08-10 | International Business Machines Corporation | Transferable device-containing layer for silicon-on-insulator applications |
FR2823373B1 (fr) | 2001-04-10 | 2005-02-04 | Soitec Silicon On Insulator | Dispositif de coupe de couche d'un substrat, et procede associe |
FR2823596B1 (fr) | 2001-04-13 | 2004-08-20 | Commissariat Energie Atomique | Substrat ou structure demontable et procede de realisation |
US6759282B2 (en) | 2001-06-12 | 2004-07-06 | International Business Machines Corporation | Method and structure for buried circuits and devices |
US6645831B1 (en) | 2002-05-07 | 2003-11-11 | Intel Corporation | Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide |
US7535100B2 (en) | 2002-07-12 | 2009-05-19 | The United States Of America As Represented By The Secretary Of The Navy | Wafer bonding of thinned electronic materials and circuits to high performance substrates |
JP4199504B2 (ja) | 2002-09-24 | 2008-12-17 | イーグル工業株式会社 | 摺動部品及びその製造方法 |
US7071077B2 (en) | 2003-03-26 | 2006-07-04 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Method for preparing a bonding surface of a semiconductor layer of a wafer |
FR2855910B1 (fr) | 2003-06-06 | 2005-07-15 | Commissariat Energie Atomique | Procede d'obtention d'une couche tres mince par amincissement par auto-portage provoque |
FR2876220B1 (fr) | 2004-10-06 | 2007-09-28 | Commissariat Energie Atomique | Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees. |
FR2876219B1 (fr) | 2004-10-06 | 2006-11-24 | Commissariat Energie Atomique | Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees. |
-
2001
- 2001-04-13 FR FR0105129A patent/FR2823596B1/fr not_active Expired - Fee Related
-
2002
- 2002-04-11 US US10/468,223 patent/US7713369B2/en not_active Expired - Lifetime
- 2002-04-11 KR KR1020037013311A patent/KR100933897B1/ko active IP Right Grant
- 2002-04-11 AU AU2002304525A patent/AU2002304525A1/en not_active Abandoned
- 2002-04-11 EP EP02732806.1A patent/EP1378003B1/fr not_active Expired - Lifetime
- 2002-04-11 JP JP2002581571A patent/JP4540933B2/ja not_active Expired - Lifetime
- 2002-04-11 WO PCT/FR2002/001266 patent/WO2002084721A2/fr active Application Filing
- 2002-04-11 CN CNB028096819A patent/CN100355025C/zh not_active Expired - Lifetime
- 2002-04-12 TW TW091107432A patent/TW577102B/zh not_active IP Right Cessation
-
2009
- 2009-12-28 JP JP2009297080A patent/JP2010114456A/ja not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10163166A (ja) * | 1996-11-28 | 1998-06-19 | Mitsubishi Electric Corp | 半導体装置の製造方法及び製造装置 |
KR20000070432A (ko) * | 1997-01-27 | 2000-11-25 | 쉔느 필립 | 이온주입을 수반하여, 이온으로부터 보호된 영역을 구비하는 박막, 특히 반도체막을 얻는 방법 |
JPH11317577A (ja) * | 1997-12-02 | 1999-11-16 | Commiss Energ Atom | 第一基板上に形成された微細構造部の最終基板への選択的なトランスファープロセス |
Also Published As
Publication number | Publication date |
---|---|
CN100355025C (zh) | 2007-12-12 |
WO2002084721A2 (fr) | 2002-10-24 |
JP2004535664A (ja) | 2004-11-25 |
EP1378003B1 (fr) | 2017-11-08 |
FR2823596B1 (fr) | 2004-08-20 |
TW577102B (en) | 2004-02-21 |
CN1528009A (zh) | 2004-09-08 |
EP1378003A2 (fr) | 2004-01-07 |
US20050029224A1 (en) | 2005-02-10 |
FR2823596A1 (fr) | 2002-10-18 |
US7713369B2 (en) | 2010-05-11 |
KR20040000425A (ko) | 2004-01-03 |
JP2010114456A (ja) | 2010-05-20 |
AU2002304525A1 (en) | 2002-10-28 |
WO2002084721A3 (fr) | 2003-11-06 |
JP4540933B2 (ja) | 2010-09-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100933897B1 (ko) | 분리가능 기판 또는 분리가능 구조체 및 그 생산방법 | |
KR100991395B1 (ko) | 제어된 기계적 강도를 가진 분리가능 구조물 및 동 구조물을 생산하는 방법 | |
US7045878B2 (en) | Selectively bonded thin film layer and substrate layer for processing of useful devices | |
CN101355013B (zh) | 制备无排除区的外延用结构的工艺 | |
JP5031364B2 (ja) | エピタキシャル成長層の形成方法 | |
US8754505B2 (en) | Method of producing a heterostructure with local adaptation of the thermal expansion coefficient | |
KR20040051605A (ko) | 미세 구성요소를 가지고 있는 박층의 제조방법 | |
JP2010538459A (ja) | 熱処理を用いる剥離プロセスにおける半導体ウエハの再使用 | |
US7176554B2 (en) | Methods for producing a semiconductor entity | |
US7439160B2 (en) | Methods for producing a semiconductor entity | |
JP2006086388A (ja) | 半導体薄膜の表面処理方法、及び半導体素子の分離方法 | |
US20120241918A1 (en) | Process for the realization of islands of at least partially relaxed strained material | |
JP2007036279A (ja) | 半導体基板の作製方法 | |
JP3013932B2 (ja) | 半導体部材の製造方法および半導体部材 | |
WO2011018780A1 (en) | A process for manufacturing a hybrid substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
AMND | Amendment | ||
E902 | Notification of reason for refusal | ||
AMND | Amendment | ||
E902 | Notification of reason for refusal | ||
AMND | Amendment | ||
E601 | Decision to refuse application | ||
J201 | Request for trial against refusal decision | ||
AMND | Amendment | ||
B701 | Decision to grant | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20121129 Year of fee payment: 4 |
|
FPAY | Annual fee payment |
Payment date: 20131128 Year of fee payment: 5 |
|
FPAY | Annual fee payment |
Payment date: 20141125 Year of fee payment: 6 |
|
FPAY | Annual fee payment |
Payment date: 20151125 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20161125 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20171127 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20191125 Year of fee payment: 11 |