KR100873759B1 - 반도체 집적 회로 장치의 제조 방법 - Google Patents
반도체 집적 회로 장치의 제조 방법 Download PDFInfo
- Publication number
- KR100873759B1 KR100873759B1 KR1020020011898A KR20020011898A KR100873759B1 KR 100873759 B1 KR100873759 B1 KR 100873759B1 KR 1020020011898 A KR1020020011898 A KR 1020020011898A KR 20020011898 A KR20020011898 A KR 20020011898A KR 100873759 B1 KR100873759 B1 KR 100873759B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- semiconductor wafer
- film
- polishing
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Element Separation (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001118413A JP2002313757A (ja) | 2001-04-17 | 2001-04-17 | 半導体集積回路装置の製造方法 |
| JPJP-P-2001-00118413 | 2001-04-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020081544A KR20020081544A (ko) | 2002-10-28 |
| KR100873759B1 true KR100873759B1 (ko) | 2008-12-15 |
Family
ID=18968809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020011898A Expired - Fee Related KR100873759B1 (ko) | 2001-04-17 | 2002-03-06 | 반도체 집적 회로 장치의 제조 방법 |
Country Status (4)
| Country | Link |
|---|---|
| US (4) | US6979649B2 (enExample) |
| JP (1) | JP2002313757A (enExample) |
| KR (1) | KR100873759B1 (enExample) |
| TW (1) | TW567550B (enExample) |
Families Citing this family (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002313757A (ja) * | 2001-04-17 | 2002-10-25 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| CN102594329A (zh) * | 2001-07-03 | 2012-07-18 | 布拉德伯里·R·法塞 | 自供电开关启动系统 |
| JP2004152920A (ja) * | 2002-10-30 | 2004-05-27 | Fujitsu Ltd | 半導体装置の製造方法及び半導体製造工程の管理方法 |
| US20050266679A1 (en) * | 2004-05-26 | 2005-12-01 | Jing-Cheng Lin | Barrier structure for semiconductor devices |
| US20050263891A1 (en) * | 2004-05-28 | 2005-12-01 | Bih-Huey Lee | Diffusion barrier for damascene structures |
| US20060019417A1 (en) * | 2004-07-26 | 2006-01-26 | Atsushi Shigeta | Substrate processing method and substrate processing apparatus |
| US7841144B2 (en) | 2005-03-30 | 2010-11-30 | Valinge Innovation Ab | Mechanical locking system for panels and method of installing same |
| JP4815801B2 (ja) * | 2004-12-28 | 2011-11-16 | 信越半導体株式会社 | シリコンウエーハの研磨方法および製造方法および円板状ワークの研磨装置ならびにシリコンウエーハ |
| US20060159964A1 (en) * | 2005-01-19 | 2006-07-20 | Shin-Etsu Chemical Co., Ltd. | Method for manufacturing a surface-treated silicon substrate for magnetic recording medium |
| JP4516445B2 (ja) * | 2005-02-18 | 2010-08-04 | パナソニック株式会社 | 半導体装置の製造方法 |
| US20060266383A1 (en) * | 2005-05-31 | 2006-11-30 | Texas Instruments Incorporated | Systems and methods for removing wafer edge residue and debris using a wafer clean solution |
| US7998865B2 (en) * | 2005-05-31 | 2011-08-16 | Texas Instruments Incorporated | Systems and methods for removing wafer edge residue and debris using a residue remover mechanism |
| JP2007012943A (ja) * | 2005-06-30 | 2007-01-18 | Toshiba Corp | 基板処理方法 |
| FR2888400B1 (fr) * | 2005-07-08 | 2007-10-19 | Soitec Silicon On Insulator | Procede de prelevement de couche |
| US7438250B2 (en) * | 2005-11-23 | 2008-10-21 | Suncast Corporation | Low entry hose reel device with elevated point of operation |
| DE102005056364B3 (de) * | 2005-11-25 | 2007-08-16 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Bipolarer Trägerwafer und mobile, bipolare, elektrostatische Waferanordnung |
| KR100758494B1 (ko) * | 2005-12-28 | 2007-09-12 | 동부일렉트로닉스 주식회사 | 반도체 장치의 소자 분리 영역 및 그 형성 방법 |
| JP2007208161A (ja) * | 2006-02-06 | 2007-08-16 | Renesas Technology Corp | 半導体装置の製造方法および半導体基板 |
| US20070257366A1 (en) * | 2006-05-03 | 2007-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer for semiconductor interconnect structure |
| US20080268660A1 (en) * | 2007-04-25 | 2008-10-30 | Takaharu Itani | Method of manufacturing semiconductor device |
| JP2008306179A (ja) * | 2007-05-21 | 2008-12-18 | Applied Materials Inc | バッキングパッドを使用して基板の両面の縁部から膜及び薄片を除去する方法及び装置 |
| JP2009004765A (ja) * | 2007-05-21 | 2009-01-08 | Applied Materials Inc | 基板研磨のためにローリングバッキングパッドを使用する方法及び装置 |
| US7858513B2 (en) * | 2007-06-18 | 2010-12-28 | Organicid, Inc. | Fabrication of self-aligned via holes in polymer thin films |
| US8264072B2 (en) | 2007-10-22 | 2012-09-11 | Infineon Technologies Ag | Electronic device |
| US7888169B2 (en) * | 2007-12-26 | 2011-02-15 | Organicid, Inc. | Organic semiconductor device and method of manufacturing the same |
| JP4395812B2 (ja) * | 2008-02-27 | 2010-01-13 | 住友電気工業株式会社 | 窒化物半導体ウエハ−加工方法 |
| US7833907B2 (en) * | 2008-04-23 | 2010-11-16 | International Business Machines Corporation | CMP methods avoiding edge erosion and related wafer |
| JP5125743B2 (ja) * | 2008-05-09 | 2013-01-23 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| JP5083252B2 (ja) * | 2009-03-13 | 2012-11-28 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| JP5571409B2 (ja) | 2010-02-22 | 2014-08-13 | 株式会社荏原製作所 | 半導体装置の製造方法 |
| JP2012216812A (ja) * | 2011-03-31 | 2012-11-08 | Elpida Memory Inc | 半導体装置及びその製造方法 |
| US8629037B2 (en) * | 2011-09-24 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming a protective film on a back side of a silicon wafer in a III-V family fabrication process |
| JP6130995B2 (ja) * | 2012-02-20 | 2017-05-17 | サンケン電気株式会社 | エピタキシャル基板及び半導体装置 |
| KR20130128227A (ko) * | 2012-05-16 | 2013-11-26 | 삼성전자주식회사 | 전자소자 탑재용 기판의 제조방법 |
| US8851413B2 (en) | 2012-11-02 | 2014-10-07 | Suncast Technologies, Llc | Reel assembly |
| US9287127B2 (en) | 2014-02-17 | 2016-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wafer back-side polishing system and method for integrated circuit device manufacturing processes |
| JP6304445B2 (ja) * | 2015-03-16 | 2018-04-04 | 富士電機株式会社 | 半導体装置の製造方法 |
| JP7016032B2 (ja) * | 2019-09-24 | 2022-02-04 | 日亜化学工業株式会社 | 半導体素子の製造方法 |
| US11201134B2 (en) * | 2020-04-20 | 2021-12-14 | United Microelectronics Corp. | Method of manufacturing semiconductor device |
| US12482665B2 (en) * | 2023-02-03 | 2025-11-25 | Nanya Technology Corporation | Method of manufacturing semiconductor structure |
| US12482664B2 (en) | 2023-02-03 | 2025-11-25 | Nanya Technology Corporation | Method of manufacturing semiconductor structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09186234A (ja) * | 1995-12-27 | 1997-07-15 | Sony Corp | 半導体装置の製造方法およびその製造装置 |
| JPH1145868A (ja) * | 1997-07-25 | 1999-02-16 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| JP2000021882A (ja) * | 1998-07-01 | 2000-01-21 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
| JP2001077113A (ja) * | 1999-09-02 | 2001-03-23 | Nec Corp | 銅配線の形成方法および銅配線の形成された半導体ウエハ |
Family Cites Families (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0761601B2 (ja) | 1987-09-14 | 1995-07-05 | スピードファム株式会社 | ウエハの鏡面加工方法 |
| JPH0434931A (ja) | 1990-05-31 | 1992-02-05 | Oki Electric Ind Co Ltd | 半導体ウエハおよびその処理方法 |
| JPH0541449A (ja) | 1991-08-06 | 1993-02-19 | Sony Corp | 半導体ウエハ |
| US5861066A (en) | 1996-05-01 | 1999-01-19 | Ontrak Systems, Inc. | Method and apparatus for cleaning edges of contaminated substrates |
| US5862560A (en) | 1996-08-29 | 1999-01-26 | Ontrak Systems, Inc. | Roller with treading and system including the same |
| US5937469A (en) | 1996-12-03 | 1999-08-17 | Intel Corporation | Apparatus for mechanically cleaning the edges of wafers |
| US5901399A (en) | 1996-12-30 | 1999-05-11 | Intel Corporation | Flexible-leaf substrate edge cleaning apparatus |
| US5868857A (en) | 1996-12-30 | 1999-02-09 | Intel Corporation | Rotating belt wafer edge cleaning apparatus |
| JPH10296641A (ja) | 1997-04-30 | 1998-11-10 | Speedfam Co Ltd | エッジポリッシング装置の研磨ドラム |
| JPH10309666A (ja) | 1997-05-09 | 1998-11-24 | Speedfam Co Ltd | エッジポリッシング装置及びその方法 |
| JP3111928B2 (ja) | 1997-05-14 | 2000-11-27 | 日本電気株式会社 | 金属膜の研磨方法 |
| JPH10328989A (ja) | 1997-06-02 | 1998-12-15 | Speedfam Co Ltd | ウエハエッジの鏡面研磨方法及び装置 |
| JPH1148109A (ja) | 1997-06-04 | 1999-02-23 | Speedfam Co Ltd | ワークエッジの鏡面研磨方法及び装置 |
| US5874778A (en) | 1997-06-11 | 1999-02-23 | International Business Machines Corporation | Embedded power and ground plane structure |
| JPH1133888A (ja) | 1997-07-24 | 1999-02-09 | Super Silicon Kenkyusho:Kk | ウェーハの鏡面面取り装置 |
| US6159081A (en) * | 1997-09-09 | 2000-12-12 | Hakomori; Shunji | Method and apparatus for mirror-polishing of workpiece edges |
| JPH1190803A (ja) | 1997-09-11 | 1999-04-06 | Speedfam Co Ltd | ワークエッジの鏡面研磨装置 |
| JPH11104942A (ja) | 1997-10-02 | 1999-04-20 | Speedfam Co Ltd | ワークエッジの研磨方法及び装置 |
| JP3875375B2 (ja) * | 1997-10-06 | 2007-01-31 | 株式会社ルネサステクノロジ | 半導体装置の製造方法および半導体基板 |
| JP3599548B2 (ja) | 1997-12-18 | 2004-12-08 | 株式会社日立製作所 | 半導体集積回路装置の製造方法 |
| JPH11204452A (ja) * | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | 半導体基板の処理方法および半導体基板 |
| JP2000173885A (ja) | 1998-03-09 | 2000-06-23 | Seiko Epson Corp | 半導体装置の製造方法 |
| JP3437771B2 (ja) | 1998-08-20 | 2003-08-18 | 株式会社東芝 | 半導体装置の製造方法 |
| JP2000077414A (ja) | 1998-09-02 | 2000-03-14 | Seiko Epson Corp | 半導体装置の製造方法 |
| JP2000208618A (ja) | 1999-01-08 | 2000-07-28 | Seiko Epson Corp | 半導体装置の製造方法および半導体装置 |
| JP3395696B2 (ja) | 1999-03-15 | 2003-04-14 | 日本電気株式会社 | ウェハ処理装置およびウェハ処理方法 |
| US6267649B1 (en) | 1999-08-23 | 2001-07-31 | Industrial Technology Research Institute | Edge and bevel CMP of copper wafer |
| US6309981B1 (en) | 1999-10-01 | 2001-10-30 | Novellus Systems, Inc. | Edge bevel removal of copper from silicon wafers |
| KR100773165B1 (ko) | 1999-12-24 | 2007-11-02 | 가부시키가이샤 에바라 세이사꾸쇼 | 반도체기판처리장치 및 처리방법 |
| JP3907151B2 (ja) * | 2000-01-25 | 2007-04-18 | 株式会社東芝 | 半導体装置の製造方法 |
| JP2001308097A (ja) * | 2000-04-27 | 2001-11-02 | Nec Corp | 半導体装置およびその製造方法 |
| JP4067307B2 (ja) | 2000-04-27 | 2008-03-26 | 株式会社荏原製作所 | 回転保持装置 |
| JP2001345294A (ja) * | 2000-05-31 | 2001-12-14 | Toshiba Corp | 半導体装置の製造方法 |
| US6709563B2 (en) | 2000-06-30 | 2004-03-23 | Ebara Corporation | Copper-plating liquid, plating method and plating apparatus |
| US6482749B1 (en) * | 2000-08-10 | 2002-11-19 | Seh America, Inc. | Method for etching a wafer edge using a potassium-based chemical oxidizer in the presence of hydrofluoric acid |
| JP4034931B2 (ja) | 2000-11-29 | 2008-01-16 | 京セラ株式会社 | 被覆超硬合金部材およびその製造方法 |
| US6509270B1 (en) * | 2001-03-30 | 2003-01-21 | Cypress Semiconductor Corp. | Method for polishing a semiconductor topography |
| JP2002313757A (ja) * | 2001-04-17 | 2002-10-25 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
-
2001
- 2001-04-17 JP JP2001118413A patent/JP2002313757A/ja active Pending
-
2002
- 2002-02-25 TW TW091103286A patent/TW567550B/zh not_active IP Right Cessation
- 2002-03-01 US US10/085,063 patent/US6979649B2/en not_active Expired - Lifetime
- 2002-03-06 KR KR1020020011898A patent/KR100873759B1/ko not_active Expired - Fee Related
-
2005
- 2005-06-28 US US11/167,253 patent/US7250365B2/en not_active Expired - Fee Related
-
2007
- 2007-07-16 US US11/778,494 patent/US7718526B2/en not_active Expired - Lifetime
-
2010
- 2010-05-18 US US12/781,816 patent/US7977234B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09186234A (ja) * | 1995-12-27 | 1997-07-15 | Sony Corp | 半導体装置の製造方法およびその製造装置 |
| JPH1145868A (ja) * | 1997-07-25 | 1999-02-16 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| JP2000021882A (ja) * | 1998-07-01 | 2000-01-21 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
| JP2001077113A (ja) * | 1999-09-02 | 2001-03-23 | Nec Corp | 銅配線の形成方法および銅配線の形成された半導体ウエハ |
Also Published As
| Publication number | Publication date |
|---|---|
| US7718526B2 (en) | 2010-05-18 |
| US20100227474A1 (en) | 2010-09-09 |
| JP2002313757A (ja) | 2002-10-25 |
| US20050250331A1 (en) | 2005-11-10 |
| US7250365B2 (en) | 2007-07-31 |
| KR20020081544A (ko) | 2002-10-28 |
| TW567550B (en) | 2003-12-21 |
| US7977234B2 (en) | 2011-07-12 |
| US20020160610A1 (en) | 2002-10-31 |
| US20070259522A1 (en) | 2007-11-08 |
| US6979649B2 (en) | 2005-12-27 |
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