KR100698987B1 - 반도체 집적 회로 장치의 제조 방법 - Google Patents

반도체 집적 회로 장치의 제조 방법 Download PDF

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Publication number
KR100698987B1
KR100698987B1 KR1020010018003A KR20010018003A KR100698987B1 KR 100698987 B1 KR100698987 B1 KR 100698987B1 KR 1020010018003 A KR1020010018003 A KR 1020010018003A KR 20010018003 A KR20010018003 A KR 20010018003A KR 100698987 B1 KR100698987 B1 KR 100698987B1
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South Korea
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film
wiring
copper
groove
integrated circuit
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Expired - Fee Related
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Korean (ko)
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KR20010095332A (ko
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노구찌준지
오하시나오후미
사이또다쯔유끼
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가부시키가이샤 히타치세이사쿠쇼
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Assigned to 르네사스 일렉트로닉스 가부시키가이샤 reassignment 르네사스 일렉트로닉스 가부시키가이샤 권리의 전부이전등록 Assignors: 가부시키가이샤 히타치세이사쿠쇼
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
    • H10P70/234—Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/277—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a planarisation of conductive layers
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0468—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H10P72/0472—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one polishing chamber
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/055—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
KR1020010018003A 2000-04-05 2001-04-04 반도체 집적 회로 장치의 제조 방법 Expired - Fee Related KR100698987B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000-104015 2000-04-05
JP2000104015A JP2001291720A (ja) 2000-04-05 2000-04-05 半導体集積回路装置および半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
KR20010095332A KR20010095332A (ko) 2001-11-03
KR100698987B1 true KR100698987B1 (ko) 2007-03-26

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Country Status (4)

Country Link
US (3) US6764950B2 (https=)
JP (1) JP2001291720A (https=)
KR (1) KR100698987B1 (https=)
TW (1) TW531892B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101119649B1 (ko) * 2007-03-13 2012-03-14 후지쯔 가부시끼가이샤 반도체 장치 및 반도체 장치의 제조 방법

Families Citing this family (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4554011B2 (ja) * 1999-08-10 2010-09-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
US7034402B1 (en) * 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
TW462085B (en) * 2000-10-26 2001-11-01 United Microelectronics Corp Planarization of organic silicon low dielectric constant material by chemical mechanical polishing
JP4535629B2 (ja) * 2001-02-21 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6727158B2 (en) * 2001-11-08 2004-04-27 Micron Technology, Inc. Structure and method for forming a faceted opening and a layer filling therein
CN1207773C (zh) 2001-12-27 2005-06-22 松下电器产业株式会社 布线结构的形成方法
CN1198331C (zh) 2001-12-27 2005-04-20 松下电器产业株式会社 布线结构的形成方法
CN1220259C (zh) 2001-12-27 2005-09-21 松下电器产业株式会社 布线结构的形成方法
JP4340040B2 (ja) * 2002-03-28 2009-10-07 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP2003318140A (ja) * 2002-04-26 2003-11-07 Applied Materials Inc 研磨方法及び装置
US7687917B2 (en) 2002-05-08 2010-03-30 Nec Electronics Corporation Single damascene structure semiconductor device having silicon-diffused metal wiring layer
TWI288443B (en) 2002-05-17 2007-10-11 Semiconductor Energy Lab SiN film, semiconductor device, and the manufacturing method thereof
DE10224167B4 (de) 2002-05-31 2007-01-25 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Kupferleitung mit erhöhter Widerstandsfähigkeit gegen Elektromigration in einem Halbleiterelement
CN100352036C (zh) 2002-10-17 2007-11-28 株式会社瑞萨科技 半导体器件及其制造方法
JP4454242B2 (ja) 2003-03-25 2010-04-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP2004363516A (ja) * 2003-06-09 2004-12-24 Sony Corp 埋め込み配線の形成方法
JP2005050903A (ja) * 2003-07-30 2005-02-24 Toshiba Corp 半導体装置およびその製造方法
US20050054206A1 (en) * 2003-09-04 2005-03-10 Nanya Technology Corporation Etching method and recipe for forming high aspect ratio contact hole
US20060172526A1 (en) * 2003-10-16 2006-08-03 United Microelectronics Corp. Method for preventing edge peeling defect
US7341946B2 (en) * 2003-11-10 2008-03-11 Novellus Systems, Inc. Methods for the electrochemical deposition of copper onto a barrier layer of a work piece
US7180195B2 (en) * 2003-12-17 2007-02-20 Intel Corporation Method and apparatus for improved power routing
SG157226A1 (en) * 2004-02-24 2009-12-29 Taiwan Semiconductor Mfg A method for improving time dependent dielectric breakdown lifetimes
US20050230354A1 (en) * 2004-04-14 2005-10-20 Hardikar Vishwas V Method and composition of post-CMP wetting of thin films
JP4703129B2 (ja) * 2004-05-06 2011-06-15 富士通セミコンダクター株式会社 半導体装置およびその製造方法、設計方法
US7465595B2 (en) * 2004-11-09 2008-12-16 Fujitsu Limited Quantum device, manufacturing method of the same and controlling method of the same
US7332422B2 (en) * 2005-01-05 2008-02-19 Chartered Semiconductor Manufacturing, Ltd. Method for CuO reduction by using two step nitrogen oxygen and reducing plasma treatment
US20060194427A1 (en) * 2005-02-25 2006-08-31 Yi-Ching Wu Interconnecting process and method for fabricating complex dielectric barrier layer
US7348276B2 (en) * 2005-03-30 2008-03-25 Fujitsu, Limited Fabrication process of semiconductor device and polishing method
US7288488B2 (en) * 2005-05-10 2007-10-30 Lam Research Corporation Method for resist strip in presence of regular low k and/or porous low k dielectric materials
JP4956919B2 (ja) * 2005-06-08 2012-06-20 株式会社日立製作所 半導体装置およびその製造方法
KR101168728B1 (ko) * 2005-07-15 2012-07-26 삼성전자주식회사 배선 구조와 배선 형성 방법 및 박막 트랜지스터 기판과 그제조 방법
JP4964442B2 (ja) * 2005-08-10 2012-06-27 三菱電機株式会社 薄膜トランジスタおよびその製造方法
US7348238B2 (en) * 2005-08-22 2008-03-25 Micron Technology, Inc. Bottom electrode for memory device and method of forming the same
KR100741882B1 (ko) * 2005-12-29 2007-07-23 동부일렉트로닉스 주식회사 고전압 소자 및 그 제조방법
US7378339B2 (en) * 2006-03-30 2008-05-27 Freescale Semiconductor, Inc. Barrier for use in 3-D integration of circuits
US7510967B2 (en) * 2006-05-29 2009-03-31 Nec Electronics Corporation Method for manufacturing semiconductor device
US20080299780A1 (en) * 2007-06-01 2008-12-04 Uv Tech Systems, Inc. Method and apparatus for laser oxidation and reduction
DE102007035266B4 (de) * 2007-07-27 2010-03-25 Siltronic Ag Verfahren zum Polieren eines Substrates aus Silicium oder einer Legierung aus Silicium und Germanium
US7758403B2 (en) * 2007-11-16 2010-07-20 Hitachi Global Storage Technologies Netherlands B.V. System, method and apparatus for lapping workpieces with soluble abrasives
US8517990B2 (en) * 2007-12-18 2013-08-27 Hospira, Inc. User interface improvements for medical devices
JP4778018B2 (ja) * 2008-04-23 2011-09-21 富士通セミコンダクター株式会社 絶縁膜形成方法
US8138041B2 (en) * 2008-06-12 2012-03-20 International Business Machines Corporation In-situ silicon cap for metal gate electrode
CN102077323A (zh) * 2008-07-03 2011-05-25 株式会社神户制钢所 配线结构、薄膜晶体管基板及其制造方法、以及显示装置
CN102203935A (zh) * 2008-10-27 2011-09-28 Nxp股份有限公司 生物兼容电极
US8513119B2 (en) 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US20100171197A1 (en) 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US20110052797A1 (en) * 2009-08-26 2011-03-03 International Business Machines Corporation Low Temperature Plasma-Free Method for the Nitridation of Copper
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
JP5859758B2 (ja) * 2011-07-05 2016-02-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8525339B2 (en) 2011-07-27 2013-09-03 International Business Machines Corporation Hybrid copper interconnect structure and method of fabricating same
JP2014027012A (ja) * 2012-07-24 2014-02-06 Toshiba Corp 半導体装置の製造方法および半導体装置の製造装置
KR20140028735A (ko) * 2012-08-30 2014-03-10 에스케이하이닉스 주식회사 반도체 메모리 소자 및 그 제조방법
US9312203B2 (en) 2013-01-02 2016-04-12 Globalfoundries Inc. Dual damascene structure with liner
JP6255728B2 (ja) * 2013-06-17 2018-01-10 富士通セミコンダクター株式会社 半導体装置、半導体装置の製造方法及び設計プログラム
JP5694503B2 (ja) * 2013-12-27 2015-04-01 Jx日鉱日石金属株式会社 自己拡散抑制機能を有するシード層及び自己拡散抑制機能を備えたシード層の形成方法
JP2016219620A (ja) * 2015-05-21 2016-12-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法およびそれに用いられるｆｏｕｐ
US9887160B2 (en) * 2015-09-24 2018-02-06 International Business Machines Corporation Multiple pre-clean processes for interconnect fabrication
US20180134546A1 (en) * 2016-11-14 2018-05-17 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
JP6352490B2 (ja) * 2017-04-24 2018-07-04 ルネサスエレクトロニクス株式会社 半導体装置
US11195748B2 (en) * 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
KR102492733B1 (ko) 2017-09-29 2023-01-27 삼성디스플레이 주식회사 구리 플라즈마 식각 방법 및 디스플레이 패널 제조 방법
US11139242B2 (en) * 2019-04-29 2021-10-05 International Business Machines Corporation Via-to-metal tip connections in multi-layer chips
US11152455B2 (en) 2019-09-23 2021-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method to reduce breakdown failure in a MIM capacitor
US11810857B2 (en) * 2020-08-25 2023-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Via for semiconductor device and method
CN112038228B (zh) * 2020-08-27 2022-08-09 上海华力集成电路制造有限公司 改善TiN薄膜连续性的表面处理方法
US11430729B2 (en) 2020-09-16 2022-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. MIM capacitor with a symmetrical capacitor insulator structure
US20250006638A1 (en) * 2023-06-30 2025-01-02 International Business Machines Corporation Pitch change between metal lines
KR102821382B1 (ko) * 2023-08-16 2025-06-17 주식회사 라온텍 마이크로 디스플레이 장치의 액정 표시 소자 및 제조 방법
CN118471905B (zh) * 2024-07-10 2024-09-27 合肥欧益睿芯科技有限公司 半导体器件及其制造方法、电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0969522A (ja) * 1995-09-01 1997-03-11 Fujitsu Ltd 埋め込み導電層の形成方法
KR0161883B1 (ko) * 1995-05-23 1999-02-01 문정환 반도체장치의 금속배선 형성방법
JPH11204523A (ja) * 1998-01-07 1999-07-30 Toshiba Corp 半導体装置の製造方法
KR19990081775A (ko) * 1998-04-09 1999-11-15 아끼구사 나오유끼 반도체 장치 및 그 제조 방법
KR20000017634A (ko) * 1998-08-31 2000-03-25 가나이 쓰토무 반도체 장치 및 그 제조 방법

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3072807B2 (ja) 1992-07-15 2000-08-07 日本電信電話株式会社 半導体装置の製造方法
JP3156886B2 (ja) 1993-01-26 2001-04-16 日本電信電話株式会社 半導体装置の製造方法
JPH0922896A (ja) * 1995-07-07 1997-01-21 Toshiba Corp 金属膜の選択的形成方法
JPH0982798A (ja) 1995-09-12 1997-03-28 Toshiba Corp 半導体装置およびその製造方法
US5990008A (en) * 1996-09-25 1999-11-23 Kabushiki Kaisha Toshiba Semiconductor device with pure copper wirings and method of manufacturing a semiconductor device with pure copper wirings
JPH10154709A (ja) 1996-09-25 1998-06-09 Toshiba Corp 半導体装置の製造方法
US6537621B1 (en) * 1996-10-01 2003-03-25 Tokyo Electron Limited Method of forming a titanium film and a barrier film on a surface of a substrate through lamination
JPH10125782A (ja) * 1996-10-15 1998-05-15 Sony Corp 半導体装置の製造方法
US5954997A (en) * 1996-12-09 1999-09-21 Cabot Corporation Chemical mechanical polishing slurry useful for copper substrates
JP3150095B2 (ja) 1996-12-12 2001-03-26 日本電気株式会社 多層配線構造の製造方法
US6048789A (en) 1997-02-27 2000-04-11 Vlsi Technology, Inc. IC interconnect formation with chemical-mechanical polishing and silica etching with solution of nitric and hydrofluoric acids
US6191007B1 (en) 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
JPH1116912A (ja) 1997-06-25 1999-01-22 Hitachi Ltd 半導体集積回路装置の製造方法および半導体集積回路装置の製造装置
JP3463979B2 (ja) * 1997-07-08 2003-11-05 富士通株式会社 半導体装置の製造方法
JPH1187349A (ja) 1997-07-16 1999-03-30 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
US6171957B1 (en) * 1997-07-16 2001-01-09 Mitsubishi Denki Kabushiki Kaisha Manufacturing method of semiconductor device having high pressure reflow process
US5904565A (en) 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
JPH11220023A (ja) 1998-02-02 1999-08-10 Sharp Corp 半導体装置及びその製造方法
US6181012B1 (en) * 1998-04-27 2001-01-30 International Business Machines Corporation Copper interconnection structure incorporating a metal seed layer
JP3080071B2 (ja) * 1998-06-12 2000-08-21 日本電気株式会社 半導体装置及びその製造方法
US6355571B1 (en) 1998-11-17 2002-03-12 Applied Materials, Inc. Method and apparatus for reducing copper oxidation and contamination in a semiconductor device
US6177364B1 (en) * 1998-12-02 2001-01-23 Advanced Micro Devices, Inc. Integration of low-K SiOF for damascene structure
US6153523A (en) 1998-12-09 2000-11-28 Advanced Micro Devices, Inc. Method of forming high density capping layers for copper interconnects with improved adhesion
US6242349B1 (en) * 1998-12-09 2001-06-05 Advanced Micro Devices, Inc. Method of forming copper/copper alloy interconnection with reduced electromigration
JP3974284B2 (ja) 1999-03-18 2007-09-12 株式会社東芝 半導体装置の製造方法
US6169036B1 (en) * 1999-03-25 2001-01-02 Lucent Technologies Inc. Method for cleaning via openings in integrated circuit manufacturing
US6177347B1 (en) * 1999-07-02 2001-01-23 Taiwan Semiconductor Manufacturing Company In-situ cleaning process for Cu metallization
US6159857A (en) 1999-07-08 2000-12-12 Taiwan Semiconductor Manufacturing Company Robust post Cu-CMP IMD process
US6521532B1 (en) 1999-07-22 2003-02-18 James A. Cunningham Method for making integrated circuit including interconnects with enhanced electromigration resistance
US6136680A (en) * 2000-01-21 2000-10-24 Taiwan Semiconductor Manufacturing Company Methods to improve copper-fluorinated silica glass interconnects
US6284657B1 (en) * 2000-02-25 2001-09-04 Chartered Semiconductor Manufacturing Ltd. Non-metallic barrier formation for copper damascene type interconnects
US6348410B1 (en) * 2000-11-02 2002-02-19 Advanced Micro Devices, Inc. Low temperature hillock suppression method in integrated circuit interconnects

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0161883B1 (ko) * 1995-05-23 1999-02-01 문정환 반도체장치의 금속배선 형성방법
JPH0969522A (ja) * 1995-09-01 1997-03-11 Fujitsu Ltd 埋め込み導電層の形成方法
JPH11204523A (ja) * 1998-01-07 1999-07-30 Toshiba Corp 半導体装置の製造方法
KR19990081775A (ko) * 1998-04-09 1999-11-15 아끼구사 나오유끼 반도체 장치 및 그 제조 방법
KR20000017634A (ko) * 1998-08-31 2000-03-25 가나이 쓰토무 반도체 장치 및 그 제조 방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101119649B1 (ko) * 2007-03-13 2012-03-14 후지쯔 가부시끼가이샤 반도체 장치 및 반도체 장치의 제조 방법
US8378489B2 (en) 2007-03-13 2013-02-19 Fujitsu Limited Semiconductor device and manufacturing method therefor

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US6764950B2 (en) 2004-07-20
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US20010030367A1 (en) 2001-10-18

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