JP2001291720A - 半導体集積回路装置および半導体集積回路装置の製造方法 - Google Patents

半導体集積回路装置および半導体集積回路装置の製造方法

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Publication number
JP2001291720A
JP2001291720A JP2000104015A JP2000104015A JP2001291720A JP 2001291720 A JP2001291720 A JP 2001291720A JP 2000104015 A JP2000104015 A JP 2000104015A JP 2000104015 A JP2000104015 A JP 2000104015A JP 2001291720 A JP2001291720 A JP 2001291720A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
semiconductor integrated
film
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000104015A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001291720A5 (https=
Inventor
Junji Noguchi
純司 野口
Tadashi Ohashi
直史 大橋
Tatsuyuki Saito
達之 齋藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000104015A priority Critical patent/JP2001291720A/ja
Priority to TW090107703A priority patent/TW531892B/zh
Priority to KR1020010018003A priority patent/KR100698987B1/ko
Priority to US09/825,946 priority patent/US6764950B2/en
Publication of JP2001291720A publication Critical patent/JP2001291720A/ja
Priority to US10/811,927 priority patent/US7232757B2/en
Publication of JP2001291720A5 publication Critical patent/JP2001291720A5/ja
Priority to US11/790,760 priority patent/US20080132059A1/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69Inorganic materials
    • H10P14/694Inorganic materials composed of nitrides
    • H10P14/6943Inorganic materials composed of nitrides containing silicon
    • H10P14/69433Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326Deposition processes
    • H10P14/6328Deposition from the gas or vapour phase
    • H10P14/6334Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69Inorganic materials
    • H10P14/692Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40Chemomechanical polishing [CMP]
    • H10P52/403Chemomechanical polishing [CMP] of conductive or resistive materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00Cleaning of wafers, substrates or parts of devices
    • H10P70/20Cleaning during device manufacture
    • H10P70/23Cleaning during device manufacture during, before or after processing of insulating materials
    • H10P70/234Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00Cleaning of wafers, substrates or parts of devices
    • H10P70/20Cleaning during device manufacture
    • H10P70/27Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/277Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a planarisation of conductive layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04Apparatus for manufacture or treatment
    • H10P72/0451Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0468Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H10P72/0472Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one polishing chamber
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/055Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition
    • HELECTRICITY
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/074Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/074Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
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    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • HELECTRICITY
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/093Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • HELECTRICITY
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
JP2000104015A 2000-04-05 2000-04-05 半導体集積回路装置および半導体集積回路装置の製造方法 Pending JP2001291720A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2000104015A JP2001291720A (ja) 2000-04-05 2000-04-05 半導体集積回路装置および半導体集積回路装置の製造方法
TW090107703A TW531892B (en) 2000-04-05 2001-03-30 Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device
KR1020010018003A KR100698987B1 (ko) 2000-04-05 2001-04-04 반도체 집적 회로 장치의 제조 방법
US09/825,946 US6764950B2 (en) 2000-04-05 2001-04-05 Fabrication method for semiconductor integrated circuit device
US10/811,927 US7232757B2 (en) 2000-04-05 2004-03-30 Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device
US11/790,760 US20080132059A1 (en) 2000-04-05 2007-04-27 Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000104015A JP2001291720A (ja) 2000-04-05 2000-04-05 半導体集積回路装置および半導体集積回路装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007310344A Division JP2008141204A (ja) 2007-11-30 2007-11-30 半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
JP2001291720A true JP2001291720A (ja) 2001-10-19
JP2001291720A5 JP2001291720A5 (https=) 2006-03-23

Family

ID=18617635

Family Applications (1)

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JP2000104015A Pending JP2001291720A (ja) 2000-04-05 2000-04-05 半導体集積回路装置および半導体集積回路装置の製造方法

Country Status (4)

Country Link
US (3) US6764950B2 (https=)
JP (1) JP2001291720A (https=)
KR (1) KR100698987B1 (https=)
TW (1) TW531892B (https=)

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JP2002246391A (ja) * 2001-02-21 2002-08-30 Nec Corp 半導体装置の製造方法
JP2004363516A (ja) * 2003-06-09 2004-12-24 Sony Corp 埋め込み配線の形成方法
US6858549B2 (en) 2001-12-27 2005-02-22 Matsushita Electric Industrial Co., Ltd. Method for forming wiring structure
US6881660B2 (en) 2001-12-27 2005-04-19 Matsushita Electric Industrial Co., Ltd. Method for forming wiring structure
US6919267B2 (en) 2001-12-27 2005-07-19 Matsushita Electric Industrial Co., Ltd. Method for forming wiring structure
US7323781B2 (en) 2003-03-25 2008-01-29 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
JP2008193120A (ja) * 2008-04-23 2008-08-21 Fujitsu Ltd 絶縁膜形成方法
JP2008545253A (ja) * 2005-05-10 2008-12-11 ラム リサーチ コーポレーション 通常の低k誘電性材料および/または多孔質の低k誘電性材料の存在下でのレジスト剥離のための方法
US7687917B2 (en) 2002-05-08 2010-03-30 Nec Electronics Corporation Single damascene structure semiconductor device having silicon-diffused metal wiring layer
US8012871B2 (en) 2002-10-17 2011-09-06 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
JP2012060149A (ja) * 2007-07-27 2012-03-22 Siltronic Ag 半導体材料から構成された基板を研磨する方法
JP2014112692A (ja) * 2013-12-27 2014-06-19 Jx Nippon Mining & Metals Corp 半導体用銅合金配線及びスパッタリングターゲット並びに半導体用銅合金配線の形成方法
JP2015128174A (ja) * 2002-05-17 2015-07-09 株式会社半導体エネルギー研究所 半導体装置
JP2016219620A (ja) * 2015-05-21 2016-12-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法およびそれに用いられるfoup
JP2017126802A (ja) * 2017-04-24 2017-07-20 ルネサスエレクトロニクス株式会社 半導体装置

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JP4554011B2 (ja) * 1999-08-10 2010-09-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
US7034402B1 (en) * 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
TW462085B (en) * 2000-10-26 2001-11-01 United Microelectronics Corp Planarization of organic silicon low dielectric constant material by chemical mechanical polishing
US6727158B2 (en) * 2001-11-08 2004-04-27 Micron Technology, Inc. Structure and method for forming a faceted opening and a layer filling therein
JP4340040B2 (ja) * 2002-03-28 2009-10-07 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP2003318140A (ja) * 2002-04-26 2003-11-07 Applied Materials Inc 研磨方法及び装置
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JP2005050903A (ja) * 2003-07-30 2005-02-24 Toshiba Corp 半導体装置およびその製造方法
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JP4703129B2 (ja) * 2004-05-06 2011-06-15 富士通セミコンダクター株式会社 半導体装置およびその製造方法、設計方法
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JP4956919B2 (ja) * 2005-06-08 2012-06-20 株式会社日立製作所 半導体装置およびその製造方法
KR101168728B1 (ko) * 2005-07-15 2012-07-26 삼성전자주식회사 배선 구조와 배선 형성 방법 및 박막 트랜지스터 기판과 그제조 방법
JP4964442B2 (ja) * 2005-08-10 2012-06-27 三菱電機株式会社 薄膜トランジスタおよびその製造方法
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US20080299780A1 (en) * 2007-06-01 2008-12-04 Uv Tech Systems, Inc. Method and apparatus for laser oxidation and reduction
US7758403B2 (en) * 2007-11-16 2010-07-20 Hitachi Global Storage Technologies Netherlands B.V. System, method and apparatus for lapping workpieces with soluble abrasives
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CN102203935A (zh) * 2008-10-27 2011-09-28 Nxp股份有限公司 生物兼容电极
US8513119B2 (en) 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
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US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
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