KR100487522B1 - 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법 - Google Patents

반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법 Download PDF

Info

Publication number
KR100487522B1
KR100487522B1 KR10-2002-0017757A KR20020017757A KR100487522B1 KR 100487522 B1 KR100487522 B1 KR 100487522B1 KR 20020017757 A KR20020017757 A KR 20020017757A KR 100487522 B1 KR100487522 B1 KR 100487522B1
Authority
KR
South Korea
Prior art keywords
signal
precharge
write
output
clock
Prior art date
Application number
KR10-2002-0017757A
Other languages
English (en)
Korean (ko)
Other versions
KR20030079016A (ko
Inventor
박상균
이호철
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR10-2002-0017757A priority Critical patent/KR100487522B1/ko
Priority to US10/268,732 priority patent/US7355912B2/en
Priority to CNB031044824A priority patent/CN100545943C/zh
Priority to DE10307244.6A priority patent/DE10307244B4/de
Priority to JP2003088701A priority patent/JP4637456B2/ja
Priority to TW092106938A priority patent/TWI284905B/zh
Publication of KR20030079016A publication Critical patent/KR20030079016A/ko
Application granted granted Critical
Publication of KR100487522B1 publication Critical patent/KR100487522B1/ko
Priority to US12/068,280 priority patent/US20080205175A1/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4094Bit-line management or control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/229Timing of a write operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
KR10-2002-0017757A 2002-04-01 2002-04-01 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법 KR100487522B1 (ko)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR10-2002-0017757A KR100487522B1 (ko) 2002-04-01 2002-04-01 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법
US10/268,732 US7355912B2 (en) 2002-04-01 2002-10-11 Auto-precharge control circuit in semiconductor memory and method thereof
CNB031044824A CN100545943C (zh) 2002-04-01 2003-02-17 半导体存储器中的自动预充电控制电路及其方法
DE10307244.6A DE10307244B4 (de) 2002-04-01 2003-02-17 Automatische Vorladesteuerungsschaltung und zugehöriges Vorladesteuerungsverfahren
JP2003088701A JP4637456B2 (ja) 2002-04-01 2003-03-27 自動プリチャージ制御回路及びその方法
TW092106938A TWI284905B (en) 2002-04-01 2003-03-27 Auto-precharge control circuit in semiconductor memory and method thereof
US12/068,280 US20080205175A1 (en) 2002-04-01 2008-02-05 Auto-precharge control circuit in semiconductor memory and method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2002-0017757A KR100487522B1 (ko) 2002-04-01 2002-04-01 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법

Publications (2)

Publication Number Publication Date
KR20030079016A KR20030079016A (ko) 2003-10-10
KR100487522B1 true KR100487522B1 (ko) 2005-05-03

Family

ID=28450114

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2002-0017757A KR100487522B1 (ko) 2002-04-01 2002-04-01 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법

Country Status (6)

Country Link
US (2) US7355912B2 (zh)
JP (1) JP4637456B2 (zh)
KR (1) KR100487522B1 (zh)
CN (1) CN100545943C (zh)
DE (1) DE10307244B4 (zh)
TW (1) TWI284905B (zh)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487522B1 (ko) * 2002-04-01 2005-05-03 삼성전자주식회사 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법
US7068564B2 (en) 2003-06-29 2006-06-27 International Business Machines Corporation Timer lockout circuit for synchronous applications
US7072234B1 (en) * 2005-02-02 2006-07-04 Infineon Technologies Ag Method and device for varying an active duty cycle of a wordline
KR100593149B1 (ko) 2005-05-12 2006-06-28 주식회사 하이닉스반도체 안정적인 오토 프리차지 신호를 발생하는 반도체 메모리장치의 클럭 동기형 오토 프리차지 제어 회로
DE102005031643B4 (de) * 2005-07-06 2007-06-14 Infineon Technologies Ag DRAM-Speicher
KR100699406B1 (ko) * 2006-01-23 2007-03-23 삼성전자주식회사 기입 회복 시간 제어회로 및 그 제어방법
KR100834395B1 (ko) * 2006-08-31 2008-06-04 주식회사 하이닉스반도체 반도체 메모리 장치
KR100875671B1 (ko) * 2006-09-27 2008-12-26 주식회사 하이닉스반도체 프리차지신호 생성장치를 구비하는 반도체메모리소자 및그의 구동방법
KR100892670B1 (ko) * 2007-09-05 2009-04-15 주식회사 하이닉스반도체 반도체 메모리 장치의 프리차지 제어 회로
KR100999876B1 (ko) 2008-12-05 2010-12-09 주식회사 하이닉스반도체 오토프리차지신호 생성회로
CN101986502A (zh) * 2009-07-28 2011-03-16 深圳富泰宏精密工业有限公司 手机电池充电电路
US8040747B2 (en) * 2009-12-30 2011-10-18 Hynix Semiconductor Inc. Circuit and method for controlling precharge in semiconductor memory apparatus
US9396771B2 (en) * 2012-05-07 2016-07-19 Samsung Electronics Co., Ltd. Memory device for performing multi-core access to bank groups
CN103514942B (zh) * 2012-06-15 2017-04-12 晶豪科技股份有限公司 用以控制随机存取存储器元件中的漏电流的电路和方法
KR20140028618A (ko) * 2012-08-29 2014-03-10 삼성전자주식회사 쓰기 페일을 줄이는 메모리 장치, 이를 포함하는 메모리 시스템 및 그 쓰기 방법
CN103700393B (zh) * 2012-09-28 2016-08-03 国际商业机器公司 用于dram的中间电路和方法
CN103824589B (zh) * 2014-03-03 2016-10-05 西安紫光国芯半导体有限公司 一种同步存储器
CN104216737A (zh) * 2014-08-15 2014-12-17 英业达科技有限公司 微控制器的重置系统和其重置方法
US20160071577A1 (en) * 2014-09-08 2016-03-10 Texas Instruments Incorporated Static random access memory with reduced write power
KR20170068719A (ko) * 2015-12-09 2017-06-20 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US10373665B2 (en) 2016-03-10 2019-08-06 Micron Technology, Inc. Parallel access techniques within memory sections through section independence
KR20180043924A (ko) * 2016-10-21 2018-05-02 에스케이하이닉스 주식회사 메모리 장치 및 메모리 컨트롤러를 포함하는 메모리 시스템
KR20200004002A (ko) * 2018-07-03 2020-01-13 삼성전자주식회사 메모리 장치 및 그것의 동작 방법
US11367476B2 (en) 2020-08-10 2022-06-21 Micron Technology, Inc. Bit line equalization driver circuits and related apparatuses, methods, and computing systems to avoid degradation of pull-down transistors
US11232830B1 (en) * 2020-12-11 2022-01-25 Micron Technology, Inc. Auto-precharge for a memory bank stack

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950027834A (ko) * 1994-03-03 1995-10-18 김광호 자동 프리차아지 기능을 가진 동기식 반도체 메모리장치
KR980004990A (ko) * 1996-06-27 1998-03-30 김주용 라이트 리커버리 보장 회로
KR19980029257A (ko) * 1996-10-25 1998-07-25 김광호 반도체 메모리 장치
KR20000047044A (ko) * 1998-12-31 2000-07-25 김영환 라이트 동작시 셀 데이터 보장장치
JP2000322886A (ja) * 1999-05-14 2000-11-24 Nec Corp 半導体記憶装置
KR20010061377A (ko) * 1999-12-28 2001-07-07 박종섭 자동 프리차지 제어장치

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (ko) 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
US5715407A (en) 1992-03-06 1998-02-03 Rambus, Inc. Process and apparatus for collision detection on a parallel bus by monitoring a first line of the bus during even bus cycles for indications of overlapping packets
USRE36532E (en) 1995-03-02 2000-01-25 Samsung Electronics Co., Ltd. Synchronous semiconductor memory device having an auto-precharge function
JP3843145B2 (ja) 1995-12-25 2006-11-08 株式会社ルネサステクノロジ 同期型半導体記憶装置
US5748551A (en) 1995-12-29 1998-05-05 Micron Technology, Inc. Memory device with multiple internal banks and staggered command execution
US5587961A (en) 1996-02-16 1996-12-24 Micron Technology, Inc. Synchronous memory allowing early read command in write to read transitions
US5825710A (en) * 1997-02-26 1998-10-20 Powerchip Semiconductor Corp. Synchronous semiconductor memory device
JPH10283779A (ja) * 1997-04-09 1998-10-23 Mitsubishi Electric Corp 同期型半導体記憶装置
US6242936B1 (en) 1998-08-11 2001-06-05 Texas Instruments Incorporated Circuit for driving conductive line and testing conductive line for current leakage
US6058069A (en) 1999-04-12 2000-05-02 Etron Technology, Inc. Protection circuit to ensure DRAM signal in write cycle
JP4748828B2 (ja) 1999-06-22 2011-08-17 ルネサスエレクトロニクス株式会社 半導体記憶装置
US6556482B2 (en) 1999-06-24 2003-04-29 Nec Electronics Corporation Semiconductor memory device
US6061285A (en) 1999-11-10 2000-05-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device capable of executing earlier command operation in test mode
JP2001167598A (ja) 1999-12-03 2001-06-22 Mitsubishi Electric Corp 半導体装置
KR100649826B1 (ko) * 1999-12-30 2006-11-24 주식회사 하이닉스반도체 반도체 메모리 소자의 오토 프리차지장치
KR100326085B1 (ko) 2000-02-24 2002-03-07 윤종용 반도체 메모리 장치의 자동 프리차지 제어신호 발생회로및 자동 프리차지 제어방법
JP2002015570A (ja) * 2000-06-28 2002-01-18 Toshiba Corp 半導体メモリ
JP2002025288A (ja) * 2000-06-30 2002-01-25 Hitachi Ltd 半導体集積回路
US6275437B1 (en) 2000-06-30 2001-08-14 Samsung Electronics Co., Ltd. Refresh-type memory with zero write recovery time and no maximum cycle time
DE10053425C2 (de) * 2000-10-27 2003-02-13 Infineon Technologies Ag Integrierter Speicher mit Zeilenzugriffsteuerung zur Aktivierung und Deaktivierung von Zeilenleitungen
US6434082B1 (en) * 2001-03-13 2002-08-13 International Business Machines Corporation Clocked memory device that includes a programming mechanism for setting write recovery time as a function of the input clock
US6661721B2 (en) * 2001-12-13 2003-12-09 Infineon Technologies Ag Systems and methods for executing precharge commands using posted precharge in integrated circuit memory devices with memory banks each including local precharge control circuits
KR100487522B1 (ko) * 2002-04-01 2005-05-03 삼성전자주식회사 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950027834A (ko) * 1994-03-03 1995-10-18 김광호 자동 프리차아지 기능을 가진 동기식 반도체 메모리장치
KR980004990A (ko) * 1996-06-27 1998-03-30 김주용 라이트 리커버리 보장 회로
KR100225947B1 (ko) * 1996-06-27 1999-10-15 김영환 라이트 리커버리 보장 회로
KR19980029257A (ko) * 1996-10-25 1998-07-25 김광호 반도체 메모리 장치
KR20000047044A (ko) * 1998-12-31 2000-07-25 김영환 라이트 동작시 셀 데이터 보장장치
JP2000322886A (ja) * 1999-05-14 2000-11-24 Nec Corp 半導体記憶装置
KR20010061377A (ko) * 1999-12-28 2001-07-07 박종섭 자동 프리차지 제어장치

Also Published As

Publication number Publication date
CN100545943C (zh) 2009-09-30
US20080205175A1 (en) 2008-08-28
JP2003297084A (ja) 2003-10-17
KR20030079016A (ko) 2003-10-10
DE10307244A1 (de) 2004-01-08
US20030185075A1 (en) 2003-10-02
DE10307244B4 (de) 2015-08-13
TW200305168A (en) 2003-10-16
US7355912B2 (en) 2008-04-08
CN1448953A (zh) 2003-10-15
TWI284905B (en) 2007-08-01
JP4637456B2 (ja) 2011-02-23

Similar Documents

Publication Publication Date Title
KR100487522B1 (ko) 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법
US5471430A (en) Test circuit for refresh counter of clock synchronous type semiconductor memory device
US5818793A (en) Clock-synchronous semiconductor memory device
KR100719377B1 (ko) 데이터 패턴을 읽는 반도체 메모리 장치
US6260128B1 (en) Semiconductor memory device which operates in synchronism with a clock signal
US11276442B2 (en) Apparatuses and methods for clock leveling in semiconductor memories
JP2009528635A (ja) 集積回路の動作パラメータを調整するための装置及び方法
JP2012164416A (ja) 行および列へのアクセス動作を同期させるための方法および装置
US7054204B2 (en) Semiconductor device and method for controlling the same
KR100430658B1 (ko) Cas 레이턴시가 1 동작과 cas 레이턴시가 2 이상인동작을 양립시키는 것이 가능한 반도체 기억 장치
US6163498A (en) Methods and systems for column line selection in a memory device
US5959936A (en) Column select line enable circuit for a semiconductor memory device
US6310821B1 (en) Clock-synchronous semiconductor memory device and access method thereof
KR100419270B1 (ko) 반도체 메모리
US7440312B2 (en) Memory write timing system
US7339839B2 (en) Triggering of IO equilibrating ending signal with firing of column access signal
KR100190099B1 (ko) 데이터 라인 등화 장치
KR20000073441A (ko) 글로벌 데이터 버스 래치
KR19980069481A (ko) 고속 메모리 장치용 섹션 워드라인 구동 펄스생성 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment
FPAY Annual fee payment
FPAY Annual fee payment

Payment date: 20190329

Year of fee payment: 15