KR100487522B1 - 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법 - Google Patents

반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법 Download PDF

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Publication number
KR100487522B1
KR100487522B1 KR10-2002-0017757A KR20020017757A KR100487522B1 KR 100487522 B1 KR100487522 B1 KR 100487522B1 KR 20020017757 A KR20020017757 A KR 20020017757A KR 100487522 B1 KR100487522 B1 KR 100487522B1
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KR
South Korea
Prior art keywords
signal
precharge
write
output
clock
Prior art date
Application number
KR10-2002-0017757A
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English (en)
Korean (ko)
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KR20030079016A (ko
Inventor
박상균
이호철
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR10-2002-0017757A priority Critical patent/KR100487522B1/ko
Priority to US10/268,732 priority patent/US7355912B2/en
Priority to CNB031044824A priority patent/CN100545943C/zh
Priority to DE10307244.6A priority patent/DE10307244B4/de
Priority to TW092106938A priority patent/TWI284905B/zh
Priority to JP2003088701A priority patent/JP4637456B2/ja
Publication of KR20030079016A publication Critical patent/KR20030079016A/ko
Application granted granted Critical
Publication of KR100487522B1 publication Critical patent/KR100487522B1/ko
Priority to US12/068,280 priority patent/US20080205175A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
KR10-2002-0017757A 2002-04-01 2002-04-01 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법 KR100487522B1 (ko)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR10-2002-0017757A KR100487522B1 (ko) 2002-04-01 2002-04-01 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법
US10/268,732 US7355912B2 (en) 2002-04-01 2002-10-11 Auto-precharge control circuit in semiconductor memory and method thereof
CNB031044824A CN100545943C (zh) 2002-04-01 2003-02-17 半导体存储器中的自动预充电控制电路及其方法
DE10307244.6A DE10307244B4 (de) 2002-04-01 2003-02-17 Automatische Vorladesteuerungsschaltung und zugehöriges Vorladesteuerungsverfahren
TW092106938A TWI284905B (en) 2002-04-01 2003-03-27 Auto-precharge control circuit in semiconductor memory and method thereof
JP2003088701A JP4637456B2 (ja) 2002-04-01 2003-03-27 自動プリチャージ制御回路及びその方法
US12/068,280 US20080205175A1 (en) 2002-04-01 2008-02-05 Auto-precharge control circuit in semiconductor memory and method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2002-0017757A KR100487522B1 (ko) 2002-04-01 2002-04-01 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법

Publications (2)

Publication Number Publication Date
KR20030079016A KR20030079016A (ko) 2003-10-10
KR100487522B1 true KR100487522B1 (ko) 2005-05-03

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2002-0017757A KR100487522B1 (ko) 2002-04-01 2002-04-01 반도체 메모리 장치의 동작 주파수에 따라 기입 회복시간을 제어하는 프리차아지 제어 회로 및 기입 회복 시간제어 방법

Country Status (6)

Country Link
US (2) US7355912B2 (zh)
JP (1) JP4637456B2 (zh)
KR (1) KR100487522B1 (zh)
CN (1) CN100545943C (zh)
DE (1) DE10307244B4 (zh)
TW (1) TWI284905B (zh)

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KR100999876B1 (ko) * 2008-12-05 2010-12-09 주식회사 하이닉스반도체 오토프리차지신호 생성회로
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US9396771B2 (en) * 2012-05-07 2016-07-19 Samsung Electronics Co., Ltd. Memory device for performing multi-core access to bank groups
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KR20140028618A (ko) * 2012-08-29 2014-03-10 삼성전자주식회사 쓰기 페일을 줄이는 메모리 장치, 이를 포함하는 메모리 시스템 및 그 쓰기 방법
CN103700393B (zh) * 2012-09-28 2016-08-03 国际商业机器公司 用于dram的中间电路和方法
CN103824589B (zh) * 2014-03-03 2016-10-05 西安紫光国芯半导体有限公司 一种同步存储器
CN104216737A (zh) * 2014-08-15 2014-12-17 英业达科技有限公司 微控制器的重置系统和其重置方法
US20160071577A1 (en) * 2014-09-08 2016-03-10 Texas Instruments Incorporated Static random access memory with reduced write power
KR20170068719A (ko) * 2015-12-09 2017-06-20 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US10373665B2 (en) 2016-03-10 2019-08-06 Micron Technology, Inc. Parallel access techniques within memory sections through section independence
KR20180043924A (ko) * 2016-10-21 2018-05-02 에스케이하이닉스 주식회사 메모리 장치 및 메모리 컨트롤러를 포함하는 메모리 시스템
KR20200004002A (ko) * 2018-07-03 2020-01-13 삼성전자주식회사 메모리 장치 및 그것의 동작 방법
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Also Published As

Publication number Publication date
KR20030079016A (ko) 2003-10-10
CN100545943C (zh) 2009-09-30
TW200305168A (en) 2003-10-16
US20030185075A1 (en) 2003-10-02
JP2003297084A (ja) 2003-10-17
US20080205175A1 (en) 2008-08-28
DE10307244A1 (de) 2004-01-08
CN1448953A (zh) 2003-10-15
JP4637456B2 (ja) 2011-02-23
TWI284905B (en) 2007-08-01
DE10307244B4 (de) 2015-08-13
US7355912B2 (en) 2008-04-08

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