KR100446402B1 - 불휘발성 반도체 기억 장치의 프로그램 방법 - Google Patents

불휘발성 반도체 기억 장치의 프로그램 방법 Download PDF

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Publication number
KR100446402B1
KR100446402B1 KR10-2002-0024959A KR20020024959A KR100446402B1 KR 100446402 B1 KR100446402 B1 KR 100446402B1 KR 20020024959 A KR20020024959 A KR 20020024959A KR 100446402 B1 KR100446402 B1 KR 100446402B1
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South Korea
Prior art keywords
voltage
memory cell
twin
bit line
control gate
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Expired - Fee Related
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KR10-2002-0024959A
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English (en)
Korean (ko)
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KR20030009120A (ko
Inventor
가나이마사히로
가메이데루히꼬
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세이코 엡슨 가부시키가이샤
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
KR10-2002-0024959A 2001-05-08 2002-05-07 불휘발성 반도체 기억 장치의 프로그램 방법 Expired - Fee Related KR100446402B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2001-00137165 2001-05-08
JP2001137165A JP4715024B2 (ja) 2001-05-08 2001-05-08 不揮発性半導体記憶装置のプログラム方法

Publications (2)

Publication Number Publication Date
KR20030009120A KR20030009120A (ko) 2003-01-29
KR100446402B1 true KR100446402B1 (ko) 2004-09-01

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KR10-2002-0024959A Expired - Fee Related KR100446402B1 (ko) 2001-05-08 2002-05-07 불휘발성 반도체 기억 장치의 프로그램 방법

Country Status (7)

Country Link
US (1) US6587381B2 (https=)
EP (1) EP1256960B1 (https=)
JP (1) JP4715024B2 (https=)
KR (1) KR100446402B1 (https=)
CN (1) CN1228786C (https=)
AT (1) ATE267447T1 (https=)
DE (1) DE60200498T2 (https=)

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JP3716914B2 (ja) 2001-05-31 2005-11-16 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP3659205B2 (ja) * 2001-08-30 2005-06-15 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその駆動方法
JP3843869B2 (ja) * 2002-03-15 2006-11-08 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP3821032B2 (ja) * 2002-03-20 2006-09-13 セイコーエプソン株式会社 ファイルストレージ型不揮発性半導体記憶装置
JP3815381B2 (ja) * 2002-06-06 2006-08-30 セイコーエプソン株式会社 不揮発性半導体記憶装置およびその駆動方法
JP3867624B2 (ja) * 2002-06-06 2007-01-10 セイコーエプソン株式会社 不揮発性半導体記憶装置およびその駆動方法
JP3871049B2 (ja) * 2002-12-10 2007-01-24 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP2004199738A (ja) * 2002-12-16 2004-07-15 Seiko Epson Corp 不揮発性記憶装置
JP3985689B2 (ja) * 2003-02-21 2007-10-03 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP3873908B2 (ja) 2003-02-28 2007-01-31 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその製造方法
JP3786095B2 (ja) * 2003-02-28 2006-06-14 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP2004265508A (ja) * 2003-02-28 2004-09-24 Seiko Epson Corp 不揮発性半導体記憶装置
JP3767588B2 (ja) * 2003-08-29 2006-04-19 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその制御方法
JP4196191B2 (ja) * 2003-09-09 2008-12-17 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその制御方法
US7120051B2 (en) * 2004-12-14 2006-10-10 Sandisk Corporation Pipelined programming of non-volatile memories using early data
US7307882B2 (en) * 2005-06-29 2007-12-11 Macronix International Co., Ltd. Non-volatile memory
US7233528B2 (en) * 2005-07-25 2007-06-19 Atmel Corporation Reduction of programming time in electrically programmable devices
TWI265626B (en) * 2005-08-19 2006-11-01 Powerchip Semiconductor Corp Non-volatile memory and manufacturing method and operating method thereof
US7366013B2 (en) * 2005-12-09 2008-04-29 Micron Technology, Inc. Single level cell programming in a multiple level cell non-volatile memory device
US7349254B2 (en) * 2006-05-31 2008-03-25 Qimonda Flash Gmbh & Co. Kg Charge-trapping memory device and methods for its manufacturing and operation
KR101320519B1 (ko) 2006-07-27 2013-10-23 삼성전자주식회사 패스 트랜지스터를 갖는 비휘발성 메모리 소자 및 그 동작방법
CN101373636B (zh) * 2007-08-20 2010-12-22 中芯国际集成电路制造(上海)有限公司 防止存储器阵列产生位线干扰的方法
US7672163B2 (en) 2007-09-14 2010-03-02 Sandisk Corporation Control gate line architecture
JP5266085B2 (ja) * 2009-02-17 2013-08-21 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
KR101849176B1 (ko) 2012-01-06 2018-04-17 삼성전자주식회사 2-트랜지스터 플래시 메모리 및 2-트랜지스터 플래시 메모리의 프로그램 방법
US20170006161A9 (en) * 2013-03-15 2017-01-05 Genesys Telecommunications Laboratories, Inc. Intelligent automated agent for a contact center
KR102083826B1 (ko) * 2013-05-13 2020-03-03 주식회사 실리콘웍스 표시 장치의 가비지 프로세싱 회로
US10074438B2 (en) 2016-06-10 2018-09-11 Cypress Semiconductor Corporation Methods and devices for reducing program disturb in non-volatile memory cell arrays
US9997253B1 (en) 2016-12-08 2018-06-12 Cypress Semiconductor Corporation Non-volatile memory array with memory gate line and source line scrambling
US11309324B2 (en) * 2020-07-28 2022-04-19 Globalfoundries Singapore Pte. Ltd. Compact memory cell with a shared conductive word line and methods of making such a memory cell
US11437392B2 (en) * 2020-07-28 2022-09-06 Globalfoundries Singapore Pte. Ltd. Compact memory cell with a shared conductive select gate and methods of making such a memory cell

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US5969383A (en) * 1997-06-16 1999-10-19 Motorola, Inc. Split-gate memory device and method for accessing the same
JP2001156275A (ja) * 1999-09-17 2001-06-08 Hitachi Ltd 半導体集積回路
US6255166B1 (en) * 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
US6344993B1 (en) * 1999-06-30 2002-02-05 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
US6366500B1 (en) * 1999-05-17 2002-04-02 Halo Lsi Device & Design Technology, Inc. Process for making and programming and operating a dual-bit multi-level ballistic flash memory

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US6366500B1 (en) * 1999-05-17 2002-04-02 Halo Lsi Device & Design Technology, Inc. Process for making and programming and operating a dual-bit multi-level ballistic flash memory
US6344993B1 (en) * 1999-06-30 2002-02-05 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
US6255166B1 (en) * 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
JP2001156275A (ja) * 1999-09-17 2001-06-08 Hitachi Ltd 半導体集積回路

Also Published As

Publication number Publication date
US6587381B2 (en) 2003-07-01
DE60200498D1 (de) 2004-06-24
DE60200498T2 (de) 2005-06-02
ATE267447T1 (de) 2004-06-15
CN1228786C (zh) 2005-11-23
EP1256960B1 (en) 2004-05-19
KR20030009120A (ko) 2003-01-29
US20030002344A1 (en) 2003-01-02
CN1399280A (zh) 2003-02-26
EP1256960A1 (en) 2002-11-13
JP2002334587A (ja) 2002-11-22
JP4715024B2 (ja) 2011-07-06

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