KR100399012B1 - 반도체장치 및 그것의 제조방법 - Google Patents

반도체장치 및 그것의 제조방법 Download PDF

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Publication number
KR100399012B1
KR100399012B1 KR10-2001-0031209A KR20010031209A KR100399012B1 KR 100399012 B1 KR100399012 B1 KR 100399012B1 KR 20010031209 A KR20010031209 A KR 20010031209A KR 100399012 B1 KR100399012 B1 KR 100399012B1
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South Korea
Prior art keywords
semiconductor device
conductive
insulating substrate
electrode
substrate
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KR10-2001-0031209A
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English (en)
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KR20010110198A (ko
Inventor
후쿠이즈미아키라
Original Assignee
엔이씨 일렉트로닉스 코포레이션
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Publication of KR20010110198A publication Critical patent/KR20010110198A/ko
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Publication of KR100399012B1 publication Critical patent/KR100399012B1/ko

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Abstract

반도체장치에서, 절연성 기판은 복수의 스루홀들을 갖는다. 복수의 도전포스트들(conductive posts)은 스루홀들에 매립된다. 도전포스트들은 적어도 하나의 제1도전포스트와 한 쌍의 제2도전포스트로 분류된다. 반도체소자는 표면측에 적어도 하나의 표면전극을 갖는다. 표면전극은 페이스다운법(face-down method)에 의해 제1도전포스트에 접속된다. 금속블록은 단면형상이 사각아치상(square-arch shape)으로 형성되고, 천장부(ceiling portion) 및 양 단부들을 갖는다. 반도체소자의 이면은 천장부에 고착되고, 양 말단부들은 제2도전포스트들에 고착된다. 밀봉수지(sealing-resin)는 반도체소자를 밀봉한다.

Description

반도체장치 및 그것의 제조방법{Semiconductor device and method of manufacturing the same}
본 발명은 대체로 반도체장치 및 그것의 제조방법에 관한 것이다. 더욱 상세하게, 본 발명은 파워장치(power device)의 장착구조에 관한 것이다.
종래 파워장치의 패키지에서는, 파워장치와 같은 반도체장치가 일반적으로 리드프레임을 이용하여 탑재되고, 공지의 트랜스퍼몰드법(transfer molding method)에 의해 수지밀봉되었다.
도 1a 및 도 1b를 참조하면서, 일본 특허출원공개공보(JP-A) No.평6-37122에 개시된 파워장치의 장착방법에 관하여 설명한다.
반도체장치를 조립하기 전에, 헤더(die pad)(21) 및 댐(dam-tie bar)(26)에 연결된 리드(23)를 갖는 리드프레임이 금속판에 구멍을 뚫어(이하, 펀칭) 형성된다.
이 구조로, 홈(28)이 헤더(21) 상면의 펠릿부착부의 펠릿외주부 바로 아래에 형성된다.
도 1a에 도시된 바와 같이, 펠릿(22)은 땜납(25)에 의해 헤더 위에 부착된다. 또, 전선(24)은 펠릿(22)상의 전극과 리드(23) 사이에 접속된다.
다음, 펠릿(22)이 탑재된 리드프레임이 밀봉용금형에 배치되고,밀봉수지(27)가 헤더(21) 이면을 노출시키고 상면측을 덮도록 수지밀봉된다. 수지밀봉후, 각 리드(23)는 댐(26)의 절단에 의해 분리된다.
상술한 장착방법에서, 장치들의 종류가 서로 다른 경우에는 리드프레임들이 다른 형상으로 설계된다. 결과적으로, 제조설비들은 각 종류들마다 전용화되고 생산라인은 유동적이지 않다.
또, 금속리드프레임을 형성하기 위한 특정 리드프레임금형은 각 종류마다 제조되어야 한다. 이런 사실들은 비용을 상승시킨다. 더욱이, 리드프레임으로부터 만들어진 장치들의 수가 감소되어 생산효율을 저하시킨다.
결과적으로, 종래방법에서는 파워장치용 패키지를 저렴하게 제공하는 것이 어렵다.
그러므로, 본 발명의 목적은 소형이고 저렴한 장착구조를 갖는 반도체장치를 제공하는 것이다.
도 1a는 종래예를 나타내는 사시도이고;
도 1b는 종래예를 나타내는 단면도이고;
도 2a는 제1실시예에 따른 반도체장치를 나타내는 평면도이고;
도 2b는 제1실시예에 따른 반도체장치를 나타내는 단면도이고;
도 2c는 제1실시예에 따른 반도체장치를 나타내는 저면도이고;
도 3a - 도 3c는 제1실시예에 따른 반도체장치의 제조방법을 나타내는 단면도들이고;
도 4a - 도 4c는 제1실시예에 따른 반도체장치의 제조방법을 나타내는 단면도들이고;
도 5는 제1실시예에 따른 제조단계를 나타내는 평면도이고;
도 6a는 제2실시예에 따른 반도체장치를 나타내는 평면도이고;
도 6b는 제2실시예에 따른 반도체장치를 나타내는 단면도이고;
도 6c는 제2실시예에 따른 반도체장치를 나타내는 저면도이고;
도 7a - 도 7c는 제2실시예에 따른 반도체장치의 제조방법을 나타내는 단면도들이고;
도 8a - 도 8c는 제2실시예에 따른 반도체장치의 제조방법을 나타내는 단면도들이다.
본 발명에 따른 반도체장치에서, 절연성기판은 복수의 스루홀들을 갖는다.
복수의 도전포스트들(conductive posts)은 스루홀들에 매립된다. 이 경우, 도전포스트들은 적어도 하나의 제1도전포스트와 한 쌍의 제2도전포스트로 분류된다.
또, 반도체소자는 표면측에 적어도 하나의 표면전극을 갖는다. 여기서, 표면전극은 페이스다운법(face-down method)에 의해 제1도전포스트에 접속된다.
더욱이, 금속블록은 단면형상이 사각아치상(square-arch shape)으로 형성되고, 천장부(ceiling portion) 및 양 단부들을 갖는다. 이 경우, 반도체소자의 이면은 천장부에 고정되고, 양 단부들은 제2도전포스트들에 고정된다.
게다가, 밀봉수지(sealing-resin)가 반도체소자를 밀봉한다.
이 구조로, 반도체소자는 이면측에 이면전극을 갖는다. 이면전극은 금속블록을 거쳐 제2도전포스트들에 접속된다.
이 경우, 각각의 제1 및 제2 도전포스트들은 Cu페이스트를 이용하여 형성될 수 있다.
또, 제1기판전극은 제1도전포스트 상에 형성된다. 기판전극은 제1기판전극을 거쳐 제1도전포스트에 접속된다.
여기서, 제1기판전극은 Ag페이스트를 이용하여 형성될 수 있다.
더욱이, 제2기판전극은 제2도전포스트 상에 형성된다. 금속블록은 제2기판전극을 거쳐 제2도전포스트에 접속된다.
여기서, 제2기판전극은 Ag페이스트를 이용하여 형성될 수 있다.
이 경우, 표면전극은 범프전극을 포함한다. 절연성기판은 수지기판을 포함한다.
특히, 수지적층판과 같은 절연성 기판이 이용된다. 또, 반도체장치의 이면전극은, 통상 히트싱크로서 작용하는 금속블록을 거쳐 절연성 기판의 측면으로 인출된다. 반도체기판은 완전히 수지밀봉되고, 다이서(dicer)를 이용하여 개개의 부분들로 절단된다.
결과적으로, 파워장치는 설비의 종류에 상관없이 높은 유연성을 갖는 생산라인에서 제조될 수 있다.
또, 높은 방열성을 갖는 소형 파워장치가 장착구조로 실현될 수 있다.
더욱 상세하게는, 펠릿은 페이스다운방법을 사용하여 도전포스트를 갖는 절연성기판상에 배치된다. 또, 금속블록은, 펠릿의 이면전극이 도전포스트로 인출되도록 그 위를 덮는다.
복수의 펠릿들이 완전히 수지밀봉된 후, 펠릿은 다이서를 이용해서 개개의 부분으로 절단된다.
결과적으로, 고가의 제조설비가 불필요하다. 또, 높은 유연성을 갖는 생산라인에서 반도체를 제조할 수 있고 반도체장치를 효과적으로 제조할 수 있다.
더욱이, 리드프레임을 이용하지 않고 높은 방열성을 갖는 소형패키지를 저렴하게 제공할 수 있다.
실시예
제1실시예
도 2a 내지 도 2c를 참조하면서, 이하 제1실시예에 대해 설명한다.
도 2a 내지 도 2c에 도시된 바와 같이, 스루홀들(2)은 유리에폭시수지 적층판으로 구성된 수지기판(1)에 개구되어, 수지기판(1)을 관통한다. 이 경우, 도전포스트들(3)이 스루홀(2)에 매립된다. 여기서, 각각의 도전포스트들(3)은 Cu페이스트에 의해 형성된다.
기판전극들(4)은 Ag페이스트를 이용하여 도전포스트(3)의 상면 및 하면 상에형성된다.
범프전극(6)을 갖는 펠릿(5)은 공지의 페이스다운법에 의해 수지기판(1)의 표면측상에 배치된다. 또, 금속블록(7)은 펠릿(5)을 덮는다.
이런 구조로, 금속블록(7)과 기판전극(4), 및 금속블록(7)과 펠릿(5)의 이면전극은 각각 땜납(8)을 거쳐 접속된다.
특히, 펠릿(5)의 주전극으로서 작용하는 이면전극은 금속블록(7) 및 도전포스트(3)를 거쳐 수지기판(1)의 이면측에서 기판전극(4)에 접속된다. 또, 수지기판(1)은 몰드수지로서 작용하는 밀봉수지(10)로 밀봉된다.
이런 반도체장치에서, 펠릿(5)에서 발생된 열은, 펠릿표면의 범프전극(6)을 거쳐 도전포스트(3)에 도달하는 경로 및 금속블록(7)을 거쳐 펠릿이면에서 금속포스트(3)에 도달하는 또 다른 경로를 통해 효과적으로 방산된다.
더욱 상세하게는, 펠릿의 표면측이 밀봉수지로 덮여져 있기 때문에, 도 1에 도시된 종래구조에 의해서는 방열(heat-dissipation)이 효과적으로 행해질 수 없다. 대조적으로, 본 발명에 의하면 방열이 펠릿(5)의 표면측에서 효과적으로 행해질 수 있다.
도 3a 내지 도 4c를 참조하면서, 본 발명에 따른 제1실시예의 제조방법에 대해 설명한다.
우선, 도 3a에 도시된 바와 같이 스루홀들(2)이 펀칭에 의해 수지적층판으로 구성되는 수지기판(1)에서 개구된다.
또, Cu페이스트가 공지의 닥터브레이드법(doctor blade method)을 이용해서스루홀(2) 안으로 도포되고 소성되어 도전포스트(3)를 형성한다.
이 경우, 수지기판(1)은 복수의 펠릿들이 도 3a에서 좌우방향으로 탑재될 수 있는 길이를 갖는다. 또, 도 5에 도시된 바와 같이 수지기판(1)은, 도 3a의 깊이방향으로 복수의 펠릿들이 또한 배치될 수 있는 길이를 갖는다.
다음, 도 3b에 도시된 바와 같이, Ag페이스트가 공지의 스크린인쇄법을 이용해서 Cu포스트(3)의 상면 및 하면 상에 도포되고 소성 또는 경화되어 기판전극(4)을 형성한다.
다음, 상면에 범프전극(6)을 갖고 이면측에 이면전극을 갖는 펠릿(5)은 뒤집혀진다. 도 3c에 도시된 바와 같이, 뒤집혀진 펠릿(5)은 (페이스다운)기판(1)상에 배치되고 가열/가압되어 기판전극(4)과 범프전극(6)이 접속된다.
이어서, 땜납페이스트는 펠릿(5) 위로 그리고 금속블록(7)의 양측 하면에 도포된다. 그 후에, 금속블록(7)은 펠릿(5) 상에 배치된다. 또, 도 4a에 도시된 바와 같이, 금속블록(7)은 리플로챔버(reflow chamber, 미도시)를 통과해서 땜납(8)을 이용해서 기판전극(4) 및 펠릿(5)에 고착된다.
다음, 펠릿(5) 및 금속블록(7)이 탑재된 수지기판(1)은 밀봉용금형(9) 안에 배치된다. 금형(9)이 죔쇠로 채워진 후, 용융에폭시계 수지에 도 4b의 전방으로부터 힘이 가해지고, 소정의 시간동안 경화되고 밀봉수지(10)를 이용해서 수지밀봉된다.
도 5에 도시된 바와 같이, 도 4b에 도시된 상태에서 일괄밀봉제품(batch sealing product)이 밀봉용금형(9)으로부터 꺼내진다.
이어서, 밀봉제품은 다이서(다이싱톱)의 칼날(12)에 의해 절단되어 각각의 패키지로 분리된다. 그것에 의해, 도 2에 도시된 반도체장치가 얻어진다.
실시예 2
다음, 본 발명에 따른 제2실시예에 대해서 설명한다.
도 2에 도시된 제1실시예와 도 6에 도시된 제2실시예 사이의 차이들은 다음과 같이 설명된다.
첫째, 제2실시예에서는 밀봉수지(10)가 금속블록(7)의 내부에만 형성되고, 금속블록(7)의 외측면에는 형성되지 않는다.
둘째, 땜납들(14)이 수지기판(1)의 이면측에 기판전극(4) 대신 형성된다. 제2실시예에서, 전극이 표면측에만 형성된 펠릿이 이용된다.
도 7a 내지 도 8c를 참조하면서, 이하 본 발명에 따른 제2실시예의 제조방법에 대해서 설명한다.
도 7a에 도시된 바와 같이, 스루홀들(2)이 수지기판(1)에서 개구되고, 도전포스트들(3)이 스루홀들(2)을 통해 형성된다. 이 단계는 제1실시예와 본질적으로 동일하다.
다음, 도 7b에 도시된 바와 같이 Ag페이스트가 스크린인쇄법을 이용해서 도포되어 Cu포스트(3)의 상면상에 기판전극(4)을 형성한다.
다음, 표면상에 범프전극(6)을 갖으며 도전성 접착제층(13)으로 작용하는 Ag페이스트로 도포되는 펠릿(5)이 뒤집혀진다. 뒤집혀진 펠릿(5)은 기판(1)상에 배치되고, 그 위에 금속블록(7)이 덮혀진다.
연속적으로, 펠릿(5)은 Ag페이스트로 소성되고, 수지기판(1)에 고착된다. 또, 금속블록(7)은 수지기판(1) 및 펠릿(5)에 고착된다. 여기서, 도전성 접착제층(13)으로 작용하는 Ag페이스트는 금속블록(7)의 측면에서 도포될 수 있다는 것이 주목된다.
다음, 도 8a에 도시된 바와 같이 펠릿(5) 및 금속블록(7)이 탑재된 수지기판(1)은 측면으로 전복된다. 또, 밀봉수지는 수지기판(1) 및 금속블록(7)에 의해 둘러싸인 공간 내부로 공급되고 경화되어 밀봉수지(10)를 형성한다.
다음, 도 8b에 도시된 바와 같이 땜납들(14)은 도전성 포스트(3)의 하면에 고착된다.
그 후에, 수지기판(1) 및 금속블록(7)은 다이서의 칼날(12)에 의해 절단되고, 각각의 패키지로 분리된다. 따라서, 도 6에 도시된 반도체기판이 얻어진다.
본 발명은 지금까지 그것의 몇몇의 실시예와 결합되어 설명되었지만, 당업자들이 본 발명을 여러가지 다른 방식들로 실시하는 것은 용이하게 가능할 수 있다.
예를 들어, Cu페이스트 또는 Ag페이스트 대신에 다른 재료가 사용될 수 있다.
또, 수지밀봉이 반드시 도 5에 도시된 상태에서 행해질 필요는 없다. 택일적으로, 수지밀봉이 도 5의 횡방향으로 각 선(열) 마다 또는 복수의 선(열)으로 분리된 후 행해질 수도 있다.
더욱이, 금속블록이 기판 및 펠릿에 동시에 고착되는 경우, 땜납페이스트가 고착부재가 되는 도전성 재료로서 사용될 수 있다.
게다가, 수지기판의 스루홀은 펀칭 대신에 천공(drilling)을 이용해서 개구될 수 있다.
상술한 바와 같이, 본 발명의 반도체장치는 도전포스트를 갖는 절연성 기판상에 페이스다운방법을 사용하여 펠릿을 탑재하고, 그 위에 펠릿의 이면전극을 도전포스트로 인출할 수 있는 금속블록을 덮어, 복수의 펠릿들을 일괄수지밀봉한 후, 다이서를 이용해서 개개의 부분으로 절단한다. 따라서, 고가의 제조설비가 불필요하고, 높은 유연성을 갖는 생산라인에서 반도체를 제조할 수 있고 반도체장치를 효과적으로 제조할 수 있다. 그리고, 리드프레임을 이용하지 않고 높은 방열성을 갖는 소형패키지를 저렴하게 공급할 수 있다.

Claims (21)

  1. 복수의 스루홀들을 갖는 절연성 기판;
    스루홀들에 매립되며, 적어도 하나의 제1도전포스트 및 한 쌍의 제2도전포스트들로 분류되는 복수의 도전포스트들;
    표면측에 페이스다운법에 의해 제1도전포스트에 접속되는 적어도 하나의 표면전극을 갖는 반도체소자;
    단면형상이 사각아치상으로 형성되며, 천장부 및 양 단부들을 갖고, 반도체소자이면이 천장부에 고착되고, 양 단부들이 제2도전포스트들에 고착되는 금속블록; 및
    반도체소자를 밀봉하는 밀봉수지를 포함하는 반도체장치.
  2. 제1항에 있어서, 반도체소자는 이면측에 이면전극을 갖고,
    이면전극은 금속블록을 거쳐 제2도전포스트들에 접속되는 반도체장치.
  3. 제1항에 있어서, 각각의 제1 및 제2 도전포스트들은 Cu페이스트를 이용해서 형성되는 반도체장치.
  4. 제1항에 있어서, 제1기판전극이 제1도전포스트상에 형성되고,
    표면전극은 제1기판전극을 거쳐 제1도전포스트에 접속되는 반도체장치.
  5. 제4항에 있어서, 제1기판전극은 Ag페이스트를 이용해서 형성되는 반도체장치.
  6. 제1항에 있어서, 제2기판전극은 제2도전포스트상에 형성되고,
    금속블록은 제2기판전극을 거쳐 제2도전포스트에 접속되는 반도체장치.
  7. 제6항에 있어서, 제2기판전극은 Ag페이스트를 이용해서 형성되는 반도체장치.
  8. 제1항에 있어서, 표면전극은 범프전극을 포함하는 반도체장치.
  9. 제1항에 있어서, 절연성 기판은 수지기판을 포함하는 반도체장치.
  10. 절연성기판을 갖는 반도체장치의 제조방법에 있어서,
    절연성 기판에 복수의 스루홀들을 개구하는 단계;
    적어도 하나의 제1도전포스트 및 한 쌍의 제2도전포스트들로 분류되는 복수의 도전포스트들을 스루홀들에 매립하는 단계;
    페이스다운법에 의해 제1도전포스트에 표면전극을 접속하여 절연성 기판상의 표면측에 적어도 하나의 표면전극을 갖는 반도체소자를 탑재하는 단계;
    단면형상이 사각아치상으로 형성되며, 천장부 및 양 단부들을 갖는 금속블록을, 반도체소자 이면을 천장부에 고착시키고, 양 단부들을 제2도전포스트들에 고착시켜서 절연성 기판상에 탑재하는 단계; 및
    반도체소자를 수지밀봉하는 단계를 포함하는 반도체장치의 제조방법.
  11. 제10항에 있어서,
    제1 및 제2 도전포스트들의 상면 및 하면들 상에 표면전극들을 형성하는 단계를 더 포함하는 반도체장치의 제조방법.
  12. 제10항에 있어서,
    이면 및 양 단부들은 땜납페이스트를 이용해서 각각 천장부 및 제2도전포스트들에 고착되는 반도체장치의 제조방법.
  13. 제10항에 있어서,
    반도체소자들은 절연기판상에 매트릭스상으로 배치되고,
    금속블록은 반도체소자들에 공통인 직사각형상으로 형성되는 반도체장치의 제조방법.
  14. 제10항에 있어서,
    수지밀봉은 트랜스퍼몰딩법 또는 포팅법을 이용해서 행해지는 반도체장치의제조방법.
  15. 제13항에 있어서, 수지밀봉후 절연성 기판을 절단하여 개개의 반도체소자들로 분리하는 하는 단계를 더 포함하는 반도체장치의 제조방법.
  16. 절연성 기판을 갖는 반도체장치의 제조방법에 있어서,
    절연성 기판에 복수의 스루홀들을 개구하는 단계;
    하나의 제1도전포스트 및 한 쌍의 제2도전포스트들로 분류되는 복수의 도전포스트들을 스루홀들에 매립하는 단계;
    도전성 접착제를 거쳐 표면전극들을 제1도전포스트에 접속시키는 것에 의해 절연성 기판상의 표면측에 표면전극을 갖는 반도체소자를 탑재하는 단계;
    단면형상이 사각아치상으로 형성되며, 천장부 및 양 단부들을 갖는 금속블록을, 도전성 접착제를 거쳐 천장부와 반도체소자 이면을 접촉시키고, 도전성 접착제를 거쳐 제2도전포스트들과 양 단부들을 접촉시켜서 절연성 기판상에 탑재하는 단계;
    표면전극 및 양 단부들이 제1 및 제2 도전포스트들에 고착되고, 이면이 천장부에 고착되도록 반도체장치를 경화하는 단계; 및
    반도체소자를 수지밀봉하는 단계를 포함하는 반도체장치의 제조방법.
  17. 제16항에 있어서,
    도전성 접착제는 도전성 페이스트를 포함하는 반도체장치의 제조방법.
  18. 제17항에 있어서,
    도전성 페이스트는 땜납 페이스트 또는 Ag 페이스트를 포함하는 반도체장치의 제조방법.
  19. 제16항에 있어서,
    반도체소자들은 절연기판상에 매트릭스상으로 배치되고,
    금속블록은 반도체소자들에 공통인 직사각형상으로 형성되는 반도체장치의 제조방법.
  20. 제16항에 있어서,
    수지밀봉은 트랜스퍼몰딩법 또는 포팅법을 이용해서 행해지는 반도체장치의 제조방법.
  21. 제16항에 있어서, 수지밀봉후 절연성 기판을 절단하여 개개의 반도체소자들로 분리하는 하는 단계를 더 포함하는 반도체장치의 제조방법.
KR10-2001-0031209A 2000-06-05 2001-06-04 반도체장치 및 그것의 제조방법 KR100399012B1 (ko)

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Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6624522B2 (en) * 2000-04-04 2003-09-23 International Rectifier Corporation Chip scale surface mounted device and process of manufacture
US6791172B2 (en) * 2001-04-25 2004-09-14 General Semiconductor Of Taiwan, Ltd. Power semiconductor device manufactured using a chip-size package
US6784540B2 (en) 2001-10-10 2004-08-31 International Rectifier Corp. Semiconductor device package with improved cooling
JP3888439B2 (ja) * 2002-02-25 2007-03-07 セイコーエプソン株式会社 半導体装置の製造方法
EP1357594A1 (en) * 2002-04-23 2003-10-29 General Semiconductor of Taiwan, Ltd. Power semiconductor device manufactured using a chip-size package
JP3853263B2 (ja) * 2002-07-08 2006-12-06 Ｎｅｃエレクトロニクス株式会社 半導体装置
US7397137B2 (en) * 2002-07-15 2008-07-08 International Rectifier Corporation Direct FET device for high frequency application
US7579697B2 (en) 2002-07-15 2009-08-25 International Rectifier Corporation Arrangement for high frequency application
DE10240461A1 (de) * 2002-08-29 2004-03-11 Infineon Technologies Ag Universelles Gehäuse für ein elektronisches Bauteil mit Halbleiterchip und Verfahren zu seiner Herstellung
WO2004057662A2 (en) * 2002-12-20 2004-07-08 Koninklijke Philips Electronics N.V. Electronic device and method of manufacturing same
TW587325B (en) * 2003-03-05 2004-05-11 Advanced Semiconductor Eng Semiconductor chip package and method for manufacturing the same
US20050269677A1 (en) * 2004-05-28 2005-12-08 Martin Standing Preparation of front contact for surface mounting
US20060220218A1 (en) * 2005-03-11 2006-10-05 Charng-Geng Sheen Embedded-type power semiconductor package device
US7524701B2 (en) * 2005-04-20 2009-04-28 International Rectifier Corporation Chip-scale package
US7230333B2 (en) * 2005-04-21 2007-06-12 International Rectifier Corporation Semiconductor package
US8466546B2 (en) 2005-04-22 2013-06-18 International Rectifier Corporation Chip-scale package
WO2007123648A2 (en) * 2006-03-28 2007-11-01 Cirque Corporation Capacitance sensing touchpad circuit capable of dual use as a touchpad controller and keyboard controller
JP4795883B2 (ja) * 2006-07-21 2011-10-19 株式会社日立ハイテクノロジーズ パターン検査・計測装置
JP4906496B2 (ja) * 2006-12-25 2012-03-28 新光電気工業株式会社 半導体パッケージ
US7759777B2 (en) * 2007-04-16 2010-07-20 Infineon Technologies Ag Semiconductor module
DE102007017831B8 (de) * 2007-04-16 2016-02-18 Infineon Technologies Ag Halbleitermodul und ein Verfahren zur Herstellung eines Halbleitermoduls
JP5601751B2 (ja) * 2007-04-26 2014-10-08 スパンション エルエルシー 半導体装置
US8067256B2 (en) * 2007-09-28 2011-11-29 Intel Corporation Method of making microelectronic package using integrated heat spreader stiffener panel and microelectronic package formed according to the method
US8507320B2 (en) * 2008-03-18 2013-08-13 Infineon Technologies Ag Electronic device including a carrier and a semiconductor chip attached to the carrier and manufacturing thereof
JPWO2009144960A1 (ja) * 2008-05-30 2011-10-06 三洋電機株式会社 半導体モジュール、半導体モジュールの製造方法および携帯機器
JP5214550B2 (ja) * 2009-07-06 2013-06-19 株式会社テラミクロス 電力半導体装置の製造方法
US9399574B2 (en) 2009-08-13 2016-07-26 Knowles Electronics Llc MEMS package and a method for manufacturing the same
US8987030B2 (en) * 2009-08-13 2015-03-24 Knowles Electronics, Llc MEMS package and a method for manufacturing the same
TWI395522B (zh) * 2009-09-15 2013-05-01 Unimicron Technology Corp 內埋式元件基板結構及其製作方法
TWI442530B (zh) * 2009-10-14 2014-06-21 Advanced Semiconductor Eng 封裝載板、封裝結構以及封裝載板製程
US8587107B2 (en) * 2010-02-09 2013-11-19 Microsemi Corporation Silicon carbide semiconductor
US8237171B2 (en) * 2010-02-09 2012-08-07 Microsemi Corporation High voltage high package pressure semiconductor package
US8513062B2 (en) * 2010-02-16 2013-08-20 Infineon Technologies Ag Method of manufacturing a semiconductor device with a carrier having a cavity and semiconductor device
JP2012028400A (ja) * 2010-07-20 2012-02-09 Denso Corp 半導体装置
JP2012028398A (ja) * 2010-07-20 2012-02-09 Denso Corp 半導体装置
JP2012028399A (ja) * 2010-07-20 2012-02-09 Denso Corp 半導体装置
JP2012028401A (ja) * 2010-07-20 2012-02-09 Denso Corp 半導体装置
JP5411981B2 (ja) * 2012-12-05 2014-02-12 スパンション エルエルシー 半導体装置の製造方法
DE102013204889A1 (de) * 2013-03-20 2014-09-25 Robert Bosch Gmbh Leistungsmodul mit mindestens einem Leistungsbauelement
WO2015004952A1 (ja) * 2013-07-09 2015-01-15 株式会社村田製作所 回路基板
JP6157998B2 (ja) * 2013-09-03 2017-07-05 ルネサスエレクトロニクス株式会社 半導体装置
JP2015231027A (ja) * 2014-06-06 2015-12-21 住友電気工業株式会社 半導体装置
JP6314729B2 (ja) * 2014-07-30 2018-04-25 株式会社ソシオネクスト 半導体装置及び半導体装置の製造方法
TWI545714B (zh) * 2015-03-06 2016-08-11 矽品精密工業股份有限公司 電子封裝件及其製法
US9887145B2 (en) * 2015-04-03 2018-02-06 Dawning Leading Technology Inc. Metal top stacking package structure and method for manufacturing the same
US10083888B2 (en) * 2015-11-19 2018-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP6741419B2 (ja) 2015-12-11 2020-08-19 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージおよびその製造方法
EP3648159B1 (en) 2018-10-31 2021-12-15 Infineon Technologies Austria AG Semiconductor package and method of fabricating a semiconductor package
US11532541B2 (en) 2020-01-28 2022-12-20 Infineon Technologies Ag Semiconductor package having a solderable contact pad formed by a load terminal bond pad of a power semiconductor die
US11502012B2 (en) 2020-01-28 2022-11-15 Infineon Technologies Ag Semiconductor packages and methods of manufacturing thereof
CN115116991B (zh) * 2022-08-29 2022-11-04 威海艾迪科电子科技股份有限公司 一种传感器及其制造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3995300A (en) * 1974-08-14 1976-11-30 Tdk Electronics Company, Limited Reduction-reoxidation type semiconducting ceramic capacitor
JPS58225659A (ja) * 1982-06-24 1983-12-27 Mitsubishi Electric Corp 半導体装置
JPS5992558A (ja) 1982-11-19 1984-05-28 Hitachi Ltd 半導体集積回路装置
JP3002034B2 (ja) * 1991-10-02 2000-01-24 株式会社日立製作所 半導体集積回路装置
JPH05267549A (ja) 1992-03-18 1993-10-15 Sumitomo Electric Ind Ltd 半導体装置
US5616520A (en) * 1992-03-30 1997-04-01 Hitachi, Ltd. Semiconductor integrated circuit device and fabrication method thereof
JPH0637122A (ja) 1992-07-15 1994-02-10 Hitachi Ltd 半導体装置
JPH06268020A (ja) * 1993-03-10 1994-09-22 Sumitomo Electric Ind Ltd 半導体装置
US5459368A (en) * 1993-08-06 1995-10-17 Matsushita Electric Industrial Co., Ltd. Surface acoustic wave device mounted module
JPH07245360A (ja) 1994-03-02 1995-09-19 Toshiba Corp 半導体パッケージおよびその製造方法
US6232152B1 (en) * 1994-05-19 2001-05-15 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
JPH08125051A (ja) 1994-10-27 1996-05-17 Hitachi Ltd 半導体装置
JP3301262B2 (ja) * 1995-03-28 2002-07-15 松下電器産業株式会社 弾性表面波装置
JP3297254B2 (ja) 1995-07-05 2002-07-02 株式会社東芝 半導体パッケージおよびその製造方法
JPH10209204A (ja) 1997-01-24 1998-08-07 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JPH113901A (ja) 1997-04-17 1999-01-06 Sony Corp 電子部品の製造方法
US5909056A (en) * 1997-06-03 1999-06-01 Lsi Logic Corporation High performance heat spreader for flip chip packages
JP3163419B2 (ja) 1997-08-22 2001-05-08 日本レック株式会社 電子部品の製造方法
JP3834426B2 (ja) * 1997-09-02 2006-10-18 沖電気工業株式会社 半導体装置
JP4011693B2 (ja) 1997-10-30 2007-11-21 シチズンホールディングス株式会社 半導体パッケージの製造方法
TW401632B (en) 1998-03-26 2000-08-11 Fujitsu Ltd Resin molded semiconductor device and method of manufacturing semiconductor package
JP3601985B2 (ja) 1998-10-30 2004-12-15 富士通株式会社 半導体パッケージの製造方法
KR100270888B1 (ko) * 1998-04-08 2000-12-01 윤종용 노운 굿 다이 제조장치
JP2000025074A (ja) 1998-07-14 2000-01-25 Aoi Denshi Kk モールド装置、モールド方法、モールドされた半導体装置の切断方法及び半導体装置の作製方法
US6239980B1 (en) * 1998-08-31 2001-05-29 General Electric Company Multimodule interconnect structure and process
TW388976B (en) * 1998-10-21 2000-05-01 Siliconware Precision Industries Co Ltd Semiconductor package with fully exposed heat sink

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