TW501255B - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- TW501255B TW501255B TW090113643A TW90113643A TW501255B TW 501255 B TW501255 B TW 501255B TW 090113643 A TW090113643 A TW 090113643A TW 90113643 A TW90113643 A TW 90113643A TW 501255 B TW501255 B TW 501255B
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- Taiwan
- Prior art keywords
- conductive
- semiconductor device
- patent application
- electrode
- substrate
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000011347 resin Substances 0.000 claims abstract description 42
- 229920005989 resin Polymers 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000007789 sealing Methods 0.000 claims description 15
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 13
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 239000004332 silver Substances 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 238000000465 moulding Methods 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims 3
- 230000001070 adhesive effect Effects 0.000 claims 3
- 239000011159 matrix material Substances 0.000 claims 2
- 238000004806 packaging method and process Methods 0.000 claims 2
- 238000011000 absolute method Methods 0.000 claims 1
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 239000002245 particle Substances 0.000 description 31
- 241000283216 Phocidae Species 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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Description
5〇1255 五、發明說明(1) 【發明背景】 本發明大體上是關於半導體裴置及其势造方法。 更特別的是,此發明係針對功率裝置:安裝結構。 在習用的功率裝置封裝中’―般使用導線架來設置類 功率裝置的半導體裝置,並利用&纟g 樹脂密封。 已知移動成形法來進行 參照圖Μ與1B,將描述日本公開專利公報(Jp_
Hei· 6-37 1 22號所揭露的功率裝置之安裝法。 ^ 在組合半導體裝置前,以衝壓一金^ ° 具有頭部(晶粒焊墊)21與由堤部(繫噹式^形= 的導線架23。 繫片)26所連結之導線23 對於此結構來說,是直接在該頭部2〗之上 連接部之膠粒外圍部下方形成凹槽28。 '厂、 如圖iA所示,膠粒22係以焊料託而附 此外直:線=連接在膠粒22上的電極 其後,將連同膠粒U所設置的導線架安裝在密圭晶粒 個導線23分開。 稽田切d %部26將各 在上述的安裝方法中,會依照裝 间 線架設計成不同形狀。闵而如办t 種類不同而將導 m ^ 因而’在各個種類中的萝造設備是 固定的’因而使得生產線不具有彈性。備疋 此外’在各個種類中必須製 成金屬導線架。這歧情況合】 = 導線架,以便形 、一 h况會導致成本升高。再者,減少由 五、發明說明(2) 導線架所引起的裝置數 复数里以便降低生產效率。 I通之,在習用方法中,很難提 裝。 丁很雞权仏廉^貝的的功率裝置封 【發明概述】 因此本發明之目的是提供一種具有小 結構的半導體裝置。 寸/、廉價安裝 在本發明的半導體裝置中,-絕緣基板具右、“ 孔。 极具有複數個通 而複數個導電端子係埋在通 電端子係至少割分A楚增#山 牡知·種情況下,導 子。 刀4一第—導電端子與一對第二導電端導 二匕外’―半導體元件至少具有位在表面的 極。i ϊ ’表面電極係以面朝下法連接至第-導“:. 再者,形成橫剖面視為方形拱狀且具有一=, 部的一金屬區塊。在此U半導體元件之_ 兩端 部,並以兩端部圈住第二導電端子。 月面圈住頂 此外,一密封樹脂會密封住半導體元件。 極 對此結構來說,半導體元件具有位在背面的— 而此背面電極係經由金屬區塊連接至第二 牙面電 在這種情況了,各個第一與第二導電端 U子。 銅膏來形成。 J籍著使用 此外,一第一基板電極係形成在第一導電# 表面電極係經由第一基板電極連接至第一導電^子^。而 501255
在此,第一基板電極可 再者,一第二基板電極 金屬區塊係經由第二基板電 在此,第二基板電極可 在這種情況下,表面電 基板則包含有一樹脂基板。 藉著使用銀膏來形成。 係形成在第二導電端子上。而 極連接至第二導電端子。 籍著使用銀膏來形成。 極包含有一凸塊電極。而絕緣 特別的是使用諸如樹脂層板的絕緣基板。此外, 體裝置之背面電極是透過一般作為熱槽的金屬區塊取出= 絕緣基板該側的。而半導體基板會完全讓樹脂密封住, 藉著使用切方塊之器具將其切割成獨立的元件。 、 因此’可在不考慮設備種類、 製造功率裝置。 具有高彈性的生產線中 裝置此外’在安裝結構可獲得具有高敷熱性的小尺寸功率 更特別的是,藉著使用面朝下法,將膠粒安裝在具 導電端子的絕緣基板上。此外,金屬區塊會覆蓋其上^致 使可將膠粒的背面電極取出至導電端子處。 在將複數個膠粒完樹脂密封住後,藉著使用切方塊之 器具將膠粒切割成獨立的元件。 因此不需要昂貴的製造設備。此外,可在具有高彈性 的生產線中製造半導體裝置,且可有效率地製造半導體裝 置。 ^ 一再者,在不需要使用導線架的情況下,廉價地提供具 有高散熱性的小尺寸封裝。 "
第7頁 501255 五、發明說明(4) 【較佳實施例】 [第一實施例] 以下將參照圖2A至2C來描述第一實施例。 . 如圖2A至2C所示,在由玻璃環氧樹脂層板製成的樹脂 基板1中開啟通孔2,以便穿透樹脂基板1。其中,將導電 端子3埋在通孔2中。在此,各個導電端子3是由銅膏所製 成的。 而基板電極4則是藉著使用銀膏而形成在導電端子3的 上下表面上。 至於具有凸塊電極6的膠粒5係藉著已知方法而安裝在 樹脂基板1的表侧上。此外,金屬區塊7會覆蓋膠粒5。 對於類似這樣的結構,金屬區塊7與基板電極4,以及 金屬區塊7與膠粒5的背面電極會分別透過焊料8而連接在 一起0 =的是’作為膠粒5之主要電極的背面電極係經由 姑i f 與導電端子3連接至位在樹脂基板1背面該侧處 & t=Γ蛋4。此外’樹脂基板1係以密封樹脂1 〇為成形樹
脂來將加以密封的。 J 般矣ΐΐϊί導體裝置中’由勝粒5所產生的熱會透過膠 來,亦合透渦ί «而抵達導電端子3的路徑有效地輻射出 一路^ 4 屬區塊7而從膠粒#面抵達金屬端子3的另 路徑有效地輻射出來。 更特別的疋,由於如圖丨所示的習·用結構之膠粒表側
501255 五、發明說明(5) 覆蓋著密封樹脂,因此無法有效地實行熱量消散。相較之 下,本實施例中可有效地從膠粒5表侧執行熱量消散。 參照圖圖3 A至4 C將描述本發明第一實施例的製造方 法。 首先,利用衝壓在由樹脂層板組成的樹脂基板1中開 啟通孔2,如圖3 A所示。 此外,藉著使用已知的輔助刀片法將銅膏施加到通孔 2中,並將銅膏加以烘烤以便形成導電端子3,。 在這種情況下,樹脂基板1具有可讓複數個膠粒設置 在如圖3 A所示各處的長度。此外,樹脂基板1亦具有可讓 複數個膠粒排列在如圖3 A與圖5所示縱深方向的長度。 其後’利用已知的遮敝印刷法將銀膏施加至銅端子3 的上下表面上,並將銀膏加以烘烤以便形成基板電極4, 如圖3B所示。 接下來’將上面具有凸塊電極6而背面該侧具有背面 電極的膠粒5翻轉。將翻轉後的膠粒5放置在(面朝下)基板 1上’並將其加熱/施壓以便讓基板電極4與凸塊電極6連 接,如圖3 C所示。 接續,將焊料糊施加在膠粒5之上與金屬區塊7下表面 兩側。之後,將金屬區塊7放置在膠粒5上。此外,藉著通 過回流室(未圖示)與使用焊料8,以金屬區塊7黏住或圍住 基板電極4與膠粒5,如圖4 A所示。 其後,將設有膠粒5與金屬區塊7的樹脂基板1安裝在 密封晶粒9的内侧。在將晶粒9夾緊後,在預定時期内將從
第9頁 501255
圖4B之前方強化的熔解環氧基底樹脂固化 月曰1 0將其進行樹脂密封。 並使用密封樹 密封出將如圖4B所示之條件内的批密封產物* 產物接L = = 鑛/:二的刀片12切割密封 體穿置。 各個封裝。藉此獍侍如圖2所示的半導 [第二實施例] 其後將敘述本發明第二實施例。 一以下將解說如圖2所示的第一實施例與如圖6所示的 一實施例之間的區別。 首先,在第二實施例中,密封樹脂10僅形成在金屬區 塊7的内侧,而不會形成在金屬區塊7的外侧表面上。 第二,以焊料球14取代基板電極4來形成在樹脂基板i 的背面該侧處。且在第二實施例中乃是應用膠粒,其中僅 在表面該側形成電極。 參照圖7A至8C,以下將敘述本發明第二實施例的製造 方法。 如圖7A所示,在樹脂基板丨中開啟通孔2,並在通孔2 中形成導電端子3。此步驟實質上與第一實施例相同。 接下來,箱者使用遮蔽印刷法將銀嘗施加至銅端子3 的上表面上以便形成基板電極4,如圖7B所示。 之後’將上面具有凸塊電極6並施以作為導電黏著層
501255 五、發明說明(7)
1 3之銀膏的膠粒5翻轉。然後,將翻轉後的膠粒5放置在義 板1上’並在其上覆蓋金屬區塊7。 接著,將膠粒5連同銀膏一併烘烤,並將其黏貼到樹 脂基板1。此外,以金屬區塊7圈住樹脂基板1與膠粒5。在
此’應注意可將作為導電黏著層1 3的銀膏施加在金屬區 7該侧處。 °° I 其後,讓設有膠粒5與金屬區塊7的樹脂基板丨橫向落 下,如圖8A所示。此外,將密封樹脂供應至由樹脂基板工 與金屬區塊7所環繞之空間的内側,並將該密封樹脂 以便形成密封樹脂1〇。 接下來’以焊料球1 4圈住導電端+ 3的下| 8Β所示。 守电鳊子3的下表面,如圖 屬巴,:切方塊之器具的刀片12切割樹脂基板1盘全 ,塊? ’並將其分成各個封裝敬: 所示的半導體基板。 來即獲侍如圖6 當本發明隨著其數種實施例一併揭t^ 項技術之相關人本*〜 # 併揭路k,對於熟悉該 方式中。 5兄,可藉由本發明來應用在各種其他 = 材料來取代鋼膏或銀膏。 封。又,在分開二所不的狀態中來執行樹脂密 後,可實行樹脂密封。谷線(仃)或複數線(行) 下,~Τ者在同k將金屬區塊黏貼至基;+ 可使用焊料膏來當作__ 基板與膠粒球的情況
第11頁 爾彳乍圈住構件的導電材料。 501255
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501255 圖式簡單說明 圖1 A是顯示習用案例之立體圖。 圖1B是顯示習用案例之橫剖面圖。 圖2A是顯示第一實施例的半導體裝置之平面圖。 圖2B是顯示第一實施例的半導體裝置之橫剖面圖。 圖2C是顯示第一實施例的半導體裝置之底視圖。 圖3A至3C是顯示第一實施例之半導體裝置的製造方法 之橫剖面圖。 圖4A至4C是顯示第一實施例之半導體裝置的製造方法 之橫剖面圖。 圖5是顯示第一實施例的製造步驟之平面圖。 圖6A是顯示第二實施例的半導體裝置之平面圖。 圖6B是顯示第二實施例的半導體裝置之橫剖面圖。 圖6C是顯示第二實施例的半導體裝置之底視圖。 圖7A至7C是顯示第二實施例之半導體裝置的製造方法 之橫剖面圖。 圖8A至8C是顯示第二實施例之半導體裝置的製造方法 之橫剖面圖。 _ 符號說明】 樹脂基板 通孔 導電端子 基板電極 、2.2 膠粒
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第14頁
Claims (1)
- 1· 一種半導體裝置,其包含: 一絕緣基板,其具有複數個通孔; y複數個導電端子,其係埋在談通孔中,而該導電* 係至 > 劃分為一第一導電端子與一對第二導電端子丨而子 一半導體元件,其至少具有位在表面的一表面 而該表面電極係以面朝下法連接至該第一導電端子;極’ τ首却Γ金屬區塊,以橫剖面視其為方形拱狀,且其具右 並以該兩端部圈住該第牛之:背面圈住該頂部, -密封樹脂,其用以密導體元件。 2. 子 如申請專利範圍第1項的半導體裝置,其中: 該f導體元件具有位在背面的一背面電極,且, 忒老面電極係經由該金屬區塊連接至該第二導電端3. 〇 如申請專利範圍第1項的 各個該第一與第二導電 半導體裝置,其中: 端子係藉著使用銅膏形成的4·如申請專利範圍第1項的半導體裝置,其中: -第-基板電極係形成在該第一導電端子上,且, 该表面電極係經由該第一基板電極連接至該第一導 端子。/、、申請專利範圍 ^ ----- •如申請專利範圍第4項的半導體裝置,其中: 忒第一基板電極係藉著使用銀膏形成的。 •如_申請專利範圍第1項的半導體裝置,其中·· 第二基板電極係形成在該第二導電端子上,且, 端=金屬區塊係經由該第二基板電極連接至該第二導電 如申请專利範圍第6項的半導體裝置,其中: 以第二基板電極係藉著使用銀膏形成的。 如申清專利範圍第1項的半導體裝置,其中: 該表面電極包含有一凸塊電極。 如申睛專利範圍第i項的半導體裝置,其中: ^絕緣基板包含有一樹脂基板。 缘美拓種::體裝置之製造方法,該半導體裝置具有-絕 緣基板,該製造方法包含下列步驟:有、、、邑 在該絕緣基板中,開啟複數個通孔; 少劃t ί ΐ ΐ:暮ΐ:複數個導電端子,該導電端子係至 一" 導電端子與一對第二導電端子; 藉者將該表面電極以面朝下法連接至該 子,來設置一半導體元件,其至少具有位在該絕上 501255 六、申請專利範圍 之表面的一表面電極; 設置一金屬區塊,其中以橫剖面視該金屬區塊為方形 拱狀,且其具有一頂部與兩端部,而該金屬區塊係藉著以 該半導體元件之一背面圈住該頂部,並以該兩端部圈住該 第二導電端子來設置的;以及, 樹脂密封該半導體元件。 11. 如申請專利範圍第1 0項的半導體裝置之製造方法,更 包含下列步驟: 在該第一與第二導電端子之上下表面上,形成基板電 極0 12. 如申請專利範圍第10項的半導體裝置之製造方法,其 中: 該背面與該兩端部係各自藉著使用焊料膏圈住該頂部 與該第二導電端子。 13. 如申請專利範圍第1 0項的半導體裝置之製造方法,其 中: 該半導體元件係以一矩陣形狀設置在該絕緣基板上, 且, 該金屬區塊係形成在與該半導體元件共通的一矩形 中 0第17頁 501255 六、申請專利範圍 14. 如申請專利範圍第10項的半導體裝置之製造方法,其 中: 該樹脂密封係藉著使用一移動成形法或一封裝法所執 行的。 15. 如申請專利範圍第1 4項的半導體裝置之製造方法,更 包含下列步驟: 在樹脂密封後,藉著切割該絕緣基板,來分成獨立的 半導體元件。 16. 一種半 緣基板,該 在該絕 在該通 導體裝 製造方 緣基板 置之製造方法,該半導體裝置具有一絕 法包含下列步驟 中,開啟複數個 孔中,埋入複數個導電 少劃分為一第一導電端子與一對第 該表面電極經由導電黏 置一半導體元件,其具 藉著將 端子,來設 表面的一表面電極 設置一金屬區塊,其中以橫剖 具有一頂部與兩端部, 件之一背面經由該導電 該導電黏著劑與 拱狀,且其 該半導體元 並讓該兩端 設置的;以 黏住該 通孔; 端子,該導電端子係至 二導電端子; 著劑連接至該第一導電 有位在該絕緣基板上之 面視該金屬區塊為方形 而該金屬區塊係藉者讓 黏著劑與該頂部接觸, 該第二導電端子接觸來 部經由及, 半導體元件,致使以該表面電極與該兩端部圈第18頁 六、申請專利範圍 住該第一與第二導電端子,且以該背面圈住該 及 了貝部;以 樹脂密封該半導體元件 7·如申請專利範圍第1 6項的半導體裝置之製造方 法,其 該導電黏著劑包含有導電膏。 ··如申綣專利範圍第丨7項的半導體裝置之製造方 該導電膏包含有焊料膏或銀膏。 1中9..如申請專利範圍第16項的半導體裝置之製造方法,其 該半導體元件係以一矩陣形狀設置在該絕緣基板上, 該金屬區塊係形成在與該半導體元件共通的— 法,其 且 中 矩形 2中。.··如申請專利範圍第16項的半導體裝置之製造方 該樹脂密封係藉著使用一 行的 法,其 動成形法或一封裝法所執 第19頁 501255 六、申請專利範圍 21.如申請專利範圍第1 6項的半導體裝置之製造方法,更 包含下列步驟: 在樹脂密封後,藉著切割該絕緣基板,來分成獨立的 半導體元件。第20頁
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