KR100310512B1 - 트랜지스터절연방법 - Google Patents

트랜지스터절연방법 Download PDF

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Publication number
KR100310512B1
KR100310512B1 KR1019940006492A KR19940006492A KR100310512B1 KR 100310512 B1 KR100310512 B1 KR 100310512B1 KR 1019940006492 A KR1019940006492 A KR 1019940006492A KR 19940006492 A KR19940006492 A KR 19940006492A KR 100310512 B1 KR100310512 B1 KR 100310512B1
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KR
South Korea
Prior art keywords
gate
substrate
insulating region
layer
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019940006492A
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English (en)
Korean (ko)
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KR940022796A (ko
Inventor
볼프강 크라우취나이더
베르너 클링엔슈타인
Original Assignee
칼 하인쯔 호르닝어
지멘스 악티엔게젤샤프트
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 칼 하인쯔 호르닝어, 지멘스 악티엔게젤샤프트 filed Critical 칼 하인쯔 호르닝어
Publication of KR940022796A publication Critical patent/KR940022796A/ko
Application granted granted Critical
Publication of KR100310512B1 publication Critical patent/KR100310512B1/ko
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1019940006492A 1993-03-30 1994-03-30 트랜지스터절연방법 Expired - Fee Related KR100310512B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US4031993A 1993-03-30 1993-03-30
US8/040.319 1993-03-30
US08/040.319 1993-03-30

Publications (2)

Publication Number Publication Date
KR940022796A KR940022796A (ko) 1994-10-21
KR100310512B1 true KR100310512B1 (ko) 2001-12-15

Family

ID=21910354

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940006492A Expired - Fee Related KR100310512B1 (ko) 1993-03-30 1994-03-30 트랜지스터절연방법

Country Status (7)

Country Link
US (1) US5854112A (enExample)
EP (1) EP0618616B1 (enExample)
JP (1) JPH06302789A (enExample)
KR (1) KR100310512B1 (enExample)
AT (1) ATE221254T1 (enExample)
DE (1) DE69431012T2 (enExample)
TW (1) TW299475B (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102356815B1 (ko) 2013-11-14 2022-01-27 롬 앤드 하스 일렉트로닉 머트어리얼즈 엘엘씨 갭-충전 방법
JP6014110B2 (ja) 2013-12-23 2016-10-25 ダウ グローバル テクノロジーズ エルエルシー ギャップ充填方法
US9324604B2 (en) 2014-07-04 2016-04-26 Rohm And Haas Electronic Materials Llc Gap-fill methods

Family Cites Families (32)

* Cited by examiner, † Cited by third party
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JPS4914390B1 (enExample) * 1969-10-29 1974-04-06
JPS6041470B2 (ja) * 1976-06-15 1985-09-17 松下電器産業株式会社 半導体装置の製造方法
NL164109C (nl) * 1977-06-08 1980-11-17 Ballast Nedam Groep Nv Baggervaartuig.
US4373248A (en) * 1978-07-12 1983-02-15 Texas Instruments Incorporated Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like
JPS5737830A (en) * 1980-08-19 1982-03-02 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS5771144A (en) * 1980-10-21 1982-05-01 Fujitsu Ltd Manufacture of semiconductor device
JPS5861672A (ja) * 1981-10-09 1983-04-12 Nec Corp 絶縁ゲ−ト型電界効果半導体集積回路装置およびその製造方法
CA1186808A (en) * 1981-11-06 1985-05-07 Sidney I. Soclof Method of fabrication of dielectrically isolated cmos device with an isolated slot
JPS58165341A (ja) * 1982-03-26 1983-09-30 Toshiba Corp 半導体装置の製造方法
JPS5976472A (ja) * 1982-10-26 1984-05-01 Toshiba Corp 半導体装置の製造方法
JPS59148360A (ja) * 1983-02-14 1984-08-25 Fujitsu Ltd 半導体記憶装置及びその製造方法
US4679303A (en) * 1983-09-30 1987-07-14 Hughes Aircraft Company Method of fabricating high density MOSFETs with field aligned channel stops
JPS61102750A (ja) * 1984-10-26 1986-05-21 Hamamatsu Photonics Kk 半導体装置
JPS6231177A (ja) * 1985-08-02 1987-02-10 Nec Corp 不揮発性半導体記憶装置
US4737828A (en) * 1986-03-17 1988-04-12 General Electric Company Method for gate electrode fabrication and symmetrical and non-symmetrical self-aligned inlay transistors made therefrom
EP0368097A3 (en) * 1988-11-10 1992-04-29 Texas Instruments Incorporated A cross-point contact-free floating-gate memory array with silicided buried bitlines
IT1227989B (it) * 1988-12-05 1991-05-20 Sgs Thomson Microelectronics Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione
JPH0775243B2 (ja) * 1989-02-22 1995-08-09 株式会社東芝 半導体装置の製造方法
JPH088313B2 (ja) * 1989-07-25 1996-01-29 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US4968900A (en) * 1989-07-31 1990-11-06 Harris Corporation Programmable speed/power arrangement for integrated devices having logic matrices
IT1236601B (it) * 1989-12-22 1993-03-18 Sgs Thomson Microelectronics Dispositivo a semiconduttore integrato di tipo eprom con connessioni metalliche di source e procedimento per la sua fabbricazione.
US5039625A (en) * 1990-04-27 1991-08-13 Mcnc Maximum areal density recessed oxide isolation (MADROX) process
IT1243303B (it) * 1990-07-24 1994-05-26 Sgs Thomson Microelectronics Schieramento di celle di memoria con linee metalliche di connessione di source e di drain formate sul substrato ed ortogonalmente sovrastate da linee di connessione di gate e procedimento per la sua fabbricazione
US5278438A (en) * 1991-12-19 1994-01-11 North American Philips Corporation Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure
JP2833323B2 (ja) * 1992-02-18 1998-12-09 日本電気株式会社 半導体装置
JPH05299414A (ja) * 1992-04-20 1993-11-12 Sharp Corp 半導体装置における素子分離酸化膜の形成方法
US5350706A (en) * 1992-09-30 1994-09-27 Texas Instruments Incorporated CMOS memory cell array
JP3431198B2 (ja) * 1993-02-26 2003-07-28 株式会社東芝 半導体記憶装置およびその製造方法
US5633187A (en) * 1995-09-22 1997-05-27 United Microelectronics Corporation Process for fabricating read-only memory cells
US5679602A (en) * 1996-01-29 1997-10-21 United Microelectronics Corporation Method of forming MOSFET devices with heavily doped local channel stops
US5763309A (en) * 1996-06-24 1998-06-09 Macronix International Co., Ltd. Self-aligned isolation and planarization process for memory array
US5766992A (en) * 1997-04-11 1998-06-16 Taiwan Semiconductor Manufacturing Company Ltd. Process for integrating a MOSFET device, using silicon nitride spacers and a self-aligned contact structure, with a capacitor structure

Also Published As

Publication number Publication date
KR940022796A (ko) 1994-10-21
ATE221254T1 (de) 2002-08-15
EP0618616A3 (en) 1997-09-10
DE69431012D1 (de) 2002-08-29
US5854112A (en) 1998-12-29
EP0618616B1 (en) 2002-07-24
TW299475B (enExample) 1997-03-01
EP0618616A2 (en) 1994-10-05
DE69431012T2 (de) 2002-11-28
JPH06302789A (ja) 1994-10-28

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