ATE221254T1 - Verfahren zur isolierung von transistoren - Google Patents

Verfahren zur isolierung von transistoren

Info

Publication number
ATE221254T1
ATE221254T1 AT94103189T AT94103189T ATE221254T1 AT E221254 T1 ATE221254 T1 AT E221254T1 AT 94103189 T AT94103189 T AT 94103189T AT 94103189 T AT94103189 T AT 94103189T AT E221254 T1 ATE221254 T1 AT E221254T1
Authority
AT
Austria
Prior art keywords
devices
gate
rows
isolation region
layers
Prior art date
Application number
AT94103189T
Other languages
English (en)
Inventor
Wolfgang Krautschneider
Werner Klingenstein
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Application granted granted Critical
Publication of ATE221254T1 publication Critical patent/ATE221254T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
AT94103189T 1993-03-30 1994-03-03 Verfahren zur isolierung von transistoren ATE221254T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US4031993A 1993-03-30 1993-03-30

Publications (1)

Publication Number Publication Date
ATE221254T1 true ATE221254T1 (de) 2002-08-15

Family

ID=21910354

Family Applications (1)

Application Number Title Priority Date Filing Date
AT94103189T ATE221254T1 (de) 1993-03-30 1994-03-03 Verfahren zur isolierung von transistoren

Country Status (7)

Country Link
US (1) US5854112A (de)
EP (1) EP0618616B1 (de)
JP (1) JPH06302789A (de)
KR (1) KR100310512B1 (de)
AT (1) ATE221254T1 (de)
DE (1) DE69431012T2 (de)
TW (1) TW299475B (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6742686B2 (ja) 2013-11-14 2020-08-19 ローム アンド ハース エレクトロニック マテリアルズ エルエルシーＲｏｈｍ ａｎｄ Ｈａａｓ Ｅｌｅｃｔｒｏｎｉｃ Ｍａｔｅｒｉａｌｓ ＬＬＣ ギャップ充填方法
JP6014110B2 (ja) 2013-12-23 2016-10-25 ダウ グローバル テクノロジーズ エルエルシー ギャップ充填方法
US9324604B2 (en) 2014-07-04 2016-04-26 Rohm And Haas Electronic Materials Llc Gap-fill methods

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JPS5861672A (ja) * 1981-10-09 1983-04-12 Nec Corp 絶縁ゲ−ト型電界効果半導体集積回路装置およびその製造方法
CA1186808A (en) * 1981-11-06 1985-05-07 Sidney I. Soclof Method of fabrication of dielectrically isolated cmos device with an isolated slot
JPS58165341A (ja) * 1982-03-26 1983-09-30 Toshiba Corp 半導体装置の製造方法
JPS5976472A (ja) * 1982-10-26 1984-05-01 Toshiba Corp 半導体装置の製造方法
JPS59148360A (ja) * 1983-02-14 1984-08-25 Fujitsu Ltd 半導体記憶装置及びその製造方法
US4679303A (en) * 1983-09-30 1987-07-14 Hughes Aircraft Company Method of fabricating high density MOSFETs with field aligned channel stops
JPS61102750A (ja) * 1984-10-26 1986-05-21 Hamamatsu Photonics Kk 半導体装置
JPS6231177A (ja) * 1985-08-02 1987-02-10 Nec Corp 不揮発性半導体記憶装置
US4737828A (en) * 1986-03-17 1988-04-12 General Electric Company Method for gate electrode fabrication and symmetrical and non-symmetrical self-aligned inlay transistors made therefrom
EP0368097A3 (de) * 1988-11-10 1992-04-29 Texas Instruments Incorporated In den Kreuzungspunkten einer Matrix kontaklos angeordnete Speicher mit schwebendem Gate und eingebetteten Silicid-Bitleitungen
IT1227989B (it) * 1988-12-05 1991-05-20 Sgs Thomson Microelectronics Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione
JPH0775243B2 (ja) * 1989-02-22 1995-08-09 株式会社東芝 半導体装置の製造方法
JPH088313B2 (ja) * 1989-07-25 1996-01-29 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US4968900A (en) * 1989-07-31 1990-11-06 Harris Corporation Programmable speed/power arrangement for integrated devices having logic matrices
IT1236601B (it) * 1989-12-22 1993-03-18 Sgs Thomson Microelectronics Dispositivo a semiconduttore integrato di tipo eprom con connessioni metalliche di source e procedimento per la sua fabbricazione.
US5039625A (en) * 1990-04-27 1991-08-13 Mcnc Maximum areal density recessed oxide isolation (MADROX) process
IT1243303B (it) * 1990-07-24 1994-05-26 Sgs Thomson Microelectronics Schieramento di celle di memoria con linee metalliche di connessione di source e di drain formate sul substrato ed ortogonalmente sovrastate da linee di connessione di gate e procedimento per la sua fabbricazione
US5278438A (en) * 1991-12-19 1994-01-11 North American Philips Corporation Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure
JP2833323B2 (ja) * 1992-02-18 1998-12-09 日本電気株式会社 半導体装置
JPH05299414A (ja) * 1992-04-20 1993-11-12 Sharp Corp 半導体装置における素子分離酸化膜の形成方法
US5350706A (en) * 1992-09-30 1994-09-27 Texas Instruments Incorporated CMOS memory cell array
JP3431198B2 (ja) * 1993-02-26 2003-07-28 株式会社東芝 半導体記憶装置およびその製造方法
US5633187A (en) * 1995-09-22 1997-05-27 United Microelectronics Corporation Process for fabricating read-only memory cells
US5679602A (en) * 1996-01-29 1997-10-21 United Microelectronics Corporation Method of forming MOSFET devices with heavily doped local channel stops
US5763309A (en) * 1996-06-24 1998-06-09 Macronix International Co., Ltd. Self-aligned isolation and planarization process for memory array
US5766992A (en) * 1997-04-11 1998-06-16 Taiwan Semiconductor Manufacturing Company Ltd. Process for integrating a MOSFET device, using silicon nitride spacers and a self-aligned contact structure, with a capacitor structure

Also Published As

Publication number Publication date
KR100310512B1 (ko) 2001-12-15
US5854112A (en) 1998-12-29
KR940022796A (ko) 1994-10-21
DE69431012T2 (de) 2002-11-28
TW299475B (de) 1997-03-01
DE69431012D1 (de) 2002-08-29
EP0618616A2 (de) 1994-10-05
EP0618616B1 (de) 2002-07-24
EP0618616A3 (de) 1997-09-10
JPH06302789A (ja) 1994-10-28

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