KR970018254A - 반도체 장치 제조방법 - Google Patents
반도체 장치 제조방법 Download PDFInfo
- Publication number
- KR970018254A KR970018254A KR1019950031710A KR19950031710A KR970018254A KR 970018254 A KR970018254 A KR 970018254A KR 1019950031710 A KR1019950031710 A KR 1019950031710A KR 19950031710 A KR19950031710 A KR 19950031710A KR 970018254 A KR970018254 A KR 970018254A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- substrate
- film
- semiconductor device
- manufacturing
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract 13
- 238000000034 method Methods 0.000 claims abstract 6
- 239000012535 impurity Substances 0.000 claims abstract 4
- 238000002955 isolation Methods 0.000 claims abstract 4
- 125000006850 spacer group Chemical group 0.000 claims abstract 3
- 230000003064 anti-oxidating effect Effects 0.000 claims abstract 2
- 238000005530 etching Methods 0.000 claims abstract 2
- 230000001590 oxidative effect Effects 0.000 claims abstract 2
- 239000003963 antioxidant agent Substances 0.000 claims 3
- 230000003078 antioxidant effect Effects 0.000 claims 3
- 238000010030 laminating Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자 제조 방법에 있어서;반도체 기판 상에 게이트 절연막 및 게이트 전도막을 차례로 적층한후 패터닝하는 단계;저농도 불순물 접합 영역을 형성하는 단계;전체구조 상부에 예정된 소자분리영역의 반도체 기판이 오픈된 기판산화방지막 패턴을 형성하는 단계;노출된 반도체 기판을 산화시켜 소자분리용 산화막을 형성하는 단계;상기 기판산화방지막 패턴을 전면식각하여 상기 패터닝된 게이트 전도막 측벽에 기판 산화방지막 스페이서를 형성하는 단계;고농도 불순물 접합영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조 방법에 관한 것으로, LOCOS 공정시의 기판산화방지막과 트랜지스터 측벽의 스페이서를 동일한 증착막으로 각각 형성하므로써 공정 단계를 획기적으로 감소시켜 소자의 신뢰도 및 수율증가와 생산성 향상을 가져오는 효과가 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 내지 제ID도는 본 발명의 일실시예에 따른 반도체 소자 제조 공정도
Claims (3)
- 반도체 소자 제조 방법에 있어서;반도체 기판 상에 게이트 절연막 및 게이트 전도막을 차례로 적층한후 피터닝하는 단계;저농도 불순물 접합 영역을 형성하는 단계;전체구조 상부에 예정된 소자분리영역이 반도체 기판이 오픈된 기판산화방지막 패턴을 형성하는 단계;노출된 반도체 기판을 산화시켜 소자분리용 산화막을 형성하는 단계;상기 기판산화방지막 패턴을 전면식각하여 상기 패터닝된 게이트 전도막 측벽에 기판산화방지막 스페이서를 형성하는 단계;고농도 불순물 접합영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.
- 제1항에 있어서, 상기 기판산화방지막은 질화막인 것을 특징으로 하는 반도체 소자 제조 방법.
- 제2항에 있어서, 상기 기판산화방지막 하부에 스트레스 방지용 산화막을 더포함하는 것을 특징으로 하는 반도체 소자 제조 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950031710A KR100201775B1 (ko) | 1995-09-25 | 1995-09-25 | 반도체 장치 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950031710A KR100201775B1 (ko) | 1995-09-25 | 1995-09-25 | 반도체 장치 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970018254A true KR970018254A (ko) | 1997-04-30 |
KR100201775B1 KR100201775B1 (ko) | 1999-06-15 |
Family
ID=19427784
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950031710A KR100201775B1 (ko) | 1995-09-25 | 1995-09-25 | 반도체 장치 제조 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100201775B1 (ko) |
-
1995
- 1995-09-25 KR KR1019950031710A patent/KR100201775B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100201775B1 (ko) | 1999-06-15 |
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