JPWO2008114341A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JPWO2008114341A1 JPWO2008114341A1 JP2009504941A JP2009504941A JPWO2008114341A1 JP WO2008114341 A1 JPWO2008114341 A1 JP WO2008114341A1 JP 2009504941 A JP2009504941 A JP 2009504941A JP 2009504941 A JP2009504941 A JP 2009504941A JP WO2008114341 A1 JPWO2008114341 A1 JP WO2008114341A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000007772 electrode material Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 22
- 229910021332 silicide Inorganic materials 0.000 claims description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 abstract description 12
- 238000005520 cutting process Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 description 15
- 238000002513 implantation Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
(a)半導体基板上に配置される複数のゲート電極パタンと、
(b)前記各ゲート電極の側壁に設けられるサイドウォールスペーサと、
を有し、前記サイドウォールスペーサの厚さは、前記ゲート電極の長辺に沿った側壁において、前記ゲート電極の短辺に沿った側壁よりも厚く構成される、ことを特徴とする。
(a)半導体基板上に、ゲート電極材料膜を成膜し、
(b)前記ゲート電極材料膜を、線状にパタニングし、
(c)前記線状のゲート電極材料膜パタンの長辺に沿ってサイドウォールを形成し、
(d)その後に、前記線状のゲート電極材料膜パタンを所定の箇所で切断して、複数のゲート電極に分断する
工程を含む。
18 活性領域
20 マスク
21 開口
25 ゲート電極
26 ポケット
27 サイドウォールスペーサ
28 ソース・ドレイン
29 薄いサイドウォール
31 シリサイド
Claims (16)
- 半導体基板上に配置される複数のゲート電極パタンと、
前記各ゲート電極の側壁に設けられるサイドウォールスペーサと、
を有し、前記サイドウォールスペーサの厚さは、前記ゲート電極の長辺に沿った側壁において、前記ゲート電極の短辺に沿った側壁よりも厚く構成される
ことを特徴とする半導体装置。 - 前記サイドウォールは、前記複数のゲート電極の長辺に沿って、分離することなく連続して位置する、ことを特徴とする請求項1に記載の半導体装置。
- 前記サイドウォールは、前記複数のゲート電極の長辺にのみ形成されていることを特徴とする請求項1に記載の半導体装置。
- 前記ゲート電極の短辺に沿った側壁には、第1の膜厚のサイドウォールが設けられ、
前記ゲート電極の長辺に沿った側壁には、前記第1の膜厚よりも厚い第2の膜厚を有するサイドウォールが設けられる、
ことを特徴とする請求項1に記載の半導体装置。 - 前記第1のサイドウォールの膜厚は、5nm〜20nmであることを特徴とする請求項4に記載の半導体装置。
- 前記第2のサイドウォールの膜厚は、30nm〜80nmであることを特徴とする請求項4に記載の半導体装置。
- 半導体基板上に、ゲート電極材料膜を成膜し、
前記ゲート電極材料膜を、線状にパタニングし、
前記線状パタンの長辺に沿ってサイドウォールを形成し、
その後に、前記線状のゲート電極材料膜パタンを所定の箇所で切断して、複数のゲート電極に分断する、
工程を含むことを特徴とする半導体装置の製造方法。 - 前記サイドウォールを形成した後であって、前記複数のゲート電極に分断する前に、前記半導体基板に不純物を注入してソース・ドレイン領域を形成する工程、
をさらに含むことを特徴とする請求項7に記載の半導体装置の製造方法。 - 前記ゲート電極の分断工程は、前記線状のゲート電極材料膜パタンと、前記サイドウォールの双方を分断することを特徴とする請求項7又は8に記載の半導体装置の製造方法。
- 前記ゲート電極の分断工程は、前記線状のゲート電極材料膜パタンを分断し、前記サイドウォールは連続した状態で残すことを特徴とする請求項7又は8に記載の半導体装置の製造方法。
- 前記サイドウォール形成前に、前記半導体基板の前記線状のゲート電極材料膜パタンの長辺に沿った領域にポケット領域および/またはエクステンション領域を形成する工程、
をさらに含むことを特徴とする請求項7に記載の半導体装置の製造方法。 - 前記ゲート電極の分断後に、前記サイドウォールの厚さよりも薄い第2のサイドウォールを、分断したゲート電極の短辺および長辺に沿って形成する工程、
をさらに含むことを特徴とする請求項7に記載の半導体装置の製造方法。 - 前記第2のサイドウォールの膜厚は、5nm〜20nmであることを特徴とする請求項12に記載の半導体装置の製造方法。
- 前記第2のサイドウォール形成後に、シリサイド処理を行って、前記分断されたゲート電極上と、前記ソース・ドレイン上に金属シリサイドを形成する工程、
をさらに含むことを特徴とする請求項12又は13に記載の半導体装置の製造方法。 - 前記半導体装置は、SRAMであることを特徴とする請求項7に記載の半導体装置。
- 前記サイドウォールの膜厚は、30nm〜80nmであることを特徴とする請求項7に記載の半導体装置の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/055351 WO2008114341A1 (ja) | 2007-03-16 | 2007-03-16 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
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JPWO2008114341A1 true JPWO2008114341A1 (ja) | 2010-06-24 |
JP5110079B2 JP5110079B2 (ja) | 2012-12-26 |
Family
ID=39765463
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2009504941A Expired - Fee Related JP5110079B2 (ja) | 2007-03-16 | 2007-03-16 | 半導体装置の製造方法 |
Country Status (3)
Country | Link |
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US (3) | US8071448B2 (ja) |
JP (1) | JP5110079B2 (ja) |
WO (1) | WO2008114341A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5525249B2 (ja) * | 2009-12-08 | 2014-06-18 | ラピスセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
TWI552230B (zh) * | 2010-07-15 | 2016-10-01 | 聯華電子股份有限公司 | 金氧半導體電晶體及其製作方法 |
US8610176B2 (en) * | 2011-01-11 | 2013-12-17 | Qualcomm Incorporated | Standard cell architecture using double poly patterning for multi VT devices |
JP5746881B2 (ja) * | 2011-02-22 | 2015-07-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5699826B2 (ja) * | 2011-06-27 | 2015-04-15 | 富士通セミコンダクター株式会社 | レイアウト方法及び半導体装置の製造方法 |
US8735972B2 (en) * | 2011-09-08 | 2014-05-27 | International Business Machines Corporation | SRAM cell having recessed storage node connections and method of fabricating same |
JP5798502B2 (ja) * | 2012-01-31 | 2015-10-21 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US8836040B2 (en) * | 2012-11-07 | 2014-09-16 | Qualcomm Incorporated | Shared-diffusion standard cell architecture |
US9633906B2 (en) * | 2014-01-24 | 2017-04-25 | International Business Machines Corporation | Gate structure cut after formation of epitaxial active regions |
Family Cites Families (19)
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JPS59127866A (ja) * | 1983-01-13 | 1984-07-23 | Toshiba Corp | 半導体装置の製造方法 |
US5217913A (en) | 1988-08-31 | 1993-06-08 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing an MIS device having lightly doped drain structure and conductive sidewall spacers |
JPH0265235A (ja) | 1988-08-31 | 1990-03-05 | Mitsubishi Electric Corp | 半導体集積回路装置 |
JPH0265213A (ja) * | 1988-08-31 | 1990-03-05 | Taiyo Yuden Co Ltd | 還元再酸化型半導体コンデンサ用磁器組成物及び磁器 |
US5146291A (en) | 1988-08-31 | 1992-09-08 | Mitsubishi Denki Kabushiki Kaisha | MIS device having lightly doped drain structure |
US5021354A (en) * | 1989-12-04 | 1991-06-04 | Motorola, Inc. | Process for manufacturing a semiconductor device |
KR0170311B1 (ko) * | 1995-06-23 | 1999-02-01 | 김광호 | 스태틱 랜덤 억세스 메모리 및 그 제조방법 |
JPH09289153A (ja) * | 1996-04-23 | 1997-11-04 | Oki Electric Ind Co Ltd | 半導体装置の製造方法及びそれに用いるマスク |
KR100223832B1 (ko) * | 1996-12-27 | 1999-10-15 | 구본준 | 반도체 소자 및 그 제조방법 |
KR100392153B1 (ko) * | 1998-07-27 | 2003-07-22 | 세이코 엡슨 가부시키가이샤 | 반도체 메모리 장치 및 그 제조 방법 |
JP2000091448A (ja) * | 1998-09-12 | 2000-03-31 | Toshiba Corp | 半導体装置の製造方法 |
TW480735B (en) * | 2001-04-24 | 2002-03-21 | United Microelectronics Corp | Structure and manufacturing method of polysilicon thin film transistor |
AU2002360760A1 (en) * | 2001-12-19 | 2003-07-09 | Advanced Micro Devices, Inc. | Composite spacer liner for improved transistor performance |
JP2004039705A (ja) * | 2002-07-01 | 2004-02-05 | Toshiba Corp | 半導体装置 |
US6936528B2 (en) | 2002-10-17 | 2005-08-30 | Samsung Electronics Co., Ltd. | Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide film |
JP2004140315A (ja) | 2002-10-17 | 2004-05-13 | Samsung Electronics Co Ltd | サリサイド工程を用いる半導体素子の製造方法 |
EP1411146B1 (en) * | 2002-10-17 | 2010-06-09 | Samsung Electronics Co., Ltd. | Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide film |
TW591741B (en) * | 2003-06-09 | 2004-06-11 | Taiwan Semiconductor Mfg | Fabrication method for multiple spacer widths |
US7718482B2 (en) * | 2007-10-10 | 2010-05-18 | Texas Instruments Incorporated | CD gate bias reduction and differential N+ poly doping for CMOS circuits |
-
2007
- 2007-03-16 JP JP2009504941A patent/JP5110079B2/ja not_active Expired - Fee Related
- 2007-03-16 WO PCT/JP2007/055351 patent/WO2008114341A1/ja active Application Filing
-
2009
- 2009-08-19 US US12/543,794 patent/US8071448B2/en active Active
-
2011
- 2011-11-02 US US13/287,770 patent/US8507990B2/en active Active
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2013
- 2013-07-03 US US13/934,759 patent/US8692331B2/en active Active
Also Published As
Publication number | Publication date |
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US8507990B2 (en) | 2013-08-13 |
US8071448B2 (en) | 2011-12-06 |
US20090309141A1 (en) | 2009-12-17 |
JP5110079B2 (ja) | 2012-12-26 |
US8692331B2 (en) | 2014-04-08 |
US20130292749A1 (en) | 2013-11-07 |
US20120043613A1 (en) | 2012-02-23 |
WO2008114341A1 (ja) | 2008-09-25 |
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