JPWO2008114341A1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A method of manufacturing a semiconductor device includes forming a gate electrode material film on a semiconductor substrate, patterning the gate electrode material film in a linear shape, and forming a sidewall along a long side of the linear gate electrode material film pattern. And forming a plurality of gate electrodes by cutting the straight line at a predetermined location.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a gate structure for realizing miniaturization of a MOS type semiconductor device and a manufacturing method thereof.

  As shown in FIG. 1, the SRAM has a gate pattern 15 arranged in a broken line shape so as to extend perpendicularly to the active region 18. In the example of FIG. 1, it has a point-symmetric cell structure, and two transfer transistors and two sets of CMOS inverters are arranged point-symmetrically in a cell 100.

  When miniaturizing the SRAM, as shown by the broken line A, the key is how far the gate protrusion amount B from the active region 18 can be reduced. Here, focusing on, for example, driver transistors in the SRAM of FIG. 1, current problems will be described.

  FIG. 2 is an enlarged view of the region A in FIG. 1 and is a diagram for explaining the receding of the gate tip due to gate etching. Generally, the tip of the gate 25 is retracted from the resist pattern (gate pattern) 15 by an actual gate etching process. For this reason, it is necessary to sufficiently secure the gate protrusion amount B at the time of forming the resist pattern in advance in anticipation of the gate etching retreat amount. As a result, the distance “d” between the active regions 18 also needs to be a value that allows for the amount of recession due to gate etching, which hinders miniaturization of the SRAM element.

  FIG. 3 is a diagram for explaining the receding of the gate tip after gate etching and device defects. When the gate protruding amount B (see FIG. 1) is sufficiently secured, the source and drain are separated by the gate as shown in FIG. If the gate protrusion is insufficient, the gate tip is retracted by polysilicon exposure and etching during patterning, and the gate tip is the active region (see FIG. 3B or 3C). It will not overlap with the source / drain. In particular, in the case of FIG. 3C, the source and drain are not separated by the gate and are short-circuited, and the device is completely defective. In the case of FIG. 3B, the source and drain are separated by the gate and the side wall, but the gate length is different from that of the non-defective product (FIG. 3A). To be judged.

  Here, a driver transistor near the cell boundary has been described as an example, but the same problem can occur with respect to the amount of protrusion of the transfer gate in the cell of FIG.

A technique called gate double patterning has recently attracted attention as a technique for reducing the cell size of the SRAM by suppressing the receding of the tip of the gate etching and reducing the distance “d” between the active regions 18 in FIG. Non-Patent Document 1). In this method, as shown in FIG. 4, first, a long gate pattern in which adjacent gates are connected to each other is formed, and then etching is performed using a mask 20 having an opening 21 for gate separation. Is a technique for separating In this method, the gate tip does not retract, so that the distance “d” between the active regions 18 in FIG. 2 can be reduced.
M. Kanda, et al, "Highly Stable 65 nm Node (CMOS5) 0.56 μm2 SRAM Cell Design for Very Low Operation Voltage", 2003 Symposium on VLSI Technology Digest of Technical Papers, at 13-14

  However, the inventors have found that a problem also occurs in the double patterning of the gate of FIG. As shown in FIG. 5A, when the gate 25 is cut at the last position of the active region (source / drain region) due to the positional deviation at the time of exposure of the gate isolation mask 20, When a device is fabricated according to a normal process, the current characteristic at the gate tip changes.

  For example, as shown in FIG. 5B, oblique implantation in four directions for forming the pocket 26 is performed, and as shown in FIG. 5C, extension implantation is performed to form the sidewall (SW) 27. When the source / drain 17 is formed, the ion implantation characteristics change between the vicinity of the edge along the gate tip and the other region. For this reason, there is a variation in the current characteristic (indicated by arrow b) along the edge of the gate and the current characteristic in the inside (indicated by arrow a).

  The resulting device causes characteristic fluctuations and becomes a cause of failure. In order to avoid this, even when performing double patterning of the gate, the gap “d” between the active regions 18 in FIG. 2 is sufficiently set in consideration of the exposure position deviation margin of the mask for gate separation and the implantation margin. It is necessary to secure it.

  Accordingly, an object of the present invention is to provide a gate structure capable of realizing miniaturization while maintaining stability of device operation characteristics in a cell structure including a MOS type element, and a manufacturing method thereof.

In order to solve the above problems, in a first aspect of the present invention, a semiconductor device includes:
(A) a plurality of gate electrode patterns disposed on the semiconductor substrate;
(B) sidewall spacers provided on the side walls of the gate electrodes;
The sidewall spacer is configured such that a thickness of the sidewall spacer along the long side of the gate electrode is greater than that of the sidewall along the short side of the gate electrode.

  As one configuration example, the sidewalls are continuously located without being separated along the long sides of the plurality of gate electrodes. Or the structure formed only in the long side of these gate electrodes may be sufficient.

  In another configuration example, a sidewall having a first film thickness is provided on the sidewall along the short side of the plurality of gate electrodes, and the sidewall along the long side is thicker than the first film thickness. A structure in which a sidewall having the second film thickness is provided may be employed.

In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided. This manufacturing method is
(A) forming a gate electrode material film on the semiconductor substrate;
(B) patterning the gate electrode material film linearly;
(C) forming a sidewall along the long side of the linear gate electrode material film pattern;
(D) After that, the process includes a step of cutting the linear gate electrode material film pattern at a predetermined location and dividing it into a plurality of gate electrodes.

  Preferably, the method further includes a step of implanting impurities into the semiconductor substrate to form source / drain regions after forming the sidewalls and before dividing into the plurality of gate electrodes.

  In a good manufacturing example, the gate electrode dividing step divides both the linear gate electrode material film pattern and the sidewall. Alternatively, the linear gate electrode material film pattern may be divided and the sidewalls may be left in a continuous state.

  Preferably, the method further includes a step of forming, after the gate electrode is divided, a second sidewall that is thinner than the sidewall along the short side and the long side of the divided gate electrode.

  With the above-described configuration and method, it is possible to prevent variations in impurity characteristics in the substrate region immediately below the gate tip and to shorten the distance between the active regions.

  As a result, the miniaturization of the cell structure of the semiconductor device can be realized and the operation can be stabilized.

It is a mask arrangement diagram of a gate electrode and an active region of a general SRAM. It is a figure for demonstrating receding of the gate front-end | tip part by an etching. It is a figure for demonstrating receding of the gate front-end | tip part after gate etching, and a device defect. It is a figure which shows the method of the well-known gate electrode double patterning. It is a figure for demonstrating the problem of the conventional gate electrode double patterning. It is a figure which shows the basic concept of this invention. It is a manufacturing-process figure of the semiconductor device of one Embodiment of this invention. It is a manufacturing-process figure of the semiconductor device of one Embodiment of this invention. It is a manufacturing-process figure of the semiconductor device of one Embodiment of this invention. It is a manufacturing-process figure of the semiconductor device of one Embodiment of this invention. It is a manufacturing-process figure of the semiconductor device of one Embodiment of this invention. It is a manufacturing-process figure of the semiconductor device of one Embodiment of this invention. It is a figure which shows the modification of the semiconductor device of this invention. It is a figure which shows another modification of the semiconductor device of this invention. It is a figure for demonstrating the effect of this invention.

Explanation of symbols

15 Gate pattern (resist pattern)
18 Active region 20 Mask 21 Opening 25 Gate electrode 26 Pocket 27 Side wall spacer 28 Source / drain 29 Thin side wall 31 Silicide

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, exemplary embodiments of the invention will be described with reference to the drawings. FIG. 6 is a diagram for explaining the basic concept of the present invention. Here, a driver transistor in the region A in FIG. 1 will be described as an example.

  In the present invention, as a method for realizing further miniaturization than the conventional double patterning, first, as shown in FIG. 6A, unlike the conventional method, the gate electrode 25 is etched based on a pattern in which the gate patterns are connected in a straight line. Then, as shown in FIG. 6B, pocket implantation is performed while the gate electrode 25 remains connected to form a pocket region 26. Further, as shown in FIG. 6C, the extension is injected while the gate electrode 25 remains connected to form a side wall spacer (hereinafter simply referred to as “side wall” or “SW”) 27. Then, source / drain implantation is performed to form a source / drain region (hereinafter simply referred to as “source / drain”) 28. Finally, as shown in FIG. 6D, the entire gate is cut after the impurity implantation is completed, and the gate electrode is separated into the designed shape.

  In this method, since the gate electrode 25 and the side wall 27 are finally cut and separated, no impurity is originally implanted into the substrate region where the gate pattern is removed. Therefore, the impurity characteristics directly under the gate electrode tip are not asymmetric. As a result, the operating characteristics are stabilized.

  Further, since the gate is finally cut and separated, unlike the conventional case, the side wall 27 is provided only in the longitudinal direction of the gate (gate width direction), and does not exist between the two opposing driver transistors (gate length direction). (FIG. 6 (d)). Therefore, the distance “d” between the active regions 18 shown in FIG. 2 can be reduced, which can contribute to miniaturization.

  In terms of these configurations, the manufacturing characteristics also apply to the configuration and method for forming the transfer gate and the load gate in the cell of FIG.

  7A to 7F are manufacturing process diagrams of the semiconductor device according to the embodiment of the present invention. Here, as in the region A of FIG. 1, a description will be given taking as an example a driver transistor adjacent in the vicinity of the SRAMM cell boundary.

  First, as shown in FIG. 7A, an element isolation region (not shown) such as STI is formed on a silicon substrate to partition the active region of the SRAM, and well injection, channel injection, activation annealing, gate oxide film deposition, The conventional method is used until the polysilicon film is deposited. In the case of the SRAM cell as shown in FIG. 1, well formation is performed so that a P well, an N well, and a P well are arranged in one cell.

  Thereafter, conventionally, gate patterning is performed using a mask separated into dotted lines in accordance with the SRAM gate pattern as shown in FIG. 1, but in the present invention, the pattern of the gate electrode 25 connected in a straight line as shown in FIG. 7A. Create In the example of FIG. 7A, the upper gate electrode 25 is cut in a later process to become a transfer gate, and the lower gate electrode 25 is cut in a later process to become a driver gate.

  Next, as shown in FIG. 7B, pocket implantation and extension implantation are performed in the same manner as in the prior art. For example, a sidewall 27 having a width of 30 nm to 80 nm is formed by a CVD oxide film, and source / drain implantation is performed. -The drain region 28 is formed.

  Next, as shown in FIG. 7C, a resist (not shown) is applied to the entire surface, and only the gate cut portion is exposed and etched using a mask 20 having a predetermined opening 21. For example, the etching is performed by RIE using a mixed gas containing HBr and oxygen at a pressure of 1 to 100 Pa and a frequency of 13.56 MHz. Further, before applying the resist, for example, a CVD nitride film may be deposited with a thickness of 10 nm to 40 nm as an etching hard mask.

  Next, as shown in FIG. 7D, the resist is removed to obtain a gate structure cut and separated into a predetermined shape. When a hard mask is used in the step of FIG. 7C, the CVD nitride film is removed with phosphoric acid after removing the resist. Thus far, the basic structure of the present invention has been completed. However, depending on the conditions of the subsequent silicide process, the silicide is expected to erode in the lateral direction (gate width direction) from the cut gate end 25a. In that case, silicide erosion from the gate end 25a can be suppressed by performing the following steps.

  That is, as shown in FIG. 7E, after the gate electrode 25 is separated, a thin sidewall 29 having a width of about 5 nm to 20 nm is formed by a CVD oxide film. The thin sidewall 29 covers the gate end 25a of the gate electrode 25 exposed by cutting and separation.

  Finally, as shown in FIG. 7F, silicide processing is performed. A silicide metal such as Ni or Co is sputtered to a film thickness of 2 to 30 nm, primary annealing is performed at a temperature of 200 ° C. to 600 ° C., unreacted metal is removed by acid solution treatment, and then 300 ° C. to 900 ° C. Secondary annealing is performed to form NiSi or CoSi silicide on the gate electrode 25 and the source / drain 28.

  8 and 9 are diagrams showing modifications of the gate structure of the present invention. In FIG. 8, only the gate electrode 25 is cut at the cutting portion 33, and the sidewall 27 is left in a continuous state without being cut. Such a configuration can be realized by controlling the etching conditions of the gate cut portion and the film quality of the sidewall 27 in the step of FIG. 7C. Since the transistor operates properly if the adjacent gate electrodes 25 are electrically insulated by the cut portion 33, an element of this form is also conceivable.

  Further, as shown in FIG. 9, in order to suppress silicide diffusion in the lateral direction of the gate, after the structure shown in FIG. 8 is formed, a thin sidewall 29 is formed to cover the gate end face and then silicided.

  In any configuration, regarding the sidewall configuration provided on the sidewall of the gate electrode 25, the sidewall along the long side of the gate (in the gate width direction) is more than the sidewall along the short side of the gate (in the gate length direction). It will have a thick sidewall.

  FIG. 10 is a diagram for explaining the effect of miniaturization of the present invention. If the amount of pocket implantation and extension implantation entering the gate electrode as a mask is estimated to be about 10 nm, the amount of protrusion after gate etching can be used to create a stable device even with the usual dub patterning method shown in FIGS. Requires a margin of (exposure misalignment margin) +10 nm. However, according to the present invention, since there is no amount of pocket injection and extension injection from the gate end 25a, the amount of protrusion after gate etching can be reduced by 10 nm to produce a device having the same performance.

The effect when the configuration of the present invention is applied to a 45 nm node SRAM is estimated. For example, it is assumed that a cell having an X direction of 760 nm and a Y direction of 340 nm (area is 0.2584 μm ² ) is created by using a gate double patterning method. Here, when the configuration of the present invention is used, a, b, c, and d in FIG. 10 can be reduced by 10 nm, the X direction is 720 nm, the Y direction is 340 nm, the area is 0.2448 μm ² , and the area is about 5%. Reduction is possible.

If applying this configuration SRAM of 32nm node, reference X-direction 530 nm, Y-direction 240 nm, the conventional structure of the area 0.1272Myuemu ^2, X-direction 490 nm, Y-direction 240 nm, the area 0.1176Myuemu ² becomes about The area can be reduced by 8%.

  Although the present invention has been described based on the preferred embodiments, the present invention is not limited thereto, and various modifications and changes can be made by those skilled in the art within the scope of the claims.

Claims (16)

A plurality of gate electrode patterns disposed on a semiconductor substrate;
A sidewall spacer provided on a sidewall of each gate electrode;
The sidewall spacer is configured such that the sidewall spacer is thicker on the side wall along the longer side of the gate electrode than on the side wall along the shorter side of the gate electrode.   2. The semiconductor device according to claim 1, wherein the sidewall is continuously located without being separated along a long side of the plurality of gate electrodes.   The semiconductor device according to claim 1, wherein the sidewall is formed only on long sides of the plurality of gate electrodes. A sidewall having a first film thickness is provided on the sidewall along the short side of the gate electrode,
A sidewall having a second film thickness larger than the first film thickness is provided on the sidewall along the long side of the gate electrode.
The semiconductor device according to claim 1.   The semiconductor device according to claim 4, wherein a film thickness of the first sidewall is 5 nm to 20 nm.   The semiconductor device according to claim 4, wherein a film thickness of the second sidewall is 30 nm to 80 nm. A gate electrode material film is formed on a semiconductor substrate,
The gate electrode material film is patterned in a linear shape,
Forming a sidewall along the long side of the linear pattern;
Thereafter, the linear gate electrode material film pattern is cut at a predetermined location to be divided into a plurality of gate electrodes.
The manufacturing method of the semiconductor device characterized by including a process. A step of forming a source / drain region by implanting impurities into the semiconductor substrate after forming the sidewalls and before dividing into the plurality of gate electrodes;
The method of manufacturing a semiconductor device according to claim 7, further comprising:   9. The method of manufacturing a semiconductor device according to claim 7, wherein the step of dividing the gate electrode divides both the linear gate electrode material film pattern and the sidewall.   9. The method of manufacturing a semiconductor device according to claim 7, wherein the step of dividing the gate electrode divides the linear gate electrode material film pattern and leaves the sidewalls in a continuous state. Forming a pocket region and / or an extension region in a region along the long side of the linear gate electrode material film pattern of the semiconductor substrate before forming the sidewall;
The method of manufacturing a semiconductor device according to claim 7, further comprising: Forming a second side wall that is thinner than the side wall after dividing the gate electrode along the short side and the long side of the divided gate electrode;
The method of manufacturing a semiconductor device according to claim 7, further comprising:   The method of manufacturing a semiconductor device according to claim 12, wherein a film thickness of the second sidewall is 5 nm to 20 nm. A step of performing a silicide treatment after forming the second sidewall to form a metal silicide on the divided gate electrode and on the source / drain;
The method of manufacturing a semiconductor device according to claim 12, further comprising:   The semiconductor device according to claim 7, wherein the semiconductor device is an SRAM.   The method of manufacturing a semiconductor device according to claim 7, wherein the sidewall has a thickness of 30 nm to 80 nm.

Images