JPS59127866A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form polysilicon wirings on a stepped difference without a mutual short circuit, and to form an MOSFET, in which a gate-fringe in the direction of gate width is shortened largely, by simultaneously etching and removing the left section of a conduction film at the stepped difference section, where at least adjacent wirings are short-circuited, and the gate-fringe of the MOSFET by using a one-time mask alignment process. CONSTITUTION:Only the direction of gate width of second layer polysilicon 205 forming a transistor for switching is brought to a patterned state. The left section of the second layer polysilicon is generated at the stepped difference section in the vicinity of first polysilicon 203, and adjacent wirings 205 and 205' are short-circuited. A photo-resist 213 on the second polysilicon 205 is removed under the state, and source-drain regions are formed through ion implantation or diffusion. The whole surface is coated with a photo-resist 230, and an opening section 231 is formed. Polysilicon in the gate-fringe section of the transistor and the left section 216 of polysilicon left and the stepped difference section are removed through an RIE.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for forming a gate electrode pattern of a wiring on a surface having a step or (dl, MO8% field effect transistor). Regarding improvement of gate fringe length.

[Prior art and its problems]

Rear! Directional etching techniques such as tip ion etching (R,IE) and sputtering etching have become widely used. The feature of this directional etching is that there is almost no side etching, so it is possible to pattern accurately according to the mask pattern.
There was a problem that the material to be etched remained.

For example, as in MO8 type dynamic memory, this is achieved by overlapping two or more layers of polysilicon.
This has become a particularly serious issue for semiconductor devices with structures that can be used as electrodes.

In addition, MO8 field effect transistor (hereinafter referred to as MO8FE)
(abbreviated as T), it was conventionally necessary to provide a gate fringe.

One reason for this is that when patterning the gate electrode,
The resist is not cut in a straight line, but is cut unevenly by the wavelength of the light. In particular, the ends of the gate electrode in the gate width direction become frozen, as shown in Figure 1, so the gate length is cut at both ends in the gate width direction. This is because it becomes shorter.

Another problem is that after patterning the gate electrode, the source/drain regions of the MOSFET are formed by diffusion, ion implantation, etc. using the gate electrode as a mask, so if there is misalignment of the mask, This is because, as shown in FIG. 2, the source region and the drain region may be confused.

For the above reasons, conventionally, the gate length of MOSFET is 1.
For 5 μm, this gate fringe should be at least 1.
It is necessary to set the thickness to 5 μm, and it is also necessary to provide a distance between the gate fringe or between the gate fringe and the wiring electrode in the same layer.

Furthermore, when the gate length is made shorter than 1.5 μm, the gate fringe needs to be longer than the gate length.

Furthermore, as higher integration progresses, in particular, the gate fringe of MOSFET forming memory cells is
There is a problem in that it limits the position of cells and, furthermore, the cell size.

The above-mentioned problems will be explained using the well-known method of manufacturing Dynamic-I (AM cell) as an example.

FIG. 3(a) is a plan view showing an example of a dynamic memory cell section using three-layer polysilicon, and FIG. 3(b) is a plan view showing an example of a dynamic memory cell section using three-layer polysilicon.
A cross section at AA/ is shown. Reference numeral 101 is the boundary between the field oxide film 102 and the element region, and the area surrounded by the four lines (101) is the element region. 100 is an 8i board.

103 is the first layer of polysilicon, which is the gate oxide film 1
04 is the t' pole for forming a memory capacitor with the silicon substrate (100).

Reference numeral 105 denotes a gate electrode wiring for switching of each memory cell formed of the second layer of polysilicon, and is formed so as to partially overlap the first layer of polysilicon (103). Reference numeral 106 is a contact hole, through which information in the memory cell is transferred to the third layer of polysilicon via the pins)/I(1
07) to the sense amplifier (Fig. 3(a)
The bit holes of the third layer of polysilicon are not drawn in t). 108 is a contact hole, and the AII word @ (109) is the second layer of polysilicon (1
05) and 108.

Now, the cross-sectional shapes of the portions indicated by circles 110 and 111 in FIG. 3(a) are shown in FIG. 3(C), (d), (e), and (f), respectively. Explain the problems involved.

(C) (e) is a cross section at (110) in FIG. 3(a), and (d) and (f) are cross sections at (111).

FIGS. 3(e) and 3(d) show 8i0. A second polysilicon film (10
This shows a state in which, for example, 3000A is formed. Part 11
The area 111 is covered with phytoresist, but the area 111 is not covered. In this state, the wafer is
Use a gas or expose to an etching atmosphere during active ion etching. The resulting structure is shown in Figure 3 (e
) (f).

In the strong portion covered with resist, the polysilicon in the flat portion (114) is completely removed, but the side wall portion 1 of the stepped portion is completely removed.
15, a polysilicon residue 116 is formed.

As shown in the plan view of FIG. 3(a), the remaining polysilicon (11) will seal the adjacent wiring (105) (105'). This is because the thickness becomes thicker, and in order to completely remove this remaining polysilicon, it is necessary to perform over-etching of 100% or more.When over-etching in this way, the oxide film is destroyed and the silicon that should become the diffusion layer is removed. Substrate surface (11D
There were serious problems such as non-uniform etching of the resist, increasing junction leakage, and resist (113) on the wiring being damaged, making the wiring thinner.

In addition, especially when there is an overhang as shown in FIG. 3(g), there is a problem that no matter how much overetching is added, there will always be a portion 116 left behind.

Furthermore, if we pay attention to the switching transistor part (118) of the memory cell surrounded by the dotted line in FIG. 3(a), the shape of the second polysilicon (105), which is the gate electrode, is actually In this case, the gate fringe becomes rounded, as shown by the thick line in FIG. 3(h). At this time, taking into account misalignment of masks, etc., a gate fringe that is approximately equal to or longer than the transistor width W is required by the fringe length -t'f. (d is the minimum dimension between gate electrodes) [Object of the Invention] This invention has been made in view of the above-mentioned matters in 1d of the present invention, and is a highly accurate patterning method and an effective M
OSFET f is to be provided.

[Summary of the invention]

The present invention uses a mask with a predetermined shape to remove a conductive film on a surface with steps, and after removing the conductive film in the gate length direction only in the gate length direction of the MOS transistor, the source and drain regions of the MOS transistor are etched by diffusion and ion implantation. After that, the conductive film is removed at the stepped portion where the adjacent wiring is short-circuited, and the gate fringe in the gate width direction of the MOS transistor is simultaneously etched using a single mask alignment process. and removing it.

〔Effect of the invention〕

According to the present invention, the polysilicon remaining on the step and the gate fringe of the MOS transistor can be simultaneously etched with two mask alignments while maintaining the batting accuracy and without deteriorating the device characteristics. The polysilicon wiring on the steps can be formed without shorting each other, and the gate fringe can be significantly reduced.
It is very possible to form O8F'ET.

As a result, a margin is provided between the gate fringe or between the gate fringe and the wiring electrode in the same layer, and the rule of pattern design using the gate fringe becomes h. Therefore, unlike the current transistors with long gate fringe, transistors with short gate fringe can be expected to achieve higher integration.

By reducing the area of the gate fringe on the field region, the stray capacitance of the gate electrode is reduced, the time required for switching the gate voltage is shortened, and the MOSFET can operate at higher speeds.

Furthermore, the weak reversal region on the field area is reduced, and the leakage current due to the weak reversal is reduced.

According to the present invention, by patterning one pole on the gate twice in the gate length direction and gate width direction, the gate electrode in the gate width direction is not rounded, and the gate length is 9 mm.
SFET was obtained, and the transistor characteristics with little variation were expected.

[Embodiments of the invention]

An embodiment of the present invention will be described using FIG. 4.

Figure 4(a) shows that only the gate width direction of the second layer of polysilicon (20) forming the switching transistor has been patterned, and the gate fringe of each transistor is similar to that of the adjacent transistor. Transistor gate
It is connected to the fringe, and the other parts show the same state as in FIG. 3 (a3), and cross-sectional views at (210) and (211) are shown in FIG. 4 (b) and (C).

That is, in the stepped portion around the first polysilicon (203),
The second layer of polysilicon is left behind and the adjacent wiring (2
0 and (205 ri).

In this state, after removing the photoresist (213) on the second polysilicon (205), the source is removed by ion implantation or diffusion using the second polysilicon as a mask.
Form a drain region. Thereafter, the entire surface is again coated with photoresist (230), and, for example, openings (231) shown by dotted lines are provided. Next, by RIE, the polysilicon in the gate fringe portion of the transistor and the large portions 216) of the polysilicon left in the step portion are removed. The polysilicon left on the step part was subjected to R twice.
Although most of the parts have been removed by IE, there is an overhang in the stepped part.
Isotropic etching is performed to completely remove the polysilicon (216) at the stepped portion so as not to affect the three portions.

Additionally, as shown in the plan view in FIG. 4(f), the two wirings (205) (205') are electrically insulated from each other, and the gate fringe of the transistor is also shortened.

The above embodiments have been explained using dynamic law A as an example, but devices having two or more layers of polysilicon, such as EPROM, I? i 1 P) 1,0 times the other one hurts. It can also be applied to devices. Furthermore, even if the device uses only one layer of polysilicon, it may be used in any device that has a step on its surface and leaves only four layers of space remaining at the step. Further, it may be used in any case where the gate fringe is close to each other or when the gate fringe and the electrode wiring of the same layer are close to each other.

Furthermore, the present invention can be applied in exactly the same way to wiring or electrodes made not only of polysilicon but also of silicide or other metals such as A or W 1Mo f'r.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the gate fringe of a conventional MOSFET, and FIG. 2 is a plan view showing a short circuit between the source region and the drain region caused by mask misalignment when the gate fringe is not provided. Fig. 3(a) is a plan view illustrating the conventional example, and Fig. 3(b) is A, -A in Fig. 3(a).
4 shows an embodiment of the present invention. It is a diagram. In the figure, 1... Contact, 2... Element region, 3... Source train, 4... Wiring electrode, 5... Gate electrode, 6... Gate fringe, 7... Gate electrode on mask, 8... source, drain short-circuit part. 1 patent attorney Noriyuki Chika (1 other person) (12) Figure 4 Figure 4<f)

Claims (1)

[Claims] After forming a conductive film having a wiring or a conductive film of %iJf of an MO8 field effect transistor on the surface of the insulating film having a step, forming a mask material for etching on the conductive film in a predetermined shape; Use this mask material as a mask,
etching away the conductive film by directional ion etching to at least the thickness of the flat portion or more;
Moreover, the step of leaving the conductive film on the side wall of the stepped portion and the gate width direction of the gate electrode, and then patterning only the gate length direction of the MOS transistor. Using the film as a mask, a step of forming a lease/drain region, and then a mask alignment step are used to form the conductive film left on the side wall portion existing between adjacent wirings or electrodes and the MO8). 1. A method of manufacturing a semiconductor device, comprising the step of etching and removing the conductive film remaining on the gate fringe portion in the gate width direction of the transistor using the same mask.