JPWO2006068082A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2006068082A1 JPWO2006068082A1 JP2006548967A JP2006548967A JPWO2006068082A1 JP WO2006068082 A1 JPWO2006068082 A1 JP WO2006068082A1 JP 2006548967 A JP2006548967 A JP 2006548967A JP 2006548967 A JP2006548967 A JP 2006548967A JP WO2006068082 A1 JPWO2006068082 A1 JP WO2006068082A1
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- variable resistance
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Abstract
Description
図1は、本実施の形態1に係る半導体装置100の構成を示す断面図である。本実施の形態1に係る半導体装置100は、半導体チップの一種であるIGBT(Insulated Gate Bipolar Transistor)チップ24に、PTC(Positive Temperature Coefficient)素子(PTC温度センサ)9が接合されている。
図12は、本実施の形態2に係る半導体装置100のPTC素子9近傍の構成を示す断面図である。
実施の形態1ではPTC素子9の銅箔電極11a,11bとIGBTチップ24間に金バンプ14を使用したが(図10参照)、金バンプ14を使用せず銅箔電極11a,11bとIGBTチップ24表面を超音波併用熱圧着方式で直接接合してもよい。あるいは金バンプ14の代わりにAlバンプを使用してもよい。
本実施の形態4に係る半導体装置100では、図1に示したPTC素子9の銅箔電極11a,11bとIGBTチップ24間の接合に低融点半田を用いている。
本実施の形態5に係る半導体装置100では、図1に示したPTC素子9の銅箔電極11a,11bとIGBTチップ24との接合に導電性ペーストを使用する。
本実施の形態6に係る半導体装置100は、図1に示したPTC素子9のPTC素材12として、BaTiO3を主材料にした無機系の材料を使用したものである。Baを+3価のLa,Ce,Pr,Nd,Sm,Gd,Hoなどで置換するか、Tiを+5価のNb,Ta,Sb,Biで置換すると、電子あるいはホールができ半導体となる。キュリー点を超えると、結晶粒界のみが絶縁化し、抵抗率が高くなり、PTCが発現する。抵抗率が急上昇する温度を制御する方法として、Baを+2価のMg,Ca,Sr,Pbなどで置換するか、Tiを+4価のHf,Sn,Zrなどで置換するとキュリー点が移動し、それに応じたPTC特性が得られる。
本実施の形態7に係る半導体装置100は、図1に示したPTC素子9の銅箔電極11a,11bと半導体チップ間の接合に導電性ろう材を使用している。
図13は、本実施の形態8に係る半導体装置800の構成を示す断面図である。本実施の形態8に係る半導体装置800は、PTC素子9に代えてNTC(Negative Temperature Coefficient)素子(NTC温度センサ)210を用いている。NTC素子210は、温度に応じて抵抗値が変化し、負の温度係数を有する可変抵抗素子である。また、IGBTチップ24部分の構成は、図2に示した構成と同様である。
Claims (13)
- エミッタ側主電極(8、410)及びコレクタ側主電極(10)を有する半導体チップ(24)と、
前記エミッタ側主電極(8、410)上に接合され、温度に応じて抵抗値が変化する可変抵抗素子(9;210)と、
を備え、
前記可変抵抗素子(9;210)は、
前記可変抵抗素子(9;210)の表面もしくは内部の少なくとも一部に形成された第1電極(11a;211a)と、
前記可変抵抗素子の表面もしくは内部の前記第1電極以外の少なくとも一部に形成された第2電極(11b;211b)と、
を備えることを特徴とする半導体装置。 - 前記可変抵抗素子(9;210)は、超音波併用熱圧着方式により接合されたことを特徴とする請求項1に記載の半導体装置。
- 前記可変抵抗素子(9;210)は、導電性ろう材により接合されたことを特徴とする請求項1に記載の半導体装置。
- 前記可変抵抗素子(9;210)は、前記可変抵抗素子(9;210)が融解する融点よりも低い温度の融点を備える低融点半田により接合されたことを特徴とする請求項1に記載の半導体装置。
- 前記可変抵抗素子(9;210)は、導電性ペーストにより接合されたことを特徴とする請求項1に記載の半導体装置。
- 前記可変抵抗素子(9;210)は、前記半導体チップ(24)表面に作成したNi面を介して前記半導体チップ(24)に半田接合されたことを特徴とする請求項1に記載の半導体装置。
- 前記可変抵抗素子(9;210)を覆うように形成された保護膜(15)をさらに備えることを特徴とする請求項1に記載の半導体装置。
- 前記可変抵抗素子(9;210)は、前記半導体チップ(24)主面の中央部に配置されたことを特徴とする請求項1に記載の半導体装置。
- 前記可変抵抗素子(9)は、正の温度係数を有する素子であることを特徴とする請求項1から8の何れかに記載の半導体装置。
- 前記可変抵抗素子(9)は、
前記第1電極(11a)及び前記第2電極間(11b)に挟まれて形成された可変抵抗素材(12)をさらに備え、
前記可変抵抗素材(12)の膜厚は、0.1mm以上、0.37mm以下であることを特徴とする請求項9に記載の半導体装置。 - 前記可変抵抗素子(210)は、負の温度係数を有する素子であることを特徴とする請求項1から8の何れかに記載の半導体装置。
- 前記可変抵抗素子(210)は、
前記第1電極(211a)及び前記第2電極(211b)間に挟まれた可変抵抗素材(220)をさらに備え、
前記可変抵抗素材(220)の膜厚は、0.1mm以上、0.5mm以下であることを特徴とする請求項11に記載の半導体装置。 - 前記可変抵抗素材(220)の膜厚は、0.1mm以上、0.3mm以下であることを特徴とする請求項12に記載の半導体装置。
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