1249750 九、發明說明 【發明所屬之技術領域】 I特別是有 本發明是㈣於―種電子元件之電阻排組， ;種包3熱敏電阻之厚帛式熱敏電阻排組。 【先前技術】 熱敏電阻係一種含有金屬(鐵、鋁、銅、鈦 思1、錄）氧化物的㈣燒結半導體㈣。其中熱、= 阻值會隨溫度變化 …、 ^。在實際運用上’則是利用熱敏電 阻的電阻-溫度之關係，結合其他被動元件，例如電阻，Π 作：電子線路和儀錶測量電路中的溫度補償、電路保護、溫 又里測或'皿度控制之裝置。習知的熱敏電阻可以製造成珠 (Bead)狀、碟狀、桿狀、晶片或薄片結構，再藉由電極連結於 電子電路之上。 明參照第1圖，第丨圖係根據習知的溫度補償技術所繪 不之溫度補償電路模型之電阻排組示意圖。電路模型中，電 阻 R1 係係一正溫度係數（Positive c〇efficient; ptc )熱敏電阻，而電阻R2、電阻R3、電阻R4、電阻R5、 電阻R6、電阻R7、電阻R8、電阻R9係預設電阻值之電阻。 在未裝置溫度補償電路模型（未繪示）中，二極體D的載頻會受 /BZL度影響’當溫度升咼時頻率會變低而影響實際操作之效 能。而在裝置有溫度補償電路模型中，當溫度升高熱敏電阻 R1阻值變大，由熱敏電阻R1、電阻R2以及電阻R3所組成 的串並聯電阻排組的電阻值會變大；當溫度降低時，由熱敏電 1249750 一電阻R2)以及電阻R3所組成的串並聯電阻排組的電阻 值會阻值變小，藉由電壓的控制可以達到準確的溫度補償效 果，以消除二極體D的載頻因溫度而產生的偏移。 “ ^而，由於習知電阻排組所使用的熱敏電阻與其他預設 電\白外接於電子電路之上，並不符合半導體電子零件產業 小型化的需求。再加上，熱敏電阻與其他預設電阻會因為沒 有，於同一基材之上，或兩個電阻之間距離過遠，使得作用 於每個電阻的熱效應並不一致，電阻阻值受溫度所產生的 =率也有所差異’因而造成熱敏電阻無法有效地提供正確 的溫度補償。 因 片，使 的問題 此有需要提供-種可共溫的厚膜式熱敏電阻排組晶 電阻排組之熱效應一致，避免造成電阻值差異所造成 發明内容 予此本發明的目的就是在提供—種熱敏電阻晶片，整合 員叹電阻與熱敏電阻於同一基 t^, 啊心上精以縮小電阻排組之 位置不：而ίΓ電阻排組一個共溫基礎，解決電阻因所在 …二差異，進而改進造成電阻排組中不同電 <間存在電阻值變異的問題。 在本發明的較佳實施例之中，厚膜式埶 由電性絕緣基材以及電阻排組所組成。其;、，】曰曰片係 至少==、至少一個具有預設電阻值之電阻、以及 、敏電阻所組成。圖案化導電層覆蓋於電性絕緣 6 1249750 基材上；該至少一個預設電阻與圖案化 結;而該至少-個熱敏電阻與圖案化導電二二相：電性連 層相互電性連結。 根據本發明之另一目❸，是提出 造方法。 裡…、敏電阻晶片的製1249750 IX. Description of the invention [Technical field to which the invention pertains] I particularly has the present invention which is (d) a resistor bank of a type of electronic component, and a thick tantalum thermistor bank of a type 3 thermistor. [Prior Art] A thermistor is a (four) sintered semiconductor (IV) containing a metal (iron, aluminum, copper, titanium, and oxide) oxide. Among them, heat, = resistance will change with temperature ..., ^. In practical use, it is based on the resistance-temperature relationship of the thermistor, combined with other passive components, such as resistors, :: temperature compensation in electronic circuit and meter measurement circuits, circuit protection, temperature and measurement, or Degree control device. Conventional thermistors can be fabricated in a Bead-like, dish-like, rod-like, wafer or sheet structure and bonded to an electronic circuit by electrodes. Referring to Figure 1, the second diagram is a schematic diagram of the resistor bank arrangement of the temperature compensation circuit model according to the conventional temperature compensation technique. In the circuit model, the resistor R1 is a positive temperature coefficient (Positive c〇efficient; ptc) thermistor, and the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7, the resistor R8, and the resistor R9 are pre- Set the resistance of the resistance value. In the un-temperature compensated circuit model (not shown), the carrier frequency of the diode D is affected by the /BZL degree. When the temperature rises, the frequency becomes lower, which affects the actual operation. In the temperature compensation circuit model of the device, when the temperature rises, the resistance value of the thermistor R1 becomes larger, and the resistance value of the series-parallel resistance row group composed of the thermistor R1, the resistor R2 and the resistor R3 becomes larger; When the voltage is reduced, the resistance value of the series-parallel resistance group consisting of the thermoelectric 1249750-resistor R2) and the resistor R3 will become smaller, and the voltage compensation can achieve accurate temperature compensation to eliminate the diode. The carrier frequency of D is offset by temperature. "^And, because the thermistors used in the conventional resistor array and other presets are externally connected to the electronic circuit, it does not meet the needs of the miniaturization of the semiconductor electronic parts industry. Plus, the thermistor and Other preset resistors may be on the same substrate, or the distance between the two resistors is too far, so that the thermal effects acting on each resistor are inconsistent, and the resistance value of the resistor is also different depending on the temperature. Therefore, the thermistor cannot effectively provide the correct temperature compensation. Due to the problem of the chip, it is necessary to provide a uniform temperature effect of the thick film type thermistor row resistor row group which can be co-temperature, avoiding the resistance value. SUMMARY OF THE INVENTION The object of the present invention is to provide a thermistor wafer, the integration of the sigh resistor and the thermistor in the same base t ^, ah heart to narrow the position of the resistor row is not: and Γ The resistor row is a common temperature base, which solves the problem that the resistance is caused by the difference between the two, and thus the variation of the resistance value caused by different electric charges in the resistor row group. In the embodiment, the thick film type crucible is composed of an electrically insulating substrate and a resistor row group. The film is at least ==, at least one resistor having a predetermined resistance value, and a resistance resistor. The patterned conductive layer covers the electrically insulating 6 1249750 substrate; the at least one predetermined resistor and the patterned junction; and the at least one thermistor and the patterned conductive two-phase: electrically connected to each other According to another aspect of the present invention, a method for manufacturing is proposed.
、電性絶緣基材之上形成一個圖案化導電層；再 於“性絕緣基材之上形成一個預設阻值之預設電阻曰 設電阻層與導電層相· 曰，使預 上再形成-個熱敏電阻Γ，ί;:_ί阻 相互電性連結。 mu層與圖案化導電層 八曰依據以上所述之較佳實施例本發明確實可以藉由單一整 合晶片提供熱敏電阻排組一個共溫環境，以解決電阻溫产差 異所造成溫度補償不準確的問題，並且可提供熱敏電：：組 微小化的電路尺寸，達成以上所述之發明目的。 Φ 【實施方式】 藉由本發明的較佳實施例，可提供一個電路尺寸較小的 熱敏電阻排組晶片，並藉由熱敏電阻晶片之基材提供熱敏電 •阻排組一個共溫環境，藉以解決電阻之間因為不同位置的溫 度差異所造成的溫度補償誤差。 請參照第2a圖與第2b圖，第2a圖與第2b圖係分別依 照本發明之一些較佳實施例所繪示之熱敏電阻晶片的電路示 意圖。在本發明的一些較佳實施例之中，厚膜式熱敏電阻晶 片係由電性絕緣基材200以及電阻排組2〇 1所组成。電阻排 1249750 組201係由圖案化導電層2〇2、預設電阻2〇4、以及熱敏電阻 206所組成（如第2a圖所繪示）。其中，圖案化導電f 2〇2係 覆蓋於電性絕緣基# 200上之導電線路。具有一預設電阻值 之預》又電阻204 ’電性連結於導電線路（圖案化導電層加）之 上，熱敏電阻206與導電線路（圖案化導電層搬）形成電性 結。 在本發明的另一此較去眘# ;丨*山 , 一罕又隹實轭例之中，具有一預設電阻值 之預設電阻204，電性遠蛀认增+ m h 、、、。於導電線路（圖案化導電層202)之 上，熱敏電阻206與導電線路（圖案化導電層2叫接觸，並且 藉由電線路（圖案化導電層？ 層202)與預设電阻204形成電性連Forming a patterned conductive layer on the electrically insulating substrate; forming a predetermined resistance of the predetermined resistance on the "insulating insulating substrate" and setting the resistive layer and the conductive layer to form a pre-formed - Thermistor Γ, ί;: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ A co-temperature environment to solve the problem of inaccurate temperature compensation caused by the difference in resistance temperature and temperature, and can provide the thermistor: the miniaturized circuit size of the group to achieve the above-mentioned object of the invention. Φ [Embodiment] In a preferred embodiment of the invention, a thermistor array chip having a small circuit size can be provided, and a thermosensitive circuit is provided by a substrate of the thermistor chip to provide a common temperature environment, thereby solving the relationship between the resistors. Temperature compensation error caused by temperature difference at different positions. Please refer to Figures 2a and 2b. Figures 2a and 2b are thermistor chips respectively according to some preferred embodiments of the present invention. In some preferred embodiments of the present invention, the thick film thermistor wafer is composed of an electrically insulating substrate 200 and a resistor bank 2〇1. The resistor row 1249750 is composed of patterned conductive The layer 2〇2, the preset resistor 2〇4, and the thermistor 206 are formed (as shown in FIG. 2a), wherein the patterned conductive f 2〇2 is electrically conductive on the electrical insulating base # 200 The circuit has a predetermined resistance value and the resistor 204' is electrically connected to the conductive line (patterned conductive layer plus), and the thermistor 206 forms an electrical junction with the conductive line (patterned conductive layer). In another example of the present invention, the yoke is a preset resistor 204 having a predetermined resistance value, and the electrical power is increased by + mh , , , . Above the conductive line (patterned conductive layer 202), the thermistor 206 is in contact with the conductive line (the patterned conductive layer 2 is contacted, and is electrically formed by the electrical line (patterned conductive layer? 202) and the predetermined resistor 204). Sexual connection
結。其中，熱敏電阻206伤w虫η絲λα + L ’、乂串聯的方式與預設電阻2〇4b相 互電性連結。在本發明的另外一 力卜些實施例之中，熱敏電阻206 係以並聯的方式與預設雷阳9 办一、 又電阻2〇4a相互電性連結（如第2b圖所 緣不）。 ’Knot. The thermistor 206 is in electrical connection with the preset resistor 2〇4b in such a manner that the tantalum λα + L ’ and the tantalum are connected in series. In another embodiment of the present invention, the thermistor 206 is electrically connected to the preset Leiyang 9 and the resistor 2〇4a in parallel (as shown in FIG. 2b). . ’
請參照第3圖，第3 FI 圖係依照本發明另一此較佳實 所繪示之熱敏電阻晶片之雷阳^ —奴佳貫施例 “一·， 電阻排、组的電路示意圖。在本發明 的另 貝施例之中，位於電性絕续苴从， y 、緣基材3 〇 〇上的熱敏電阻Μ 組3 01係由複數個熱敏電阻 3〇6h，、0 % # …、敏電阻306a及熱敏電阻 3 06b 以及複數個預設電阻，也丨上 304b , . 例如預設電阻304a及預設電阻 …H、並％、或並聯_串聯 各個電阻之間分別都相距有 才以生連、、、。，且 預設電阻304a係以串聯方式如χ + .、、、敏冤阻306a與 預mww, Γ 電性連結；熱敏電阻鳩與 預5又電阻304b係以並聯方式相 熱敏電阻306a與預設電阻^生；^ ;熱敏電阻、 係以並聯-牟聯方式相互電性 1249750 連、、、口。在本發明的其他實施例 μ雷阳中由圖案化導電層302、預 口又電阻304、以及熱敏電阻3〇 ..^ ^ 6所組成之電阻排組的配置方 式，係依據電阻排組之功能靈卡 刀月b而求，電阻特性例如、熱敏電阻 —電阻值曲線、預設電阻之熱偏移效應，加以設計編排。 值=主意的{，當電阻排組3〇1具有兩個以上之熱敏電 L:，其中至少會有一對熱敏電阻，例如熱敏電阻鳩與孰 敏電阻306a具有不同之埶成庫孫 …级應係數。例如，在本發明的一些 實知例之中，熱敏電阻306b與熱敏電阻編分別有不同之 ::感應曲線。在本發明的另一些實施例之中，熱敏電阻難 與熱敏電阻306a分別為正溫度係數血 又你数興負，皿度係數之熱敏電 。在本發明的又一些實施例之中，熱敏電阻3鳴盘孰敏電 阻场的熱傳導距離不同，例如熱敏電阻3〇6a之上包：一層 例如樹脂材質，而熱敏電阻306b裸露於外。 請參照第4圖’第4圖係依照本發明又—較佳實施例所 =之熱敏電阻晶片的剖面示意圖。在本發明的較佳實施例 ’圖案化導電層4G2係形成並覆蓋於電性絕緣基材· 之上，圖案化導電層4〇2具有複數個開口，例如開口 4〇3a與 開口 403b，藉以將電性絕緣基材4〇〇暴露出來。 在本發明的較佳實施例之中，預設電阻係與圖案化 =互電性連結。在本實施例之中，一部份預設電阻心位 於電性絕緣基材400之上，圖案化導電層4〇2的開口仂“之 中，與圖案化導電層402相互電性連結。另外一 ^ 電阻404b位於圖案化導電層4〇2之上’與圖案化導電声術 相互電性連結。 曰 1249750 在本發明的較佳實施例之中，熱敏電阻則與圖案化導電 層接觸，且藉由圖案化導電層與預設電阻相互電性連結。在 本實施例之中，一部份熱敏電阻406a位於電性絕緣基材4〇〇 之上，圖案化導電層402的開口 403b之中，與圖案化導電層 402相互電性連結，並藉由圖案化導電層與預設電阻 以及預設電阻404b相互電性連結。另一部份熱敏電阻4〇6b 位於圖案化導電層402之上，與圖案化導電層4〇2相互電性 連結，並藉由圖案化導電層4〇2與預設電阻4〇4a以及預設電 • 阻4〇4b相互電性連結。 其中，電性絕緣基材4〇〇的熔點係實質大於。材 夤可為一種陶瓷基材，例如氧化锆陶瓷或氧化鋁陶瓷。熱敏 電阻層4〇6之材質係一熱敏電阻膏，例如正溫度係數（Positive Temperature Coefficient; pTC )熱敏電阻膏、或負度係數 ^Negative Temperature c〇efficient; NTC )熱敏電阻膏經過低 服坟、纟。而成。在本發明的一些實施例之中，導電層4⑽係金 屬材貝層例如金 '銀 '銅χ銘、欽、錯、翻或以上所述金 屬a金在本發明的另一些實施例之中，導電層4〇2可以 是、石墨、摻雜之多晶矽。 實施例之中，係採用氧化鍅陶瓷作為電 化導電層402之材質係銀鈀合金。且採 在本發明的較佳 性絕緣基材400，圖案 用正溫度係數之熱敏電阻膏所形成之熱敏電阻406。 在本g务日月 孕乂佳實施例之中，熱敏電阻晶片更包括保護 層410覆蓋於一部份 77之熱敏電阻層406a之上，在本實施例之 中另邛伤之熱敏電阻406b則暴露於外，並未覆蓋保護層 1249750 4 1 0 °保蠖層4 1 〇之材質俏由俨备似r匕 ,^ 柯貝係由衣乳树脂、玻璃或矽所細# , 本發明的一此實絲 7所組成。在 二貫施例之中，熱敏電阻晶片還 極408，與圖宰化導雷 對外口p電 口朱1C等電層402相互電性連結。 根據本發明之另一目的， 造方法。 但…敏尾阻晶片的製 ^ θ在參妝第4圖’首先，提供-熔點實質大於1 〇〇〇。「 ::絕緣基材400，例如氧化錯陶究基材錢 =:使用例如，網版印刷製程'旋塗製程、沉積製程、炉 鍍程、或磨印製程，於電性絕緣基材400之上形成一 0宰" =電層.其中，圖案化導電層4G2具有複數=口 = 如開口仙與開口跡藉以將電性絕緣基材彻暴露出來。 圖案化導電層402係金屬材質層，例如金、銀、銅、鋁、 鈦H或以上所述金屬之合金。在本發明的另—此實施 =中’圖案化導電層之材質可以是、石墨、摻雜之多晶石夕， 較佳為鈦。 •、接著，分別在圖案化導電層術之開口 4心中以及圖案 化導電層402上形成至少一個預母雷 ， 1U頂σ又電阻層，例如形成於圖案 化導電層402之開口 403a + 〈闹口 4U3a中的預没電阻層4〇4a;以及形成於 圖案化導電層402上的預設電阻層键。使預設電阻4〇4a及 預設電阻404b與圖案化導電層4〇2相互電性連結。其中，預 設電阻404a及預設電阻404b之形成方法係選自於由網版印 刷製程、旋塗製程以及壓印製程所組成之一族群。 然後，藉由，例如網版印刷製程、旋塗製程以及壓印製 程，將一熱敏電阻膏分別塗布在圖案化導電層4〇2之開口 4〇3a 1249750 中’以及圖案化導電層4〇2上該電性絕緣基材4〇〇之上，使 5亥熱敏電阻膏與導電層402接觸。 再進行一低溫燒結步驟，燒結溫度，例如大約在6〇〇艺 至J 1,000 C之間。將該熱敏電阻膏燒結成至少一個具有陶兗半 導體材質之熱敏電阻，例如熱敏電阻4〇6a及熱敏電阻4〇6b。 在本發明的較佳實施例之中，形成熱敏電阻層4〇6a及熱 敏電阻406b之步驟還可以包括，在熱敏電阻層4〇6&之上形 φ 成並覆蓋由，例如環氧樹脂、玻璃或矽所組成保護層410。 由上述本發明較佳實施例可知，應用本發明具有電路尺 寸較小，且減少電阻排組之電阻值變異等優點。藉由將電阻 卜、、且整a於同一晶片之上，可以提供電阻排組一個共溫的環 境，減少習知電阻組排組電路因為位置不同導致外部環境溫 度差異’影響電阻阻值的變異程度。加上，藉由厚膜技術將 排組電路集中於單一基材之±，將排組之電路尺寸實質加以 縮小，以符合電子產品講求輕薄短小的趨勢。 鲁雖然本發明已以—較佳實施例揭露如上，然其並非用以 =疋本發明，任何熟習此技藝者，在不脫離本發明之精神和 fe圍内，當可作各種之更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 *為讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 12 1249750 第1圖係根據習知的溫度補償技術所繪示之溫度補償電 路模型之電阻排組示意圖。 第2a圖與第2b圖係分別依照本發明一些較佳實施例所 繪不之熱敏電阻晶片的電路不意圖。 第3圖係依照本發明另一較佳實施例所繪示之熱敏電阻 晶片之電阻排組的電路示意圖。 第4圖係依照本發明又一較佳實施例所繪示之熱敏電阻 晶片的剖面不意圖。 【主要元件符號說明】 200、 3 00、400 :電性絕緣基材 201、 301 :電阻排組 202、 302、402 :圖案化導電層 204、304a、304b、404a、404b、Rl、R2、R3、R4、R5、R6、 R7、R8、R9 :預設電阻 206、306a、3 06b、406a、406b :熱敏電阻 403a、403b :開口 408 :外部電極 410 :保護層 D :二極體 13Referring to FIG. 3, the third FI diagram is a schematic diagram of a resistor row and a group of the thermistor wafer according to another preferred embodiment of the present invention. In another embodiment of the present invention, the thermistor 3 group 3 01 located on the y and the edge substrate 3 系 is composed of a plurality of thermistors 3 〇 6h, 0%. # ..., 电阻 306a and thermistor 3 06b and a plurality of preset resistors, also on the 304b, for example, the preset resistor 304a and the preset resistor ... H, and %, or parallel _ series resistors are respectively The distance between the electrodes is connected, and the preset resistors 304a are connected in series such as χ + , , , 冤 306 306a and pre-mww, Γ electrically connected; the thermistor 预 and the pre- 5 and the resistor 304b The thermistor 306a and the preset resistor are connected in parallel; the thermistor is electrically connected to the 1249750 in parallel and in parallel. In other embodiments of the present invention, Arrangement of the resistor bank consisting of the patterned conductive layer 302, the pre-reistance resistor 304, and the thermistor 3〇..^^6 According to the function of the resistor row group, the resistance characteristics such as the thermistor-resistance curve and the thermal offset effect of the preset resistor are designed and arranged. Value = idea {, when the resistor row The group 3〇1 has two or more thermistors L: wherein at least one pair of thermistors, for example, the thermistor 孰 and the varistor 306a have different coefficients, such as a coefficient. In some embodiments of the invention, the thermistor 306b and the thermistor are respectively different from each other: an induction curve. In other embodiments of the invention, the thermistor is difficult to be positive with the thermistor 306a, respectively. The temperature coefficient blood is again negative, and the temperature coefficient is thermistor. In still other embodiments of the present invention, the thermistor 3 has a different heat conduction distance of the ohmic resistance field, such as the thermistor 3〇6a. The upper package: one layer is made of, for example, a resin material, and the thermistor 306b is exposed. Referring to FIG. 4, FIG. 4 is a schematic cross-sectional view of the thermistor wafer according to the preferred embodiment of the present invention. Preferred embodiment of the invention 'patterning guide The layer 4G2 is formed and overlaid on the electrically insulating substrate. The patterned conductive layer 4〇2 has a plurality of openings, such as openings 4〇3a and openings 403b, thereby exposing the electrically insulating substrate 4〇〇. In a preferred embodiment of the present invention, the predetermined resistance is connected to the pattern=electrical connection. In this embodiment, a portion of the predetermined resistor core is located on the electrically insulating substrate 400, and patterned. Among the openings 导电 of the conductive layer 4〇2, the patterned conductive layer 402 is electrically connected to each other. Further, a resistor 404b is located above the patterned conductive layer 4'' and electrically coupled to the patterned conductive acoustics.曰 1249750 In a preferred embodiment of the invention, the thermistor is in contact with the patterned conductive layer and electrically coupled to the predetermined resistor by the patterned conductive layer. In this embodiment, a portion of the thermistor 406a is located on the electrically insulating substrate 4, and is electrically connected to the patterned conductive layer 402 in the opening 403b of the patterned conductive layer 402. The patterned conductive layer is electrically connected to the preset resistor and the predetermined resistor 404b. Another part of the thermistor 4〇6b is located on the patterned conductive layer 402, electrically connected to the patterned conductive layer 4〇2, and patterned by the conductive layer 4〇2 and the preset resistor 4〇4a and The preset electric resistance 4 〇 4b is electrically connected to each other. Wherein, the melting point of the electrically insulating substrate 4〇〇 is substantially larger. The material may be a ceramic substrate such as zirconia ceramic or alumina ceramic. The material of the thermistor layer 4〇6 is a thermistor paste, such as a positive temperature coefficient (pTC) thermistor paste, or a negative coefficient (Negative Temperature c〇efficient; NTC) thermistor paste Low service graves, squatting. Made. In some embodiments of the present invention, the conductive layer 4 (10) is a metal shell layer such as gold 'silver' gong ming, ming, wrong, turning or the metal a gold described above in other embodiments of the invention, The conductive layer 4〇2 may be graphite, doped polysilicon. In the examples, a cerium oxide ceramic was used as the material of the electrochemical conductive layer 402 as a silver-palladium alloy. Further, in the preferred insulating substrate 400 of the present invention, the thermistor 406 formed of a positive temperature coefficient thermistor paste is patterned. In the preferred embodiment of the present invention, the thermistor wafer further includes a protective layer 410 overlying a portion 77 of the thermistor layer 406a. In this embodiment, another thermal shock is applied. The resistor 406b is exposed to the outside, and is not covered with the protective layer 1249750 4 1 0 ° The protective layer 4 1 〇 is made of 俨 匕 匕 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ , , , , , , , , , , , , , , , One of the solid silk 7 is composed. In the second embodiment, the thermistor wafer is further electrically connected to the electric layer 402 of the outer layer p-electrode Zhu 1C. According to another object of the present invention, a method of making. However, the fabrication of the snubber wafer is in the form of Figure 4, first of all, providing - the melting point is substantially greater than 1 〇〇〇. ": Insulating substrate 400, for example, oxidizing the substrate material money =: using, for example, a screen printing process, a spin coating process, a deposition process, a furnace plating process, or a rubbing process, on the electrically insulating substrate 400 Forming a 0 slaughter " = electrical layer. wherein, the patterned conductive layer 4G2 has a complex number = mouth = such as opening and opening traces to expose the electrically insulating substrate. The patterned conductive layer 402 is a metal layer, For example, gold, silver, copper, aluminum, titanium H or an alloy of the above metals. In another embodiment of the present invention, the material of the patterned conductive layer may be graphite, doped polycrystalline stone, Preferably, titanium, then, at least one pre-male, 1 U top σ and resistive layer, for example, formed in the opening of the patterned conductive layer 402, is formed in the opening 4 of the patterned conductive layer and on the patterned conductive layer 402, respectively. 403a + <pre-no resistance layer 4〇4a in the tray 4U3a; and a predetermined resistance layer key formed on the patterned conductive layer 402. The preset resistor 4〇4a and the preset resistor 404b and the patterned conductive layer 4 〇2 is electrically connected to each other, wherein the preset resistor 404a and the preset power The forming method of the resist 404b is selected from the group consisting of a screen printing process, a spin coating process, and an imprint process. Then, by, for example, a screen printing process, a spin coating process, and an imprint process, a heat is applied. The ohmic resistance paste is respectively coated on the opening 4〇3a 1249750 of the patterned conductive layer 4〇2 and the electrically conductive insulating substrate 4〇〇 on the patterned conductive layer 4〇2, so that the 5 ohm thermistor paste and The conductive layer 402 is contacted. A low temperature sintering step is performed, and the sintering temperature is, for example, between about 6 rpm and J 1,000 C. The thermistor paste is sintered into at least one thermistor having a ceramic semiconductor material, for example The thermistor 4〇6a and the thermistor 4〇6b. In the preferred embodiment of the present invention, the steps of forming the thermistor layer 4〇6a and the thermistor 406b may further include the thermistor layer 4 The top surface φ is formed and covered with a protective layer 410 composed of, for example, epoxy resin, glass or germanium. As can be seen from the above preferred embodiments of the present invention, the present invention has a smaller circuit size and reduces the resistance row group. The resistance value variation and other advantages. By placing the resistors on and off the same wafer, it is possible to provide a common temperature environment for the resistors to be arranged, and to reduce the variation of the external resistance due to the difference in position of the conventional resistor group. In addition, by thick film technology, the circuit is concentrated on a single substrate, and the circuit size of the array is substantially reduced to meet the trend of lightness and shortness of the electronic product. The embodiments are disclosed above, but they are not intended to be used in the present invention. Any person skilled in the art can make various changes and retouchings without departing from the spirit and scope of the present invention. The scope defined in the appended patent application shall prevail. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more apparent and understood. Figure 1 is a schematic diagram of a resistor bank arrangement of a temperature compensation circuit model according to a conventional temperature compensation technique. 2a and 2b are circuit diagrams of the thermistor wafers respectively depicted in accordance with some preferred embodiments of the present invention. Figure 3 is a circuit diagram showing the resistor bank of the thermistor wafer according to another preferred embodiment of the present invention. Figure 4 is a cross-sectional view of a thermistor wafer in accordance with still another preferred embodiment of the present invention. [Main component symbol description] 200, 300, 400: electrically insulating substrate 201, 301: resistor row group 202, 302, 402: patterned conductive layer 204, 304a, 304b, 404a, 404b, Rl, R2, R3 , R4, R5, R6, R7, R8, R9: preset resistors 206, 306a, 306b, 406a, 406b: thermistors 403a, 403b: opening 408: external electrode 410: protective layer D: diode 13