JP7622308B2 - 半導体デバイスにおける成形された相互接続バンプ - Google Patents

半導体デバイスにおける成形された相互接続バンプ Download PDF

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JP7622308B2
JP7622308B2 JP2020519726A JP2020519726A JP7622308B2 JP 7622308 B2 JP7622308 B2 JP 7622308B2 JP 2020519726 A JP2020519726 A JP 2020519726A JP 2020519726 A JP2020519726 A JP 2020519726A JP 7622308 B2 JP7622308 B2 JP 7622308B2
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bumps
surface area
semiconductor package
power
tapered
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JP2020537342A (ja
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ケイ コドゥリ スリーニーバサン
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テキサス インスツルメンツ インコーポレイテッド
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    • H10W72/01212—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps at a different location than on the final device, e.g. forming as prepeg
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    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
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    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
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  • Lead Frames For Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Manufacturing & Machinery (AREA)
JP2020519726A 2017-10-05 2018-10-04 半導体デバイスにおける成形された相互接続バンプ Active JP7622308B2 (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201762568330P 2017-10-05 2017-10-05
US201762568331P 2017-10-05 2017-10-05
US201762568333P 2017-10-05 2017-10-05
US62/568,331 2017-10-05
US62/568,333 2017-10-05
US62/568,330 2017-10-05
US16/103,839 US11444048B2 (en) 2017-10-05 2018-08-14 Shaped interconnect bumps in semiconductor devices
US16/103,839 2018-08-14
PCT/US2018/054392 WO2019070995A1 (en) 2017-10-05 2018-10-04 INTERCONNECTION BUMPS SHAPED IN SEMICONDUCTOR DEVICES

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JP2020537342A JP2020537342A (ja) 2020-12-17
JP7622308B2 true JP7622308B2 (ja) 2025-01-28

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JP2020519680A Active JP7197849B2 (ja) 2017-10-05 2018-10-05 半導体デバイスにおけるリードフレーム
JP2020519681A Active JP7448754B2 (ja) 2017-10-05 2018-10-05 半導体デバイスにおけるプレモールドリードフレーム

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US (6) US11444048B2 (https=)
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