JP7197849B2 - 半導体デバイスにおけるリードフレーム - Google Patents
半導体デバイスにおけるリードフレーム Download PDFInfo
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- JP7197849B2 JP7197849B2 JP2020519680A JP2020519680A JP7197849B2 JP 7197849 B2 JP7197849 B2 JP 7197849B2 JP 2020519680 A JP2020519680 A JP 2020519680A JP 2020519680 A JP2020519680 A JP 2020519680A JP 7197849 B2 JP7197849 B2 JP 7197849B2
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- 239000004065 semiconductor Substances 0.000 title claims description 147
- 150000001875 compounds Chemical class 0.000 claims description 14
- 238000000465 moulding Methods 0.000 claims description 14
- 230000005540 biological transmission Effects 0.000 claims 1
- 230000008054 signal transmission Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 description 59
- 229910052751 metal Inorganic materials 0.000 description 59
- 238000005520 cutting process Methods 0.000 description 42
- 238000000034 method Methods 0.000 description 23
- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 229910000679 solder Inorganic materials 0.000 description 16
- 239000000463 material Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000012530 fluid Substances 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000000926 separation method Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910007637 SnAg Inorganic materials 0.000 description 1
- 229910007116 SnPb Inorganic materials 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009760 electrical discharge machining Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
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Description
Claims (10)
- 半導体パッケージであって、
長手方向軸を含む複数のバンプを含む半導体ダイと、
前記複数のバンプに取り付けられるリードフレームの一部であって、前記リードフレームが、第1の側と、前記第1の側とは逆の第2の側と、前記第1の側から前記リードフレーム内に延在する第1の複数の開口と、前記第2の側から前記リードフレーム内に延在する第2の複数の開口とを含み、前記第1の複数の開口が第1の横方向幅を有し、前記第2の複数の開口が前記第1の横方向幅より大きい第2の横方向幅を有する、前記リードフレームの一部と、
前記半導体ダイの一部と前記複数のバンプの一部と前記第1の複数の開口の一部とを覆うモールディング化合物と、
を含み、
前記第1の複数の開口が前記半導体パッケージの上面から見て非線形であり、前記複数のバンプの幾つかの幅が前記複数のバンプの他のものと異なる、半導体パッケージ。 - 請求項1に記載の半導体パッケージであって、
前記第2の複数の開口が前記半導体パッケージの底面から見て線形である、半導体パッケージ。 - 請求項1に記載の半導体パッケージであって、
前記複数のバンプの各々が、前記複数のバンプの各々の長手方向軸に沿って前記リードフレームから離れて先細りにされている、半導体パッケージ。 - 請求項1に記載の半導体パッケージであって、
前記第2の複数の開口の各々の深さが、前記第1の側と前記第2の側との間の間隔の50~80パーセントである、半導体パッケージ。 - 請求項1に記載の半導体パッケージであって、
前記第1の複数の開口の各々が正弦曲線パターンを含む、半導体パッケージ。 - 半導体パッケージであって、
第1の側と前記第1の側とは逆の第2の側とを含むリードフレームと、
前記第1の側からの第1の複数の開口であって、前記第1の複数の開口の各々が前記リードフレームの上面から見て非線形である、前記第1の複数の開口と、
前記第2の側からの第2の複数の開口であって、前記第2の複数の開口の各々が前記第1の複数の開口の各々より広い、前記第2の複数の開口と、
複数の第1のバンプと複数の第2のバンプとを介して前記リードフレームに電気的に接続される半導体ダイであって、前記複数の第1のバンプの各々が、前記半導体パッケージの断面平面上の前記複数の第2のバンプの各々の横方向断面エリアより大きい横方向断面エリアを含み、前記半導体パッケージの断面平面が前記複数の第1のバンプ又は前記複数の第2のバンプと交わる、前記半導体ダイと、
を含み、
前記複数の第1のバンプが多数の行に配列され、前記多数の行の異なるが隣接する行からの前記複数のバンプの少なくとも2つが前記半導体パッケージの側面から見て互いに部分的に重なる、半導体パッケージ。 - 請求項6に記載の半導体パッケージであって、
前記第2の複数の開口の各々が、前記半導体パッケージの底面から見て線形である、半導体パッケージ。 - 請求項6に記載の半導体パッケージであって、
前記リードフレームと前記半導体ダイと前記第1の複数の開口と前記第2の複数の開口との一部を覆うモールド化合物を更に含む、半導体パッケージ。 - 請求項6に記載の半導体パッケージであって、
前記複数の第1のバンプが前記半導体ダイへの電力伝送のためのものである、半導体パッケージ。 - 請求項6に記載の半導体パッケージであって、
前記複数の第2のバンプが前記半導体ダイへの信号伝送のためのものである、半導体パッケージ。
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US201762568330P | 2017-10-05 | 2017-10-05 | |
US201762568333P | 2017-10-05 | 2017-10-05 | |
US201762568331P | 2017-10-05 | 2017-10-05 | |
US62/568,333 | 2017-10-05 | ||
US62/568,331 | 2017-10-05 | ||
US62/568,330 | 2017-10-05 | ||
US16/150,986 | 2018-10-03 | ||
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