JP2020537340A - 半導体デバイスにおけるリードフレーム - Google Patents
半導体デバイスにおけるリードフレーム Download PDFInfo
- Publication number
- JP2020537340A JP2020537340A JP2020519680A JP2020519680A JP2020537340A JP 2020537340 A JP2020537340 A JP 2020537340A JP 2020519680 A JP2020519680 A JP 2020519680A JP 2020519680 A JP2020519680 A JP 2020519680A JP 2020537340 A JP2020537340 A JP 2020537340A
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- Prior art keywords
- openings
- lead frame
- bumps
- metal strip
- semiconductor package
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 156
- 239000002184 metal Substances 0.000 claims abstract description 95
- 229910052751 metal Inorganic materials 0.000 claims abstract description 95
- 238000005520 cutting process Methods 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 51
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 14
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- 238000000465 moulding Methods 0.000 claims description 16
- 238000003486 chemical etching Methods 0.000 claims description 9
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 230000008054 signal transmission Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 16
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- 238000004519 manufacturing process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 235000014676 Phragmites communis Nutrition 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
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- 241001124569 Lycaenidae Species 0.000 description 1
- 244000089486 Phragmites australis subsp australis Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910007637 SnAg Inorganic materials 0.000 description 1
- 229910007116 SnPb Inorganic materials 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 235000014987 copper Nutrition 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
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- 230000024241 parasitism Effects 0.000 description 1
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- 239000011347 resin Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
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Abstract
Description
Claims (27)
- 半導体パッケージを形成するための方法であって、
半導体パッケージのためのリードフレームを形成することを含み、
前記リードフレームを形成することが、
金属ストリップの第1の側に延在する第1の複数の開口を形成するため、切断パターンに従って前記第1の側を深さD1まで切断することであって、前記深さD1が前記金属ストリップの高さHより小さく、前記深さD1が、前記金属ストリップの前記第1の側から、前記第1の側とは反対の前記金属ストリップの第2の側に向かっている、前記第1の側を切断することと、
前記金属ストリップの前記第2の側に延在する第2の複数の開口を形成するため、フォトレジストパターンに従って前記金属ストリップの前記第2の側を深さD2までエッチングすることであって、前記深さD2が前記金属ストリップの高さHより浅い、前記第2の側をエッチングすることと、
半導体ダイと、前記リードフレームの前記複数のリード上の複数のバンプランディングサイトとの間の複数のバンプを結合することであって、前記複数のバンプの少なくとも幾つかが、前記複数のリードの最後の一つに沿った端部から見たときに重なり合うように見える、前記複数のバンプを結合することと、
半導体パッケージを形成するため、前記半導体ダイの少なくとも一部と前記リードフレームの少なくとも一部をモールディング化合物で覆うことと、
を含み、
前記第1の複数の開口の少なくとも幾つかが、前記第2の複数の開口の上にあり、前記第2の複数の開口の少なくとも幾つかと流体連通してリードフレーム上に複数のリードを形成し、
前記第1の側を切断するための前記切断パターンが非線形部分を含む、
方法。 - 請求項1に記載の半導体パッケージを形成するための方法であって、前記金属ストリップの前記第1の側を切断することが、レーザー、精密ウォータージェット、又はプラズマカッターを用いることを含む、方法。
- 請求項1に記載の半導体パッケージを形成するための方法であって、前記切断パターンが、前記第1の開口が前記第2の開口の上にあるように前記フォトレジストパターンと整合し、前記金属ストリップの前記第1の側を切断することが、前記高さHの少なくとも50パーセントが前記金属ストリップの前記第2の側からエッチングされている位置と整合する、方法。
- 請求項1に記載の半導体パッケージを形成するための方法であって、前記第2の側からの前記エッチングが、前記金属ストリップの前記高さHの50〜80パーセントを取り除く、方法。
- 請求項1に記載の半導体パッケージを形成するための方法であって、前記金属ストリップの前記第1の側を切断することが、50ミクロン未満である横方向幅W1を有する切断部を形成することを含む、方法。
- 請求項1に記載の半導体パッケージを形成するための方法であって、前記金属ストリップの前記第1の側を切断することが、25ミクロン未満である横方向幅W1を有する切断を形成することを含む、方法。
- 請求項1に記載の半導体パッケージを形成するための方法であって、前記切断が、前記エッチング後に行われる、方法。
- 請求項1に記載の半導体パッケージを形成するための方法であって、前記フォトレジストパターンが実質的に線形である、方法。
- 請求項1に記載の半導体パッケージを形成するための方法であって、前記フォトレジストパターンが実質的に線形であり、前記切断パターンが曲線状である、方法。
- 方法であって、
半導体パッケージのためのリードフレームを形成することを含み、
前記リードフレームを形成することが、
金属ストリップの第1の側を前記第1の側へ延在する第1の複数の開口を形成するために切断パターンに従って切断することであって、前記金属ストリップが前記第1の側と前記第1の側とは反対の第2の側とを有し、前記金属ストリップが前記第1の側と前記第2の側との間に高さHを有し、対応するバンプのベースを受けるためのサイトである複数のバンプランディングサイトを有する複数のリードを形成することを含む、前記第1の側を切断することと、
前記金属ストリップの前記第2の側にフォトレジストを適用することと、
前記金属ストリップの前記第2の側へ延在する第2の複数の開口を形成するために前記金属ストリップの前記第2の側に化学エッチングを適用することであって、前記第2の複数の開口の少なくとも一部が前記第1の複数の開口と整合し、前記第2の側からの前記エッチングの深さD2が前記金属ストリップの前記高さH未満である、前記金属ストリップの前記第2の側に化学エッチングを適用することと、
前記金属ストリップの前記第2の側から前記フォトレジストを取り除くことと、
半導体ダイと、前記リードフレーム上の前記複数のバンプランディングサイトとの間の複数のバンプを結合することであって、前記複数のバンプの少なくとも幾つかが、前記複数のリードの少なくとも幾つかに沿った端部から見たときに重なり合うように見える、前記複数のバンプを結合することと、
半導体パッケージを形成するため、前記半導体ダイ及び前記リードフレームの少なくとも一部をモールディング化合物で覆うことと、
を含む、
方法。 - 請求項10に記載の方法であって、前記金属ストリップの前記第1の側を切断することがレーザーを用いることを含む、方法。
- 請求項10に記載の方法であって、前記金属ストリップの前記第1の側を切断することが、精密ウォータージェット又はプラズマカッターを用いることを含む、方法。
- 請求項10に記載の方法であって、前記フォトレジストパターンに従って前記金属ストリップの前記高さHの50〜80パーセントが除去されるまで前記化学的エッチングが適用される、方法。
- 請求項10に記載の方法であって、前記金属ストリップの前記第1の側を切断することが、50ミクロン未満である横方向幅W1を有する切断を形成することを含む、方法。
- 請求項10に記載の方法であって、前記金属ストリップの前記第1の側を切断することが、25ミクロン未満である横方向幅W1を有する切断を形成することを含む、方法。
- 請求項10に記載の方法であって、前記切断が、前記化学的エッチングを適用する工程の後に行われる、方法。
- 請求項10に記載の方法であって、前記切断パターンが、非線形であり正弦波パターンに類似している、方法。
- 半導体パッケージであって、
金属リードフレームを含み、前記金属リードフレームが、
第1の側と前記第1の側とは反対の第2の側とを有する金属ストリップ、
前記第1の側から前記金属ストリップ内へ部分的に延在し、前記第1の側に沿って延在する第1の複数の開口であって、前記第1の複数の開口の各々が、50ミクロン又はそれより短い横方向幅W1を有する、前記第1の複数の開口と、
前記第2の側から前記金属ストリップ内へ部分的に延在し、前記第2の側に沿って延在する第2の複数の開口であって、前記第2の複数の開口の各々が、前記横方向幅W1より大きい横方向幅W2を有し、前記第1の複数の開口が前記第2の複数の開口と交差して複数のリードを形成する、前記第2の複数の開口と、
前記複数のリード上の前記リードフレームの前記第1の側上の複数のバンプランディングサイトと、
幅W3を有し、前記リードフレーム上の前記複数のバンプランディングサイトの少なくとも幾つかから半導体ダイ上のサイトまで延在する、複数の電力バンプと、
幅W4を有し、前記リードフレーム上の前記複数のバンプランディングサイトの少なくとも幾つかから半導体ダイ上のサイトまで延在する複数の信号バンプであって、W3がW4より大きい、前記複数の信号バンプと、
前記リードフレームの少なくとも一部と前記半導体ダイの少なくとも一部と覆うモールディング化合物と、
を含み、
前記第1の複数の開口が、非線形であり、前記第2の複数の開口の上にあり、
前記複数の電力バンプの少なくとも幾つかと前記複数の信号バンプの少なくとも幾つかとが、前記リードフレームの少なくとも一つに沿った端部から見た場合に重なって見える、
半導体パッケージ。 - 請求項18に記載の半導体パッケージであって、
前記複数の電力バンプのうちの少なくとも一つが、前記複数のリードの第2のリードに近接する前記複数のリードの第1のリード上にあり、
前記複数の信号バンプのうちの少なくとも一つが前記第2のリードに結合され、
前記第1のリード上の前記複数の信号バンプのうちの少なくとも一つの信号バンプの中心が、前記複数の電力バンプのうちの前記少なくとも一つの電力バンプの中心から距離Dだけ直角に分離されており、W3の半分にW4の半分に付加したものがDより大きい、
半導体パッケージ。 - 請求項18に記載の半導体パッケージであって、前記複数の電力バンプの各々が、前記半導体ダイにおける端部から前記リードフレームにおけるより大きな端部まで長手方向軸に沿って先細りにされている、半導体パッケージ。
- 請求項18に記載の半導体パッケージであって、前記第2の複数の開口の深さが、前記金属リードフレームの高さHの50〜80パーセントである、半導体パッケージ。
- 請求項18に記載の半導体パッケージであって、前記第2の複数の開口が線形である、半導体パッケージ。
- 半導体パッケージであって、
第1の側と前記第1の側とは反対の第2の側とを含むリードフレーム、
前記第1の側からの第1の複数の開口及び前記第2の側からの第2の複数の開口であって、前記第2の複数の開口の各々が前記第1の複数の開口の各々より広く、前記第1の複数の開口の各々が前記リードフレームの上面図から非線形である、前記第1の複数の開口及び前記第2の複数の開口、
複数の第1のバンプ及び複数の第2のバンプを介して前記リードフレームに電気的に接続される半導体ダイ、
を含み、
複数の第1のバンプの各々が、半導体ダイの所与の断面平面上の前記第2の複数のバンプの各々の横方向断面エリアより大きい横方向断面エリアを含み、
前記第1の複数のバンプのうちの少なくとも一つが、前記半導体パッケージの側面図からの前記第2の複数のバンプのうちの少なくとも一つと重なる、
半導体パッケージ。 - 請求項23に記載の半導体パッケージであって、前記第2の複数の開口の各々が、前記リードフレームの平面図から線形である、半導体パッケージ。
- 請求項23に記載の半導体パッケージであって、モールド化合物が、前記リードフレーム、前記半導体ダイ、前記第1の複数の開口、及び前記第2の複数の開口の一部を覆う、半導体パッケージ。
- 請求項23に記載の半導体パッケージであって、前記複数の第1のバンプが前記半導体ダイへの電力伝送のためのものである、半導体パッケージ。
- 請求項23に記載の半導体パッケージであって、前記複数の第2のバンプが前記半導体への信号伝送のためのものである、半導体パッケージ。
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EP3692569A1 (en) | 2020-08-12 |
US20220037277A1 (en) | 2022-02-03 |
JP2020537342A (ja) | 2020-12-17 |
EP3692574A4 (en) | 2020-12-02 |
US20230012200A1 (en) | 2023-01-12 |
EP3692570A1 (en) | 2020-08-12 |
CN111357098A (zh) | 2020-06-30 |
EP3692570A4 (en) | 2020-12-02 |
EP3692569A4 (en) | 2020-12-09 |
WO2019071072A1 (en) | 2019-04-11 |
JP2020537341A (ja) | 2020-12-17 |
JP7448754B2 (ja) | 2024-03-13 |
US20210210453A1 (en) | 2021-07-08 |
CN111316433A (zh) | 2020-06-19 |
US11444048B2 (en) | 2022-09-13 |
US10957666B2 (en) | 2021-03-23 |
WO2019071069A1 (en) | 2019-04-11 |
US20190109016A1 (en) | 2019-04-11 |
WO2019070995A1 (en) | 2019-04-11 |
CN111295748A (zh) | 2020-06-16 |
EP3692574A1 (en) | 2020-08-12 |
US11152322B2 (en) | 2021-10-19 |
US20190109076A1 (en) | 2019-04-11 |
JP7197849B2 (ja) | 2022-12-28 |
US20190109110A1 (en) | 2019-04-11 |
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