CN111403304B - 形成迹线上凸块(bot)组件的方法和半导体结构 - Google Patents
形成迹线上凸块(bot)组件的方法和半导体结构 Download PDFInfo
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- CN111403304B CN111403304B CN202010223888.0A CN202010223888A CN111403304B CN 111403304 B CN111403304 B CN 111403304B CN 202010223888 A CN202010223888 A CN 202010223888A CN 111403304 B CN111403304 B CN 111403304B
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Abstract
本发明的实施例提供了一种形成封装件的迹线上凸块(BOT)的方法和半导体结构。该方法包括:在衬底上形成接合迹线,在平面视图中,接合迹线具有第一部分,第二部分和将第一部分连接至第二部分的第三部分,第一部分的第一侧壁与第二部分的第一侧壁共线,第一部分的第二侧壁与第二部分的第二侧壁和第三部分的第二侧壁共线,在平面视图中,第三部分的第一侧壁具有朝着第三部分的第二侧壁凹进的一个或多个第一凹槽,第三部分的第二侧壁整体是平坦的侧壁;将导电柱置放在接合迹线的第三部分上方,使得导电柱至少部分地覆盖接合迹线的第三部分中的一个或多个第一凹槽;以及将接合迹线电连接至导电柱。
Description
分案申请
本申请是2014年08月28日提交的标题为“用于迹线上凸块(BOT)组件的迹线设计”、专利申请号为201410431316.6的分案申请。
技术领域
本发明涉及半导体领域,更具体地,涉及用于迹线上凸块(BOT)组件的迹线设计。
背景技术
在诸如倒装芯片芯片级封装件(fcCSP)的封装件中,将集成电路(IC)或管芯通过迹线上凸块(BOT)互连件安装到衬底(例如,印刷电路板(PCB)或其他集成电路载体)。BOT互连件采用焊料将IC的凸块电连接到衬底的迹线。
根据更小的封装件的需求,经常尝试减小邻近的凸块之间的距离,也称为凸块间距。一种减小凸块间距的方式是通过减小相邻的金属迹线之间的距离。
不幸地是,减小相邻的金属迹线之间的间距可以导致不期望的或不利的影响。例如,如果相邻的金属迹线彼此太近,则当建立BOT互连件时,可以形成焊桥。
发明内容
为解决上述问题,本发明提供了一种用于形成迹线上凸块(BOT)组件的方法,包括:在衬底上形成接合迹线;在接合迹线上方设置导电柱,使得导电柱至少延伸到接合迹线的一端;以及回流位于接合迹线和导电柱之间的焊料部件以将接合迹线电连接到导电柱。
该方法还包括将导电柱设置在接合迹线上方,使得导电柱悬于接合迹线的一端之上。
该方法还包括设置导电柱,使得接合迹线位于导电柱外围中的长度为导电柱的直径的约20%到约100%。
该方法还包括设置导电柱,使得接合迹线位于导电柱外围中的长度小于导电柱的直径。
该方法还包括在设置导电柱之前,相对于相邻迹线的长度降低接合迹线的长度。
该方法还包括在设置导电柱之前,去除接合迹线的一部分以产生增广润湿区域。
其中,在回流焊料部件之后,焊料部件邻接接合迹线的端表面和两个侧壁。
此外,还提供了一种用于形成迹线上凸块(BOT)组件的方法,包括:在衬底上形成接合迹线;产生增广润湿区域;以及将焊料施加到接合迹线的增广润湿区域上方,以将接合迹线电连接到导电柱。
其中,增广润湿区域包括接合迹线的端表面。
其中,增广润湿区域包括接合迹线的端表面和接合迹线的两个相对侧壁的一部分。
其中,增广润湿区域包括位于接合迹线中的至少一个凹槽。
其中,增广润湿区域包括位于接合迹线中的多个凹槽。
该方法还包括去除接合迹线的一部分以产生增广润湿区域。
该方法还包括去除接合迹线的一部分,使得接合迹线位于导电柱外围中的长度是导电柱的直径的约20%到约100%。
该方法还包括对准导电柱,使得导电柱的外围至少延伸到接合迹线的一端。
该方法还包括对准导电柱,使得导电柱的外围悬于接合迹线的一端之上。
此外,还提供了一种用于封装件的迹线上凸块(BOT)互连件,包括:接合迹线,接合迹线包括远端;导电柱,至少延伸到接合迹线的远端;以及焊料部件,电连接接合迹线和导电柱。
其中,导电柱悬于接合迹线的远端之上。
其中,封装件中的接合迹线的长度比相邻迹线的长度短。
其中,焊料部件啮合接合迹线的端表面和相对侧壁。
附图说明
为了更全面地理解本发明及其优势,现将结合附图所进行的以下描述作为参考,其中:
图1示出了为了易于说明的封装件(已去除管芯)中的迹线上凸块(BOT)组件的实施例的顶视图;
图2示出了通常沿线2-2截取的图1的BOT组件的实施例的截面图;
图3示出了通常沿线2-2截取的图1的BOT组件的实施例的截面图;
图4至图6共同示出了用于制造图1至图3的BOT组件的实施例的工艺流程的实施例;
图7至图8示出了可以形成在图1的BOT组件的实施例的接合迹线中的凹槽;
图9示出了相对于导电柱下方的接合迹线的部分的导电柱的尺寸;
图10至图11提供了一组图像,该组图像示出了位于图1的BOT互连件和BOT组件的实施例中的焊料部件和相邻的迹线之间的增大的距离;以及
图12至图13示出了形成图1的BOT组件的方法的实施例。
除非另有说明,否则不同图中的相应数字和符号常常表示相应的部分。绘制的图只用于清楚地说明实施例的相关方面,因此无需按比例绘制。
具体实施方式
下面,详细讨论本发明各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式,而不用于限制本发明的范围。
本发明将关于具体环境中的实施例进行描述,即合并迹线上凸块(BOT)互连件的封装件。然而,本发明中的构思也可以应用于其他封装件、互连组件或半导体结构。
共同参考图1至图3,示出了用于封装件12的迹线上凸块(BOT)组件10。下文将提供更全面的解释,BOT组件10比使用其他方法形成的BOT组件提供更多的益处和优势。例如,BOT组件10允许焊料更均匀地分散在接合迹线上方。通过这样做,禁止或避免了细小的间距凸块设计中邻近的迹线之间的不期望的焊桥。此外,BOT组件10为封装件12提供了更稳健的和更可靠的电子互连。
如图所示,采用BOT组件10将管芯14(在图2和图3中)电连接(以及,在一些实施例中,结构性连接)到衬底16。在实施例中,管芯14包括从晶圆分割的各种不同的集成电路的一个或多个。在实施例中,例如,衬底16可以是印刷电路板。在一些实施例中,管芯14和衬底16均可以包括为了易于示出而忽略的额外的组件、层、结构或部件。
如图1所示,BOT组件10包括接合迹线18、导电柱20、和焊料部件22。接合迹线18邻近于衬底16上的至少一个相邻的迹线30。下文将进行解释,接合迹线18具有减小的长度,或可以将接合迹线18相对于邻近的相邻迹线30缩短。换句话说,接合迹线18可以比相邻迹线30更短。
如图2和图3所示,接合迹线18由衬底16支撑。在实施例中,将接合迹线18全部设置在衬底16的顶面上方。在实施例中,接合迹线18至少部分地嵌入到衬底16中。例如,由诸如铜(Cu)的导电金属形成接合迹线18,但是也可以由其他合适的导电金属形成。
再次参考图1,BOT组件10的接合迹线18包括接合迹线18的端24。端24也可以称为远端。端24提供位于相对的侧壁28之间的端表面26。在接合迹线18短于相邻的迹线30的实施例中,接合迹线18的远端24偏移于相邻的迹线30的远端24。换句话说,虽然设置在衬底16上,但是接合迹线18和相邻的迹线30没有彼此对准。
如图2至图3所示,将导电柱20连接到管芯14。例如,由诸如铜(Cu)的导电金属形成导电柱20,但是也可以由其他合适的导电金属形成。导电柱20可以指代凸块或底部凸块金属化(UBM)。
如图1至图2所示,在一些实施例中,导电柱20至少延伸到接合迹线18的远端24,且可以延伸到远端24的上方。换句话说,如图1所示,导电柱20的外围32至少到达下面的接合迹线18的端表面26。在实施例中,导电柱20悬于下面的接合迹线18之上,使得导电柱20的外围32突出超过下面的接合迹线18的端表面26。在实施例中,导电柱20的宽度34大于下面的接合迹线18的宽度36。
在实施例中,接合迹线18和导电柱20可以采用多种合适的形状。换句话说,接合迹线18和导电柱20不限于图1至图3中示出的形状。例如,除了矩形,接合迹线18还可以是正方形、圆形、椭圆形等。此外,除了椭圆形,导电柱20还可以是矩形、正方形、圆形等。
如图1至图3,将焊料部件22(例如,焊料接合点)设置在导电柱20和接合迹线18之间且环绕导电柱20和接合迹线18。同样地,焊料部件22可以电连接从具有设置在衬底16上的接合迹线18的管芯14延伸的导电柱20。
在实施例中,焊料部件22接合且邻接接合迹线18的侧壁28。在实施例中,焊料部件22还接合且邻接接合迹线18的端表面26。焊料部件22可以是用于接合部件且在部件下方具有金属结合点的焊膏、焊球或另一合适的易熔金属合金。
如图1至图2所示,由于导电柱20至少延伸到接合迹线18的远端24,且可以悬于接合迹线18的远端24之上,所以允许焊料部件22均匀地分散在接合迹线18的侧壁28上。由于焊料部件22沿侧壁28的两侧设置,所以相比于当焊料仅润湿(wet on)在两个侧壁28的一个侧壁上时,减小了位于接合迹线18的任一侧上的焊料的体积。换句话说,将焊料的体积分散到两个侧壁28之间,而不是仅沿侧壁28的一个侧壁积累。
由于将焊料的体积分配在接合迹线18的两个侧壁28之间,相对于当仅沿着接合迹线18面对相邻迹线30的侧壁28收集大多数或全部的焊料部件22时,减小了焊料部件22和相邻迹线30之间的距离。因此,例如,可以减小接合迹线18和相邻迹线30之间的间距以提供更小的整体封装件10。
在实施例中,将焊料的体积分配在接合迹线18的两个侧壁28和端表面26之间。在这样的实施例中,相对于当仅沿着接合迹线18面对相邻迹线30的侧壁28收集焊料部件22时,可以进一步降低焊料部件22和相邻迹线30之间的距离。
在实施例中,从一开始就可以使接合迹线18小于相邻迹线30。在这种情况下,将不会产生由图4中的虚线描绘的接合迹线18的部分38。在另一实施例中,如果在接合迹线18的远端24具有足够的空间以允许导电柱延伸到远端24或悬于远端24之上,则接合迹线18和相邻的接合迹线18可以具有约相同的长度。换言之,如果将接合迹线18的远端24间隔远离衬底16的外围以考虑焊料连接件,则接合迹线18和相邻的接合迹线18可以具有约相同的长度。
现在参考图4至图6,概要地示出了用于制造图1至图3的BOT组件10的实施例工艺流。如图4所示,在衬底16上形成接合迹线18和相邻迹线30。在实施例中,在形成工艺期间,忽略了接合迹线18的部分38(由虚线表示),使得接合迹线18在长度上小于相邻迹线30。
在实施例中,接合迹线18和相邻迹线30最初可以形成为具有相同的长度,之后,可以去除部分38以提供具有较短长度的接合迹线18。例如,可以通过蚀刻去除接合迹线18的部分38。也可以通过激光切割、激光灼烧、选择性蚀刻工艺、机械切割等适当地去除接合迹线的部分38。
现在参考图5,当制造的接合迹线18小于相邻迹线30或当已经去除接合迹线18的部分38时,产生或制造了增广润湿区域(augmented wetting area)40(图5中虚线所示)。在实施例中,增广润湿区域40包括接合迹线18的端表面26。在实施例中,增广润湿区域40包括端表面26和接合迹线18的两个侧壁28的至少一部分。增广润湿区域40为焊料部件22提供更多的面积和额外的表面以使焊料部件22分散在其上方和周围。
现在参考图5,将导电柱20设置在接合迹线18上方。在实施例中,导电柱20至少延伸到接合迹线18的远端24。在实施例中,导电柱20悬于接合迹线18的远端24之上。换言之,如图5所示,导电柱20的外围32设计为超过下面的接合迹线18的端表面26。
现在参考图6,在设置导电柱20之后,回流最初设置在接合迹线18和导电柱20之间的焊料部件22。当焊料部件22冷却时,将接合迹线18电连接至导电柱20。在图6中,焊料部件22沿接合迹线18的两个侧壁28和端表面26延伸。因此,相对于其他BOT互连件降低了焊料部件22向邻接的相邻迹线30的方向挤出。
如图7至图8所示,在实施例中,可以在接合迹线18中形成一个或多个凹槽42以产生或有助于接合迹线18的增广润湿区域40(虚线所示)。换言之,可以在接合迹线18中形成凹槽42,而不是(或另外)去除图4中示出的接合迹线18的部分38。接合迹线18中的凹槽42提供了用于焊料部件22的区域以基于回流占据。同样地,相对于其他BOT互连件降低了焊料部件22向邻接的相邻迹线30的方向挤出。
如图7所示,凹槽42可以形成为“鱼骨”图案。如图8中所示,凹槽42可以形成为“梳子”图案。凹槽42也可以形成为各种其他合适的图案。例如,凹槽42可以形成为对称的或不对称的图案,凹槽42之间的间距相等或不相等的图案等。此外,凹槽42可以具有多种合适的形状。例如,凹槽42可以是正方形、矩形、半圆形、椭圆等。
现在参考图9,相邻迹线30描绘为横向邻接接合迹线18。如图所示,示出的焊料部件22和导电柱20位于接合迹线18上方。导电柱20具有直径R。接合迹线18具有长度L,长度L表示接合迹线18位于导电柱20的外围32中的部分。
在实施例中,接合迹线18位于导电柱20的外围32中的长度L是导电柱20的直径R的约20%到约100%。选择20%的下限是因为总的装配工艺变化是导电柱20的直径R的约20%。因此,为了确保导电柱20在接合迹线18上有合适的接合点,建议接合迹线18的长度L为导电柱20的直径R的20%以上。如果不是的话,由于导电柱20没有接触接合迹线18,在装配工艺之后可遇到电动开启(electric open)。在实施例中,设置导电柱20,使得接合迹线18位于导电柱20的外围32中的长度L小于导电柱20的直径R的100%。换言之,满足等式1/5R≤L≤R。
现在参考图10至图11,第一图像44和第二图像46示出了当使用本文描述的工艺时焊料部件和相邻迹线之间的增大的距离。的确,如图10所示,BOT互连件52中的焊料部件和相邻迹线之间的距离D1小于使用实施例BOT组件10的焊料部件和相邻迹线之间的迹线D2。换言之,由于支持焊料部件22沿着图11的BOT组件10中的两个侧壁润湿,所以图11中的距离D2远远大于图10中的距离D1。
在图12中,示出了形成BOT组件10的方法60。在框62中,在衬底16上形成接合迹线18。在框64中,将导电柱20设置在接合迹线18上方,使得导电柱20至少延伸到接合迹线18的端24。在框66中,回流接合迹线18和导电柱20之间的焊料部件22以将接合迹线18电连接到导电柱20。
在图13中,示出了用于形成BOT组件10的方法70。在框72中,接合迹线18形成在衬底16上。在框74中,去除接合迹线18的部分以产生增广润湿区域40。在框76中,将焊料施加到接合迹线18的增广润湿区域40上方以将接合迹线电连接到导电柱20。
由上可知,本领域的普通技术人员将意识到BOT组件10控制或最小化焊料挤出。而且,BOT组件10使焊料更均匀地分散到接合迹线上方。因此,降低了焊桥在细小凸块间距封装件中形成的可能性。换言之,禁止或避免了细小间距凸块(I/O)设计中邻近迹线之间的不期望的焊桥。此外,通过在没有大量额外的工艺成本的情况下改变现存的迹线图案设计,BOT组件10为封装件12提供了更稳健和可靠的电互连件。
一种用于形成迹线上凸块(BOT)组件的实施例方法包括:在衬底上形成接合迹线,将导电柱设置在接合迹线上方使得导电柱至少延伸到接合迹线的端,以及回流接合迹线和导电柱之间的焊料部件以将接合迹线电连接到导电柱。
一种用于形成迹线上凸块(BOT)组件的实施例方法包括:在衬底上形成接合迹线,去除接合迹线的部分以产生增广润湿区域,以及将焊料施加到接合迹线的增广润湿区域的上方以将接合迹线电连接到导电柱。
一种用于封装件的实施例迹线上凸块(BOT)互连件包括:接合迹线,接合迹线包括远端;导电柱,至少延伸到接合迹线的远端;以及焊料部件,电连接接合迹线和导电柱。
虽然根据示出的实施例介绍本发明,但是,本说明并不构成限制意义。参考本说明,示出实施例的不同修改和组合以及本发明的其他实施例对本领域的技术人员来说是显而易见的。因此,所附权利要求包括任何这样的修改或实施例。
Claims (20)
1.一种形成迹线上凸块(BOT)组件的方法,该方法包括:
在衬底上形成接合迹线,在平面视图中,所述接合迹线具有第一部分,第二部分和将所述第一部分连接至所述第二部分的第三部分,所述第一部分的第一侧壁与所述第二部分的第一侧壁共线,所述第一部分的第二侧壁与所述第二部分的第二侧壁和所述第三部分的第二侧壁共线,在平面视图中,所述第三部分的第一侧壁具有朝着所述第三部分的第二侧壁凹进的多个第一凹槽,所述第三部分的第二侧壁整体是平坦的侧壁;
将导电柱置放在所述接合迹线的所述第三部分上方,使得所述导电柱至少部分地覆盖所述接合迹线的所述第三部分中的所述多个第一凹槽;以及
将所述接合迹线电连接至所述导电柱,
其中,所述第一部分和所述第二部分的宽度与所述第三部分最宽处的宽度相同。
2.根据权利要求1所述的方法,其中,通过使用焊料部件将所述接合迹线连接至所述导电柱来至少部分地执行所述电连接。
3.根据权利要求2所述的方法,其中,所述焊料部件沿着所述接合迹线的表面延伸,所述接合迹线的表面与所述衬底相交。
4.根据权利要求3所述的方法,其中,所述焊料部件延伸至所述衬底。
5.根据权利要求2所述的方法,其中,所述焊料部件沿着所述第三部分的所述多个第一凹槽中的每一个凹槽的侧壁延伸。
6.根据权利要求5所述的方法,其中,所述焊料部件填充所述第三部分中的所述多个第一凹槽。
7.根据权利要求6所述的方法,其中,所述焊料部件与所述衬底物理接触。
8.根据权利要求2所述的方法,其中,所述焊料部件接触所述第一部分的相对侧壁和所述第二部分的相对侧壁。
9.根据权利要求1所述的方法,其中,所述多个第一凹槽包括梳状图案。
10.根据权利要求1所述的方法,其中,所述导电柱的宽度大于所述接合迹线的宽度。
11.根据权利要求1所述的方法,其中,所述接合迹线至少部分地嵌入在所述衬底中。
12.一种半导体结构,包括:
衬底;以及
接合迹线,位于所述衬底上,所述接合迹线包括:
第一部分;
第二部分;和
第三部分,将所述第一部分连接至所述第二部分,在平面视图中,所述第一部分的第一侧壁与所述第二部分的第一侧壁共线,所述第一部分的第二侧壁与所述第二部分的第二侧壁和所述第三部分的第二侧壁均共线,所述第三部分的第一侧壁具有多个凹口,而所述第三部分的第二侧壁完全是平坦的侧壁,
其中,所述第一部分和所述第二部分的宽度与所述第三部分最宽处的宽度相同。
13.根据权利要求12所述的结构,其中,所述多个凹口在平面视图中具有梳状图案。
14.根据权利要求12所述的结构,还包括:焊料部件,位于所述接合迹线的所述第三部分上,在平面视图中,所述焊料部件与所述多个凹口重叠。
15.根据权利要求14所述的结构,其中,所述焊料部件沿着所述多个凹口的侧壁延伸。
16.根据权利要求15所述的结构,其中,所述焊料部件填充所述多个凹口。
17.根据权利要求14所述的结构,还包括:导电柱,位于所述焊料部件上,所述导电柱在平面视图中与所述多个凹口重叠。
18.根据权利要求12所述的结构,其中,所述接合迹线至少部分地嵌入在所述衬底中。
19.根据权利要求17所述的结构,其中,所述焊料部件的宽度大于所述导电柱的宽度。
20.根据权利要求14所述的结构,其中,所述焊料部件接触所述第一部分的相对侧壁和所述第二部分的相对侧壁。
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US9129955B2 (en) * | 2009-02-04 | 2015-09-08 | Texas Instruments Incorporated | Semiconductor flip-chip system having oblong connectors and reduced trace pitches |
US8390119B2 (en) * | 2010-08-06 | 2013-03-05 | Mediatek Inc. | Flip chip package utilizing trace bump trace interconnection |
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