TW201546956A - 形成跡線上凸塊(bot)組件的方法以及跡線上凸塊內連線 - Google Patents
形成跡線上凸塊(bot)組件的方法以及跡線上凸塊內連線 Download PDFInfo
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- TW201546956A TW201546956A TW103144811A TW103144811A TW201546956A TW 201546956 A TW201546956 A TW 201546956A TW 103144811 A TW103144811 A TW 103144811A TW 103144811 A TW103144811 A TW 103144811A TW 201546956 A TW201546956 A TW 201546956A
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Abstract
提供一種封裝體中的跡線上凸塊(BOT)內連線以及製造該BOT內連線的方法。一種示範性BOT內連線包括接合跡線,其包括一遠端;導電柱,至少延伸至接合跡線的遠端;以及焊料特徵,電性耦接接合跡線以及導電柱。在一實施方式中,導電柱懸垂於接合跡線的端面上。在另一實施方式中,接合跡線包括一或多個凹陷,用以捕集回流後的焊料特徵。因此,焊料特徵可利用的潤濕區變得較大,同時允許封裝體的凸塊間距保持很小。
Description
本發明是有關於封裝結構,且特別是有關於形成跡線上凸塊組件的方法以及跡線上凸塊內連線。
在像是覆晶晶片尺寸封裝(flip chip Chip Scale Package,fcCSP)的封裝體中,積體電路(IC)或晶粒透過跡線上凸塊(bump on trace,BOT)內連線安裝於基材(例如印刷電路板或其他積體電路載體)。BOT內連線採用焊料,以將IC的凸塊電性耦接至基材的跡線。
由於對愈來愈小的封裝體的需求,已經進行許多嘗試以降低被稱之為凸塊間距(pitch)的相鄰凸塊之間的距離。一種降低凸塊間距的方法是降低鄰接金屬跡線之間的距離。
可惜的是,降低鄰接金屬跡線之間的距離可能導致不理想的或有害的結果。例如,如果鄰接金屬跡線彼此太過接近,在建立BOT內連線的回流期間可能形成焊
料橋(solder bridge)。
一種形成跡線上凸塊(BOT)組件的示範性方法包括形成接合跡線在基材上,定位導電柱於接合跡線上以使導電柱至少延伸至接合跡線的末端,以及回流介於接合跡線和導電柱之間的焊料特徵以將接合跡線電性耦接至導電柱。
一種形成跡線上凸塊(BOT)組件的示範性方法包括形成接合跡線於基材上,移除接合跡線的一部分以產生擴充潤濕區,以及施用焊料於接合跡線的擴充潤濕區上以將接合跡線電性耦接至導電柱。
一種示範性的封裝體的跡線上凸塊(BOT)內連線,包括接合跡線,其包括一遠端;導電柱,至少延伸至接合跡線的遠端;以及焊料特徵,電性耦接接合跡線以及導電柱。
10‧‧‧跡線上凸塊組件
12‧‧‧封裝體
14‧‧‧晶粒
16‧‧‧基材
18‧‧‧接合跡線
20‧‧‧導電柱
22‧‧‧焊料特徵
24‧‧‧末端
26‧‧‧端面
28‧‧‧側壁
30‧‧‧鄰接跡線
32‧‧‧邊緣
34‧‧‧寬度
36‧‧‧寬度
38‧‧‧部份
40‧‧‧擴充潤濕區
42‧‧‧凹陷
44‧‧‧第一圖像
46‧‧‧第二圖像
52‧‧‧BOT內連線
60、70‧‧‧方法
62、64、66、72、74、76‧‧‧方塊
D1、D2‧‧‧距離
L‧‧‧長度
R‧‧‧直徑
為了更完整理解本揭露及其優點,現在參照以下說明並結合附圖,其中:圖1繪示封裝體中示範性的跡線上凸塊(BOT)組件的上視圖,為了易於說明,圖中省略晶粒;圖2繪示圖1的示範性BOT組件大致沿著線2-2的剖面圖;
圖3繪示圖1的示範性BOT組件大致沿著線3-3的剖面圖;圖4-6共同繪示了用來製作圖1-3的示範性BOT組件的示範性流程;圖7-8繪示可以在圖1的示範性BOT組件的接合跡線(landing trace)中形成的凹陷;圖9繪示相對於接合跡線位於導電柱下方的部份之導電柱尺寸;圖10-11提供一系列圖像,繪示相較於BOT內連線,圖1的示範性BOT組件中焊料特徵和鄰接跡線所增加的距離;而圖12-13繪示形成圖1的BOT組件的示範性方法。
除非另作說明,不同圖式中對應的數字和符號通常指涉對應的部件。圖式之繪示是為了清楚說明實施方式的相關態樣,而不一定是按照比例繪示的。
以下將詳細討論本實施方式的製造和使用。然而,應理解的是,本揭露提供了許多可應用的發明概念,其可體現於各式各樣的具體脈絡。所討論的具體實施方式僅是說明性的,並不限制本揭露的範疇。
將參照一具體脈絡中的實施方式來描述本揭露,即結合跡線上凸塊(BOT)內連線的封裝體。然而,本揭露中的概念也可以應用於其他封裝體、內連
線組件或半導體結構。
一同參照圖1-3,其繪示用於封裝體12的跡線上凸塊(BOT)組件10。如下文將更完整解釋的,相對於使用其他方法形成的BOT組件,BOT組件10提供了許多好處和優點。例如,BOT組件10使焊料得以更均勻地散布在接合跡線上。藉此,產生於微細間距凸塊設計中相鄰跡線之間的不理想的焊料橋接現象(solder bridging)得到抑制或排除。此外,BOT組件10為封裝體12提供了更健全可靠的電性內連線。
如圖所示,採用BOT組件10以將晶粒14(見圖2和3)電性耦接(以及在一些實施方式中,結構性耦接)至基材16。在一實施方式中,晶粒14包括從晶圓上分離出來的多種不同積體電路中的一者或多者。在一實施方式中,基材16例如可以是印刷電路板。在一些實施方式中,晶粒14和基材16可各自包括此處為了便於說明而省略的其他構件、層、結構或特徵。
如圖1所示,BOT組件10包括接合跡線18、導電柱20以及焊料特徵22。接合跡線18與基材16上鄰接跡線30中的至少一者相鄰。如以下將解釋的,相對於相鄰的鄰接跡線30,接合跡線18的長度減少,或可被截斷(truncated)。換句話說,接合跡線18可以比鄰接跡線30短。
如圖2-3所示,接合跡線18由基材16支持。在一實施方式中,接合跡線18全部配置於基材16的
頂表面上。在一實施方式中,接合跡線18至少部份內埋於基材16中。接合跡線18由導電金屬形成,例如銅(Cu),但若適當也可由其他導電金屬形成。
回頭參照圖1,BOT組件10的接合跡線18包括接合跡線18的末端24。末端24也可稱為遠端(distal end)。末端24提供位於相對的側壁28之間的端面26。在接合跡線18比鄰接跡線30短的實施方式中,接合跡線18的遠端24與鄰接跡線30的遠端24錯開(offset)。換句話說,位於基材16上的接合跡線18和鄰接跡線30相互不對齊。
如圖2-3所示,導電柱20耦接至晶粒14。導電柱20由導電金屬形成,例如銅(Cu),但若適當也可由其他導電金屬形成。導電柱20可被稱為凸塊或凸塊底層金屬化層(under bump metallization,UBM)。
如圖1-2所示,導電柱20至少延伸到接合跡線18的遠端24,且在一些實施方式中可延伸到超過遠端24。換句話說,導電柱20的邊緣32至少會碰觸到下方的接合跡線18的端面26,如圖1所示。在一實施方式中,導電柱20懸垂於下方的接合跡線18上,使得導電柱20的邊緣32之投影超過下方的接合跡線18的端面26。在一實施方式中,導電柱20的寬度34大於下方的接合跡線18的寬度36。
在一實施方式中,接合跡線18和導電柱20可以具有各種不同的形狀。換句話說,接合跡線18和導
電柱20不限於圖1-3所繪示的形狀。例如,接合跡線18可以是方形、圓形、卵形等形狀,而不是矩形。此外,導電柱20可以是矩形、方形、圓形等形狀而不是卵形。
如圖1-3所示,焊料特徵22(例如焊料接點)配置於導電柱20和接合跡線18之間,且包圍兩者。藉此,焊料特徵22得以將從晶粒14延伸出的導電柱20電性耦接至配置於基材16上的接合跡線18。
在一實施方式中焊料特徵22貼合(engage)且緊靠著接合跡線18的兩個側壁28。在一實施方式中,焊料特徵22也接合且緊靠著接合跡線18的端面26。焊料特徵22可以是焊料膏、焊料球或其他用來連接部件且熔點比該部件低的適當易熔金屬合金。
因為導電柱20至少延伸到接合跡線18的遠端24且可能懸垂於遠端24上,如圖1-2所示,焊料特徵22得以均勻地散布在接合跡線18的兩個側壁28上。由於焊料特徵22沿著兩個側壁28配置,焊料在接合跡線18的每一側上的體積相較於焊料僅潤濕兩個側壁28中之一者的情形更為減少。換句話說,焊料的體積均分於兩個側壁28,而不是聚集在側壁28中的一者。
因為焊料的體積由接合跡線18的兩個側壁28共享,比起焊料特徵22的大部分或全部都聚集在接合跡線18面對鄰接跡線30的側壁28上的情形,焊料特徵22和鄰接跡線30之間的距離減少了。因此,接合跡線18和鄰接跡線30之間的間距可以縮短,由此,例如可使封裝
體10的整體變小。
在一實施方式中,焊料的體積由接合跡線18的兩個側壁28和端面26共享。在此類實施方式中,焊料特徵22和鄰接跡線30之間的距離可以進一步減少(相對於焊料特徵22僅聚集在接合跡線18面對鄰接跡線30的側壁28上的情形)。
在一實施方式中,可以一開始就把接合跡線18做得比鄰接跡線30小。在此類情況中,不會產生接合跡線18的部份38(在圖4中由虛線所繪示者)。在其他實施方式中,如果在接合跡線18的遠端24有足夠空間,允許導電柱延伸至或懸垂於遠端24上,接合跡線18和鄰接的接合跡線18可具有大致相同的長度。換句話說,如果接合跡線18的遠端24和基材16的邊緣間隔開來,能允許焊料連接,那麼接合跡線18和鄰接的接合跡線18可具有大致相同的長度。
現在參照圖4-6,其繪示了用來製作圖1-3的BOT組件10的示範性流程。如圖4所示,接合跡線18和鄰接跡線30形成在基材16上。在一實施方式中,接合跡線18的部份38(由虛線表示)在形成過程期間被移除,使得接合跡線18的長度比鄰接跡線30短。
在一實施方式中,接合跡線18和鄰接跡線30一開始形成的時候可以具有相同長度,之後,可以移除部份38以讓接合跡線18的長度較短。接合跡線18的部份38例如可以透過蝕刻移除。若適當,接合跡線的部份38
也可以透過雷射切割、雷射燒製(laser burn)、選擇性蝕刻製程、機械式切割等方法來移除。
現在參照圖5,當接合跡線18變得比鄰接跡線30短,或者接合跡線18的部份38被移除以後,產生或製造出擴充潤濕區40(圖5中以虛線呈現)。在一實施方式中,擴充潤濕區40包括接合跡線18的端面26。在一實施方式中,擴充潤濕區40包括接合跡線18的端面26和兩個側壁28的至少一部分。擴充潤濕區40提供了更多的區域或額外的表面,使焊料特徵22得以散布於其上並包圍之。
現在參照圖5,導電柱20位於接合跡線18上。在一實施方式中,導電柱20至少延伸至接合跡線18的遠端24。在一實施方式中,導電柱20懸垂於接合跡線18的遠端24上。換句話說,導電柱20的邊緣32之投影,超出了下方的接合跡線18的端面26,如圖5所示。
現在參照圖6,在定位導電柱20之後,起初配置在接合跡線18和導電柱20之間的焊料特徵22經回流處理。在焊料特徵22冷卻時,接合跡線18電性耦接至導電柱20。在圖6中,焊料特徵22沿著接合跡線18的兩個側壁28和端面26延伸。因此,焊料特徵22往相鄰的鄰接跡線30方向的突出相較於其他BOT內連線有所減少。
如圖7-8所示,在一實施方式中,可以在接合跡線18中形成一或多個凹陷42,以產生或擴大接合跡線
18的擴充潤濕區40(以虛線呈現)。換句話說,除了如圖4所示的移除接合跡線18的部份38之外,還可以在接合跡線18中形成凹陷42。接合跡線18中的凹陷42提供了焊料特徵22在回流時可以佔據的空間。藉此,焊料特徵22往相鄰的鄰接跡線30方向的突出相較於其他BOT內連線有所減少。
如圖7所示,凹陷42可以形成為「魚骨」圖案。如圖8所示,凹陷42可以形成為「梳狀」圖案。凹陷42也可以形成各種其他圖案。例如,凹陷42可以形成為對稱或非對稱圖案、在凹陷42之間的間距一致或不一致的圖案等等。此外,凹陷42可具有各種適當的形狀。例如,凹陷42可以是方形、矩形、半圓形、卵形等等。
現在參照圖9,鄰接跡線30被繪示成與接合跡線18在側向上相鄰。如圖所示,焊料特徵22和導電柱20被繪示為位於接合跡線18上。導電柱20具有直徑R。接合跡線18具有一長度L,其代表接合跡線18位於導電柱20的邊緣32內的部份。
在一實施方式中,接合跡線18在導電柱20的邊緣32內的長度L是導電柱20之直徑R的約20%至約100%。選擇20%作為下限是因為整個組裝過程的變異係數(variation)是導電柱20之直徑R的約20%。因此,為了確保導電柱20能夠適當連接於接合跡線18,建議接合跡線18的長度L為導電柱20的直徑R的20%或更大。若非如此,在組裝過程之後可能會因為導電柱20
並未接觸接合跡線18而遭遇電性斷路。在一實施方式中,導電柱20之定位將使得接合跡線18在導電柱20的邊緣32內的長度L小於導電柱20之直徑R的100%。換句話說,滿足等式1/5RLR。
現在參照圖10-11,第一圖像44和第二圖像46顯示在使用本文所述的製程時在焊料特徵和鄰接跡線之間所增加的距離。確實,如圖10所示,距離D1小於距離D2,其中距離D1是在BOT內連線52內介於焊料特徵和鄰接跡線之間的距離,距離D2是使用示範性BOT組件10時介於焊料特徵和鄰接跡線之間的距離。換句話說,因為焊料特徵22可以沿著圖11的BOT組件10中的兩個側壁潤濕,圖11中的距離D2遠超過圖10中的距離D1。
在圖12中繪示形成BOT組件10的方法60。在方塊62中,接合跡線18形成在基材16上。在方塊64中,導電柱20定位於接合跡線18上,使得導電柱20至少延伸至接合跡線18的末端24。在方塊66中,介於接合跡線18和導電柱20之間的焊料特徵22經回流處理以將接合跡線18電性耦接至導電柱20。
在圖13中繪示形成BOT組件10的方法70。在方塊72中,接合跡線18形成在基材16上。在方塊74中,接合跡線18的一部分被移除以產生擴充潤濕區40。在方塊76中,施用焊料於接合跡線18的擴充潤濕區40上以將接合跡線電性耦接至導電柱20。
基於前述,本技術領域中具有通常知識者將理
解,BOT組件10控制或最小化焊料的突出。再者,BOT組件10使焊料可以更均勻地散布在接合跡線上。此外,在凸塊間距微細的封裝體中形成焊料橋的可能性降低了。換句話說,避免或抑制了在間距微細的凸塊(I/O)設計中相鄰跡線之間不理想的焊料橋接現象。此外,藉由改變現存的跡線圖案設計,BOT組件10為封裝體12提供了更健全可靠的電性內連線,且沒有顯著增加製程費用。
一種形成跡線上凸塊(BOT)組件的示範性方法包括形成接合跡線在基材上,定位導電柱於接合跡線上以使導電柱至少延伸至接合跡線的末端,以及回流介於接合跡線和導電柱之間的焊料特徵以將接合跡線電性耦接至導電柱。
一種形成跡線上凸塊(BOT)組件的示範性方法包括形成接合跡線於基材上,移除接合跡線的一部分以產生擴充潤濕區,以及施用焊料於接合跡線的擴充潤濕區上以將接合跡線電性耦接至導電柱。
一種示範性的封裝體的跡線上凸塊(BOT)內連線,包括接合跡線,其包括一遠端;導電柱,至少延伸至接合跡線的遠端;以及焊料特徵,電性耦接接合跡線以及導電柱。
雖然本揭露提供說明性的實施方式,這些描述不應該以限制性的方式來解讀。在參照了本說明以後,說明性實施方式和其他實施方式的各種修改和結合,對於所屬技術領域中具有通常知識者而言是顯而易見的。因此,
隨附請求項意欲涵蓋任何該等修改或實施方式。
10‧‧‧跡線上凸塊組件
12‧‧‧封裝體
16‧‧‧基材
18‧‧‧接合跡線
20‧‧‧導電柱
22‧‧‧焊料特徵
24‧‧‧末端
26‧‧‧端面
28‧‧‧側壁
30‧‧‧鄰接跡線
32‧‧‧邊緣
34‧‧‧寬度
36‧‧‧寬度
Claims (20)
- 一種形成跡線上凸塊(BOT)組件的方法,包括:形成一接合跡線於一基材上;定位一導電柱於該接合跡線上,使該導電柱至少延伸至該接合跡線的一末端;以及回流介於該接合跡線和該導電柱之間的一焊料特徵以將該接合跡線電性耦接至該導電柱。
- 如申請專利範圍第1項所述之形成跡線上凸塊組件的方法,更包括定位該導電柱於該接合跡線上以使該導電柱懸垂於該接合跡線的該末端上。
- 如申請專利範圍第1項所述之形成跡線上凸塊組件的方法,更包括定位該導電柱以使該接合跡線位於一導電柱邊緣內的長度是該導電柱的直徑的約20%至約100%。
- 如申請專利範圍第1項所述之形成跡線上凸塊組件的方法,更包括定位該導電柱以使該接合跡線位於一導電柱邊緣內的長度小於該該導電柱的直徑。
- 如申請專利範圍第1項所述之形成跡線上凸塊組件的方法,更包括在定位該導電柱之前使該接合跡線的長度相對於一鄰接跡線的長度有所減少。
- 如申請專利範圍第1項所述之形成跡線上凸塊組件的方法,更包括在定位該導電柱之前移除該接合跡線的一部分以產生一擴充潤濕區。
- 如申請專利範圍第1項所述之形成跡線上凸塊組件的方法,其中在回流該焊料特徵之後該焊料特徵緊靠著該接合跡線的一端面和兩個側壁。
- 一種形成跡線上凸塊(BOT)組件的方法,包括:形成一接合跡線於一基材上;產生一擴充潤濕區;以及施用一焊料於該接合跡線的該擴充潤濕區上以將該接合跡線電性耦接至一導電柱。
- 如申請專利範圍第8項所述之形成跡線上凸塊組件的方法,其中該擴充潤濕區包括該接合跡線的一端面。
- 如申請專利範圍第8項所述之形成跡線上凸塊組件的方法,其中該擴充潤濕區包括該接合跡線的一端面以及該接合跡線之相對兩側壁的一部分。
- 如申請專利範圍第8項所述之形成跡線 上凸塊組件的方法,其中該擴充潤濕區包括該接合跡線中的至少一凹陷。
- 如申請專利範圍第8項所述之形成跡線上凸塊組件的方法,其中該擴充潤濕區包括該接合跡線中的多個凹陷。
- 如申請專利範圍第8項所述之形成跡線上凸塊組件的方法,更包括移除該接合跡線的一部分以產生該擴充潤濕區。
- 如申請專利範圍第8項所述之形成跡線上凸塊組件的方法,更包括移除該接合跡線的一部分以使該接合跡線在一導電柱邊緣內的長度是該導電柱的直徑的約20%至約100%。
- 如申請專利範圍第8項所述之形成跡線上凸塊組件的方法,更包括調整該導電柱以使該導電柱的邊緣至少延伸至該接合跡線的一末端。
- 如申請專利範圍第8項所述之形成跡線上凸塊組件的方法,更包括調整該導電柱以使該導電柱的邊緣懸垂於該接合跡線的一末端上。
- 一種封裝體的跡線上凸塊(BOT)內連 線,包括:一接合跡線,包括一遠端;一導電柱,至少延伸至該接合跡線的該遠端;以及一焊料特徵,電性連接該接合跡線和該導電柱。
- 如申請專利範圍第17項所述之跡線上凸塊內連線,其中該導電柱懸垂於該接合跡線的該遠端上。
- 如申請專利範圍第17項所述之跡線上凸塊內連線,其中該接合跡線的長度比該封裝體中的一鄰接跡線短。
- 如申請專利範圍第17項所述之跡線上凸塊內連線,其中該焊料特徵接合該接合跡線的一端面以及其相對的側壁。
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US10833033B2 (en) * | 2011-07-27 | 2020-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bump structure having a side recess and semiconductor structure including the same |
US20150187719A1 (en) * | 2013-12-30 | 2015-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Trace Design for Bump-on-Trace (BOT) Assembly |
CN110634828B (zh) * | 2018-06-21 | 2021-11-16 | 矽创电子股份有限公司 | 凸块结构 |
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US6664483B2 (en) * | 2001-05-15 | 2003-12-16 | Intel Corporation | Electronic package with high density interconnect and associated methods |
US8574959B2 (en) * | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
US8076232B2 (en) * | 2008-04-03 | 2011-12-13 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
US8841779B2 (en) * | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
US9258904B2 (en) * | 2005-05-16 | 2016-02-09 | Stats Chippac, Ltd. | Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings |
JP2008186876A (ja) * | 2007-01-29 | 2008-08-14 | Alps Electric Co Ltd | 電子部品及びその製造方法 |
US9345148B2 (en) | 2008-03-25 | 2016-05-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad |
US8198186B2 (en) * | 2008-12-31 | 2012-06-12 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material during reflow with solder mask patch |
US9129955B2 (en) * | 2009-02-04 | 2015-09-08 | Texas Instruments Incorporated | Semiconductor flip-chip system having oblong connectors and reduced trace pitches |
US8390119B2 (en) * | 2010-08-06 | 2013-03-05 | Mediatek Inc. | Flip chip package utilizing trace bump trace interconnection |
US8435834B2 (en) * | 2010-09-13 | 2013-05-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP |
US8441127B2 (en) * | 2011-06-29 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace structures with wide and narrow portions |
TW201306203A (zh) * | 2011-07-22 | 2013-02-01 | Powertech Technology Inc | 避免銲料橋接金屬柱之半導體封裝構造 |
US8952529B2 (en) * | 2011-11-22 | 2015-02-10 | Stats Chippac, Ltd. | Semiconductor device with conductive layer over substrate with vents to channel bump material and reduce interconnect voids |
US8664041B2 (en) * | 2012-04-12 | 2014-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for designing a package and substrate layout |
US20150187719A1 (en) * | 2013-12-30 | 2015-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Trace Design for Bump-on-Trace (BOT) Assembly |
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- 2013-12-30 US US14/143,648 patent/US20150187719A1/en not_active Abandoned
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2014
- 2014-08-28 CN CN202010223888.0A patent/CN111403304B/zh active Active
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DE102014118941A1 (de) | 2015-07-02 |
US10269759B2 (en) | 2019-04-23 |
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US20150187719A1 (en) | 2015-07-02 |
CN104752336A (zh) | 2015-07-01 |
TWI550767B (zh) | 2016-09-21 |
CN111403304A (zh) | 2020-07-10 |
CN111403304B (zh) | 2023-05-05 |
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