CN111316433A - 半导体装置中的成形互连凸块 - Google Patents

半导体装置中的成形互连凸块 Download PDF

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Publication number
CN111316433A
CN111316433A CN201880070356.9A CN201880070356A CN111316433A CN 111316433 A CN111316433 A CN 111316433A CN 201880070356 A CN201880070356 A CN 201880070356A CN 111316433 A CN111316433 A CN 111316433A
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China
Prior art keywords
bumps
surface area
leadframe
package
tapered
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CN201880070356.9A
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Chinese (zh)
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斯里尼瓦萨恩·K·科杜里
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Texas Instruments Inc
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Texas Instruments Inc
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Publication of CN111316433A publication Critical patent/CN111316433A/zh
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    • H10W70/01—Manufacture or treatment
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    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
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    • H10W72/01212—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps at a different location than on the final device, e.g. forming as prepeg
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    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
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    • H10W72/01251—Changing the shapes of bumps
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
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  • Lead Frames For Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Manufacturing & Machinery (AREA)
CN201880070356.9A 2017-10-05 2018-10-04 半导体装置中的成形互连凸块 Pending CN111316433A (zh)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201762568330P 2017-10-05 2017-10-05
US201762568331P 2017-10-05 2017-10-05
US201762568333P 2017-10-05 2017-10-05
US62/568,331 2017-10-05
US62/568,333 2017-10-05
US62/568,330 2017-10-05
US16/103,839 US11444048B2 (en) 2017-10-05 2018-08-14 Shaped interconnect bumps in semiconductor devices
US16/103,839 2018-08-14
PCT/US2018/054392 WO2019070995A1 (en) 2017-10-05 2018-10-04 INTERCONNECTION BUMPS SHAPED IN SEMICONDUCTOR DEVICES

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CN111316433A true CN111316433A (zh) 2020-06-19

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CN201880070356.9A Pending CN111316433A (zh) 2017-10-05 2018-10-04 半导体装置中的成形互连凸块
CN201880070342.7A Active CN111295748B (zh) 2017-10-05 2018-10-05 半导体装置中的引线框
CN201880073966.4A Pending CN111357098A (zh) 2017-10-05 2018-10-05 半导体装置中的预模制引线框

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CN201880073966.4A Pending CN111357098A (zh) 2017-10-05 2018-10-05 半导体装置中的预模制引线框

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US (6) US11444048B2 (https=)
EP (3) EP3692574A4 (https=)
JP (3) JP7622308B2 (https=)
CN (3) CN111316433A (https=)
WO (3) WO2019070995A1 (https=)

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US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
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