JP7485736B2 - 3d nandデバイス用の誘電体材料上におけるモリブデンを含有する低抵抗膜の成膜 - Google Patents
3d nandデバイス用の誘電体材料上におけるモリブデンを含有する低抵抗膜の成膜 Download PDFInfo
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- JP7485736B2 JP7485736B2 JP2022145721A JP2022145721A JP7485736B2 JP 7485736 B2 JP7485736 B2 JP 7485736B2 JP 2022145721 A JP2022145721 A JP 2022145721A JP 2022145721 A JP2022145721 A JP 2022145721A JP 7485736 B2 JP7485736 B2 JP 7485736B2
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- molybdenum
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Description
本願は、米国特許法第119条の下、2017年4月10日出願の米国仮特許出願第62/483,857号の利益を主張し、その仮特許出願は、参照によって本書に組み込まれる。
特定の実施形態において、タングステン(W)系成長開始層上にモリブデン(Mo)含有層を含む構造が提供される。Mo含有膜の形成方法も提供されている。
特定の実施形態では、Mo含有層が、W系成長開始層を利用せずに蒸着されてよい。例えば、元素Mo層が、TiNまたは誘電体層の上に蒸着されてよい。特定の前駆体に対して、蒸着温度は、蒸着を得るために、相対的に高くてよい(550℃超)。塩素含有前駆体(MoOCl5、MoOCl4、およびMoO2Cl2など)を用いたCVD蒸着が、TiNおよび誘電体表面に550℃より高い温度で実行されてよい。より低い温度で、CVD蒸着が、上述のようにW系成長開始層を用いて任意の表面に実行されてもよい。さらに、いくつかの実施形態において、CVD蒸着が、PNLプロセスによって蒸着されたMo含有核形成層を用いて任意の表面に実行されてもよい。
より低い温度(550℃未満)での蒸着が、図4Aに示すような処理によって非W表面(誘電体およびTiN表面など)に直接実行されてもよい。それは、W含有面上で用いられてもよい。図4Aは、開示された実施形態に従って実行される方法の処理フローチャートを提供する。図4Aの動作402~408は、少なくとも誘電体表面またはその他の表面へ直接的に共形Mo層を形成するために実行されてよい。
H2のパルス
アルゴンパージ
バックグラウンドのH2を伴うかまたは伴わないMo含有前駆体のパルス
アルゴンパージ
繰り返し
いくつかの実施形態において、多成分Mo含有膜が提供される。いくつかのかかる実施形態において、多成分Mo含有膜は、ホウ素(B)、シリコン(Si)、または、ゲルマニウム(Ge)の内の1または複数を含んでよい。図4Bは、開示された実施形態に従って実行される方法の処理フローチャートを提供する。
WF6を還元するために、それぞれ、シランおよびジボランを用いてPNLによって蒸着されたタングステン核形成層上にCVD Mo膜を成長させた。シラン蒸着タングステン核形成層は、SW核形成層とも呼ばれ、ジボラン蒸着タングステン核形成層は、BW核形成層とも呼ばれる。Mo膜は、MoOCl4およびH2から蒸着された。
いくつかの実施形態において、熱アニールが、Mo蒸着後に実行される。これは、Mo粒子成長および低い抵抗率を可能にしうる。Moの融点はWよりも低いので、Mo膜に対しては、粒子成長およびそれに伴う抵抗率の低下が、より低い温度で起きる。アニール温度の例は、700℃~1100℃の範囲である。アニールは、炉内でまたは高速熱アニールによって実行されてよい。様々な実施形態によると、アニールは、水素(H2)雰囲気、窒素(N2)雰囲気、または、真空など、任意の適切な雰囲気中で実行されてよい。
任意の適切なチャンバを用いて、開示した実施形態を実施することができる。蒸着装置の例としては、例えば、カリフォルニア州フレモントのLam Research社製のALTUS(登録商標)およびALTUS(登録商標)Max、もしくは、様々な他の市販の処理システムのいずれかなど、様々なシステムが挙げられる。処理は、複数の蒸着ステーションで並行して実行できる。
理解を深めるために、本実施形態について、ある程度詳しく説明したが、添付の特許請求の範囲内でいくらかの変更および変形を行ってもよいことは明らかである。本発明の処理、システム、および、装置を実施する多くの他の方法が存在することに注意されたい。したがって、本実施形態は、例示的なものであって、限定的なものではないとみなされ、実施形態は、本明細書に示した詳細に限定されない。
本開示は、以下の形態により実現されてもよい。
[形態1]
方法であって、
タングステン(W)含有層を基板上に提供する工程と、
モリブデン(Mo)含有層を前記W含有層上に蒸着させる工程と、
を備える、方法。
[形態2]
形態1に記載の方法であって、前記W含有層は、WCN層である、方法。
[形態3]
形態1の方法であって、前記W含有層は、W核形成層である、方法。
[形態4]
形態1ないし3のいずれかに記載の方法であって、前記W含有層は、1または複数の塩化タングステン前駆体から蒸着される、方法。
[形態5]
形態1ないし3のいずれかに記載の方法であって、前記Mo含有層は、1(原子)%未満の不純物を有するMo層である、方法。
[形態6]
形態1ないし3のいずれかに記載の方法であって、さらに、前記Mo含有層を熱アニールする工程を備える、方法。
[形態7]
形態1ないし3のいずれかに記載の方法であって、前記Mo含有層は、還元剤と、六フッ化モリブデン(MoF 6 )、五塩化モリブデン(MoCl 5 )、二塩化二酸化モリブデン(MoO 2 Cl 2 )、四塩化酸化モリブデン(MoOCl 4 )、および、ヘキサカルボニルモリブデン(Mo(CO) 6 )から選択されたMo含有前駆体とに、前記W含有層を暴露させることによって蒸着される、方法。
[形態8]
形態7に記載の方法であって、前記Mo含有前駆体への暴露中の基板温度は、550℃未満である、方法。
[形態9]
形態7に記載の方法であって、前記基板は、第1基板温度で前記還元剤に暴露され、第2基板温度で前記Mo含有前駆体に暴露され、前記第1基板温度は、前記第2基板温度よりも低い、方法。
[形態10]
形態9に記載の方法であって、前記還元剤は、ホウ素含有還元剤とシリコン含有還元剤との混合物である、方法。
[形態11]
方法であって、
第1基板温度で、基板を収容する処理チャンバに還元剤ガスを流して、前記基板上に共形還元剤層を形成する工程と、
第2基板温度で前記共形還元剤層をモリブデン含有前駆体に暴露させて、前記還元剤層をモリブデンに変換する工程と、
を備える、方法。
[形態12]
形態11に記載の方法であって、前記第1基板温度は、前記第2基板温度より低い、方法。
[形態13]
形態11または12に記載の方法であって、前記還元剤は、ホウ素含有還元剤とシリコン含有還元剤との混合物である、方法。
[形態14]
形態11または12に記載の方法であって、前記第1基板温度は400℃以下であり、前記第2基板温度は500℃以上である、方法。
[形態15]
形態11または12に記載の方法であって、さらに、前記モリブデンをアニールする工程を備える、方法。
[形態16]
方法であって、
還元剤をパルス供給する工程であって、前記還元剤は、ホウ素(B)含有、シリコン(Si)含有、または、ゲルマニウム(Ge)含有である、工程と、
Mo含有前駆体をパルス供給する工程であって、
前記Mo含有前駆体は、前記還元剤または前記還元剤の生成物によって還元されて、B、Si、および、Geの内の1以上を含む多成分タングステン含有膜を前記基板上に形成する、工程と、
を備える、方法。
[形態17]
形態16に記載の方法であって、前記多成分タングステン含有膜は、5%~60%(原子%)のB、Si、または、Geを含み、前記5%~60%(原子%)のB、Si、または、Geは、前記還元剤によって供給される、方法。
Claims (4)
- モリブデンを含有する膜を形成する方法であって、
上に誘電体材料が形成された基板を提供する工程と、
前記誘電体材料上に核形成層を形成する工程と、
上に前記核形成層が形成された前記基板にモリブデン含有ガスおよび還元ガスを供給して、前記核形成層上にモリブデン膜を形成する工程と、
を備える、方法。 - 請求項1に記載の方法であって、前記核形成層を形成する工程は、前記基板を、(i)六フッ化タングステンガスおよびシリコン含有ガス、または、(ii)六フッ化タングステンガスおよびホウ素含有ガスのうちの少なくとも一方のガスに暴露する、方法。
- 請求項1の方法であって、前記モリブデン膜を蒸着する工程は、第1基板温度の第1動作および第2基板温度の第2動作を含み、前記第1基板温度は、前記第2基板温度よりも低い、方法。
- 請求項1の方法であって、
前記核形成層は、モリブデンを含む、方法。
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PCT/US2018/026746 WO2018191183A1 (en) | 2017-04-10 | 2018-04-09 | Low resistivity films containing molybdenum |
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TW201903847A (zh) | 2019-01-16 |
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CN110731003B (zh) | 2024-03-26 |
US20220223471A1 (en) | 2022-07-14 |
KR102572271B1 (ko) | 2023-08-28 |
CN110731003A (zh) | 2020-01-24 |
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