JP7274477B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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Description
1.第1の実施形態
1.1.半導体装置の構造例
1.2.半導体装置の製造方法例
1.3.半導体装置の変形例
2.第2の実施形態
2.1.固体撮像装置の第1の構造例
2.2.固体撮像装置の第2の構造例
2.3.固体撮像装置の第3の構造例
2.4.固体撮像装置の第4の構造例
3.応用例
(1.1.半導体装置の構造例)
まず、図1及び図2を参照して、本開示の第1実施形態に係る半導体装置の構造例について説明する。図1は、本開示の第1の実施形態に係る半導体装置の構造例を模式的に示す縦断面図である。
次に、図3~図4Dを参照して、本実施形態に係る半導体装置1の製造方法の一例について説明する。
続いて、図5A~図5Cを参照して、本実施形態に係る半導体装置1の変形例について説明する。図5A~図5Cは、第1~第3の変形例に係る半導体装置の構造例を模式的に示す縦断面図である。
図5Aに示すように、第1の変形例に係る半導体装置2Aは、第2配線間絶縁層220の内部に第2配線層230が設けられ、貫通ビア235によって第2配線層230及び第1配線層130が電気的に接続されている点が半導体装置1と異なる。第1の変形例に係る半導体装置2Aによれば、配線の引き回しをより多層化することが可能である。
図5Bに示すように、第2の変形例に係る半導体装置2Bは、凹部の内部に第1配線層130及び空隙150が形成された第1配線間絶縁層120がさらに繰り返し形成されている点が半導体装置2Aと異なる。第2の変形例に係る半導体装置2Bによれば、複数層に形成された配線の各々の配線間容量を低減することが可能である。
図5Cに示すように、第3の変形例に係る半導体装置2Cは、第5配線間絶縁層520、第5配線層530、第4配線間絶縁層420及び第4配線層430等が形成され、所定の機能を有する回路が形成された半導体基板500がさらに貼り合わせられている点が半導体装置2Bと異なる。第3の変形例に係る半導体装置2Cによれば、異なる機能を有する回路が形成された基板を積層した積層型半導体装置において、配線間容量を低減することが可能である。例えば、基板100には、複数の画素を配列した画素回路が設けられ、半導体基板500には、画素部にて光電変換された画素信号を情報処理するロジック回路が設けられてもよい。
(2.1.固体撮像装置の第1の構造例)
次に、図6A~図7Bを参照して、本開示の第2の実施形態に係る固体撮像装置の第1の構造例について説明する。図6Aは、本実施形態に係る固体撮像装置の第1の構造例を模式的に示す縦断面図である。図6Bは、本実施形態に係る固体撮像装置の画素回路を模式的に示す説明図である。図7A及び図7Bは、本実施形態に係る固体撮像装置の第1の構造例の平面配置を模式的に示す平面断面図である。
次に、図8を参照して、本実施形態に係る固体撮像装置の第2の構造例について説明する。図8は、本実施形態に係る固体撮像装置の第2の構造例を模式的に示す縦断面図である。
続いて、図9を参照して、本実施形態に係る固体撮像装置の第3の構造例について説明する。図9は、本実施形態に係る固体撮像装置の第3の構造例を模式的に示す縦断面図である。
次に、図10を参照して、本実施形態に係る固体撮像装置の第4の構造例について説明する。図10は、本実施形態に係る固体撮像装置の第4の構造例を模式的に示す縦断面図である。
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、内視鏡手術システムに応用されてもよい。
例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。
(1)
基板上に設けられ、前記基板と反対側に凹部を有する第1配線間絶縁層と、
前記第1配線間絶縁層の前記凹部の内部に設けられた第1配線層と、
前記第1配線層及び前記第1配線間絶縁層の凹凸形状に沿って設けられた封止膜と、
前記第1配線間絶縁層の上に前記凹部を覆うように設けられ、前記凹部に向き合う面が平坦である第2配線間絶縁層と、
前記第2配線間絶縁層と、前記第1配線層及び前記第1配線間絶縁層との間に設けられた空隙と、
を備える、半導体装置。
(2)
前記第1配線層は、前記凹部の底面から凸となるように設けられる、前記(1)に記載の半導体装置。
(3)
一部の前記第1配線層の高さは、前記第1配線間絶縁層の高さよりも低く、
前記空隙は、前記第2配線間絶縁層と、一部の前記第1配線層との間にさらに設けられる、
前記(2)に記載の半導体装置。
(4)
前記第1配線層は、前記凹部の内部に複数設けられ、
前記空隙は、複数の前記第1配線層の間に連続して設けられる、
前記(1)~(3)のいずれか一項に記載の半導体装置。
(5)
前記第1配線間絶縁層と、前記第2配線間絶縁層との間の接合面には、前記封止膜が設けられる、前記(1)~(4)のいずれか一項に記載の半導体装置。
(6)
前記第2配線間絶縁層の表面には、シリコン酸化膜又はシリコン窒化膜が設けられる、前記(1)~(5)のいずれか一項に記載の半導体装置。
(7)
前記第1配線間絶縁層と接する前記第1配線層の表面には、チタン、タンタル、ルテニウム又はコバルトのいずれかの元素を含むバリア層が設けられる、前記(1)~(6)のいずれか一項に記載の半導体装置。
(8)
前記第2配線間絶縁層の上には、第2配線層がさらに設けられ、
前記第2配線間絶縁層と、前記第1配線層とが接する領域には、前記第2配線間絶縁層を貫通して設けられ、前記第2配線層と、前記第1配線層とを電気的に接続する貫通ビアがさらに設けられる、
前記(1)~(7)のいずれか一項に記載の半導体装置。
(9)
前記第2配線間絶縁層は、前記基板と反対側に凹部を有し、
前記第2配線層は、前記第2配線間絶縁層の前記凹部の内部に設けられ、
前記第2配線間絶縁層の上には、前記第2配線間絶縁層の前記凹部を覆うように設けられ、前記凹部と対向する面が平坦である第3配線間絶縁層がさらに設けられ、
前記第3配線間絶縁層と、前記第2配線層及び前記第2配線間絶縁層との間には、空隙がさらに設けられる、
前記(8)に記載の半導体装置。
(10)
所定の機能を有する回路が形成された半導体基板と、前記半導体基板上に積層された多層配線層と、を有する積層基板をさらに備え、
前記積層基板は、前記多層配線層と、前記第2配線間絶縁層が設けられた側の面とが対向するように前記基板と貼り合わされる、
前記(1)~(9)のいずれか一項に記載の半導体装置。
(11)
前記半導体基板又は前記基板には、複数の画素を配列した画素部が設けられる、前記(10)に記載の半導体装置。
(12)
前記半導体基板には、ロジック回路が設けられ、
前記基板には、前記画素部が設けられる、
前記(11)に記載の半導体装置。
(13)
前記第1配線層は、前記複数の画素の各々に対応する光電変換素子からの電荷を蓄積するフローティングディフュージョン配線を含む、前記(12)に記載の半導体装置。
(14)
前記第1配線層は、前記複数の画素からの画素信号を伝送する垂直信号線を含む、前記(12)又は(13)に記載の半導体装置。
(15)
基板上に、前記基板と反対側に第1配線層を埋め込んだ第1配線間絶縁層を形成することと、
前記第1配線間絶縁層に凹部を形成し、前記凹部の内部にて前記第1配線層を露出させることと、
前記第1配線層及び前記第1配線間絶縁層の凹凸形状に沿って封止膜を設けることと、
前記第1配線間絶縁層の上に前記凹部を覆うように、前記凹部に向き合う面が平坦である第2配線間絶縁層を設け、前記第2配線間絶縁層と、前記第1配線層及び前記第1配線間絶縁層との間に空隙を形成することと、
を含む、半導体装置の製造方法。
100 基板
110 層間絶縁膜
120 第1配線間絶縁層
130 第1配線層
131 バリア層
132 キャップ層
140 封止膜
150 空隙
200 対向基板
211、212 層間絶縁膜
220 第2配線間絶縁層
160 貫通ビア
Claims (14)
- 基板上に設けられ、前記基板と反対側に凹部を有する第1配線間絶縁層と、
前記第1配線間絶縁層の前記凹部の内部に設けられた第1配線層と、
前記第1配線層及び前記第1配線間絶縁層の凹凸形状に沿って設けられた封止膜と、
前記第1配線間絶縁層の上に前記凹部を覆うように設けられ、前記凹部に向き合う面が平坦である第2配線間絶縁層と、
前記第2配線間絶縁層と、前記第1配線層及び前記第1配線間絶縁層との間に設けられた空隙と、
を備え、
一部の前記第1配線層の高さは、前記第1配線間絶縁層の高さよりも低く、
前記第2配線間絶縁層と前記一部の第1配線層との間に挟まれるように、他の空隙がさらに設けられている、
半導体装置。 - 前記第1配線層は、前記凹部の底面から凸となるように設けられる、請求項1に記載の半導体装置。
- 前記第1配線層は、前記凹部の内部に複数設けられ、
前記空隙は、複数の前記第1配線層の間に連続して設けられる、
請求項1又は2に記載の半導体装置。 - 前記第1配線間絶縁層と、前記第2配線間絶縁層との間の接合面には、前記封止膜が設けられる、請求項1~3のいずれか1項に記載の半導体装置。
- 前記第2配線間絶縁層の表面には、シリコン酸化膜又はシリコン窒化膜が設けられる、請求項1~4のいずれか1項に記載の半導体装置。
- 前記第1配線間絶縁層と接する前記第1配線層の表面には、チタン、タンタル、ルテニウム又はコバルトのいずれかの元素を含むバリア層が設けられる、請求項1~5のいずれか1項に記載の半導体装置。
- 前記第2配線間絶縁層の上には、第2配線層がさらに設けられ、
前記第2配線間絶縁層と、前記第1配線層とが接する領域には、前記第2配線間絶縁層を貫通して設けられ、前記第2配線層と、前記第1配線層とを電気的に接続する貫通ビアがさらに設けられる、
請求項1~6のいずれか1項に記載の半導体装置。 - 前記第2配線間絶縁層は、前記基板と反対側に凹部を有し、
前記第2配線層は、前記第2配線間絶縁層の前記凹部の内部に設けられ、
前記第2配線間絶縁層の上には、前記第2配線間絶縁層の前記凹部を覆うように設けられ、前記凹部と対向する面が平坦である第3配線間絶縁層がさらに設けられ、
前記第3配線間絶縁層と、前記第2配線層及び前記第2配線間絶縁層との間には、空隙がさらに設けられる、
請求項7に記載の半導体装置。 - 所定の機能を有する回路が形成された半導体基板と、前記半導体基板上に積層された多層配線層と、を有する積層基板をさらに備え、
前記積層基板は、前記多層配線層と、前記第2配線間絶縁層が設けられた側の面とが対向するように前記基板と貼り合わされる、
請求項1~8のいずれか1項に記載の半導体装置。 - 前記半導体基板又は前記基板には、複数の画素を配列した画素部が設けられる、請求項9に記載の半導体装置。
- 前記半導体基板には、ロジック回路が設けられ、
前記基板には、前記画素部が設けられる、
請求項10に記載の半導体装置。 - 前記第1配線層は、前記複数の画素の各々に対応する光電変換素子からの電荷を蓄積するフローティングディフュージョン配線を含む、請求項11に記載の半導体装置。
- 前記第1配線層は、前記複数の画素からの画素信号を伝送する垂直信号線を含む、請求項11又は12に記載の半導体装置。
- 基板上に、前記基板と反対側に第1配線層を埋め込んだ第1配線間絶縁層を形成することと、
前記第1配線間絶縁層に凹部を形成し、前記凹部の内部にて前記第1配線層を露出させることと、
前記第1配線層及び前記第1配線間絶縁層の凹凸形状に沿って封止膜を設けることと、
前記第1配線間絶縁層の上に前記凹部を覆うように、前記凹部に向き合う面が平坦である第2配線間絶縁層を設け、前記第2配線間絶縁層と、前記第1配線層及び前記第1配線間絶縁層との間に空隙を形成することと、
を含み、
一部の前記第1配線層の高さが、前記第1配線間絶縁層の高さよりも低くなるように、前記第1配線層を形成し、前記第2配線間絶縁層と前記一部の第1配線層との間に挟まれるように、他の空隙をさらに形成することをさらに含む、
半導体装置の製造方法。
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JP2013165147A (ja) | 2012-02-10 | 2013-08-22 | Renesas Electronics Corp | 半導体装置および半導体装置の製造方法 |
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US20210118935A1 (en) | 2021-04-22 |
CN112219274A (zh) | 2021-01-12 |
US11901392B2 (en) | 2024-02-13 |
US11515351B2 (en) | 2022-11-29 |
US20230073800A1 (en) | 2023-03-09 |
WO2020004065A1 (ja) | 2020-01-02 |
JPWO2020004065A1 (ja) | 2021-08-02 |
TWI823955B (zh) | 2023-12-01 |
DE112019003245T5 (de) | 2021-04-08 |
TW202015207A (zh) | 2020-04-16 |
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