JP6694252B2 - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JP6694252B2 JP6694252B2 JP2015179064A JP2015179064A JP6694252B2 JP 6694252 B2 JP6694252 B2 JP 6694252B2 JP 2015179064 A JP2015179064 A JP 2015179064A JP 2015179064 A JP2015179064 A JP 2015179064A JP 6694252 B2 JP6694252 B2 JP 6694252B2
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- oxide
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- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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Description
本発明の一態様は、絶縁体を形成し、絶縁体上に層を形成し、層を介して絶縁体に酸素を添加した後、層を除去し、酸素の添加された絶縁体上に酸化物半導体を形成し、酸化物半導体を有する半導体素子を形成する半導体装置の作製方法である。
または、本発明の一態様は、(1)において、酸化物半導体を形成した後、加熱処理を行う半導体装置の作製方法である。
または、本発明の一態様は、(1)または(2)において、層は、酸化物半導体を有する半導体装置の作製方法である。
または、本発明の一態様は、(1)乃至(3)のいずれか一において、層の除去は、ウェットエッチング法によって行う半導体装置の作製方法である。
または、本発明の一態様は、(1)乃至(4)のいずれか一において、絶縁体は、シリコンを有する酸化物であることを特徴とする半導体装置の作製方法である。
または、本発明の一態様は、(1)乃至(5)のいずれか一において、加熱処理によって酸化物半導体中の水素と絶縁体中の酸素とを反応させ、水として脱離させる半導体装置の作製方法である。
または、本発明の一態様は、(1)乃至(6)のいずれか一において、酸素の添加は、イオン注入法によって行う半導体装置の作製方法である。
または、本発明の一態様は、(1)乃至(7)のいずれか一において、半導体素子がトランジスタである半導体装置の作製方法である。
以下では、本発明の一態様に係る半導体装置について説明する。
以下では、本発明の一態様に係る半導体素子の一種であるトランジスタについて説明する。
半導体406の上下に半導体を配置することで、トランジスタの電気特性を向上させることができる場合がある。以下では、半導体406、およびその上下に配置する半導体について、図13を用いて詳細に説明する。
以下では、酸化物半導体の構造について説明する。
まずは、CAAC−OSについて説明する。なお、CAAC−OSを、CANC(C−Axis Aligned nanocrystals)を有する酸化物半導体と呼ぶこともできる。
次に、微結晶酸化物半導体について説明する。
次に、非晶質酸化物半導体について説明する。
なお、酸化物半導体は、nc−OSと非晶質酸化物半導体との間の構造を有する場合がある。そのような構造を有する酸化物半導体を、特に非晶質ライク酸化物半導体(a−like OS:amorphous−like Oxide Semiconductor)と呼ぶ。
以下では、CAAC−OSおよびnc−OSの成膜モデルの一例について説明する。
以下では、本発明の一態様に係るトランジスタなどを利用した半導体装置の一例について説明する。
図14(A)に示す回路図は、pチャネル型のトランジスタ2200とnチャネル型のトランジスタ2100を直列に接続し、かつそれぞれのゲートを接続した、いわゆるCMOSインバータの構成を示している。
図15は、図14(A)に対応する半導体装置の断面図である。図15に示す半導体装置は、トランジスタ2200と、トランジスタ2100と、を有する。また、トランジスタ2100は、トランジスタ2200の上方に配置する。なお、トランジスタ2100として、図6に示したトランジスタを用いた例を示しているが、本発明の一態様に係る半導体装置は、これに限定されるものではない。例えば、図7、図11または図12に示したトランジスタなどを、トランジスタ2100として用いても構わない。よって、トランジスタ2100については、適宜上述したトランジスタについての記載を参酌する。
また図14(B)に示す回路図は、トランジスタ2100とトランジスタ2200のそれぞれのソースとドレインを接続した構成を示している。このような構成とすることで、いわゆるCMOSアナログスイッチとして機能させることができる。
本発明の一態様に係るトランジスタを用いた、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置(記憶装置)の一例を図18に示す。
図19は、図18(A)に対応する半導体装置の断面図である。図19に示す半導体装置は、トランジスタ3200と、トランジスタ3300と、容量素子3400と、を有する。また、トランジスタ3300および容量素子3400は、トランジスタ3200の上方に配置する。なお、トランジスタ3300としては、上述したトランジスタ2100についての記載を参照する。また、トランジスタ3200としては、図15に示したトランジスタ2200についての記載を参照する。なお、図15では、トランジスタ2200がpチャネル型トランジスタである場合について説明したが、トランジスタ3200がnチャネル型トランジスタであっても構わない。
図18(B)に示す半導体装置は、トランジスタ3200を有さない点で図18(A)に示した半導体装置と異なる。この場合も図18(A)に示した半導体装置と同様の動作により情報の書き込みおよび保持動作が可能である。
以下では、本発明の一態様に係る撮像装置について説明する。
撮像装置200が有する1つの画素211を複数の副画素212で構成し、それぞれの副画素212に特定の波長帯域の光を透過するフィルタ(カラーフィルタ)を組み合わせることで、カラー画像表示を実現するための情報を取得することができる。
以下では、シリコンを用いたトランジスタと、酸化物半導体を用いたトランジスタと、を用いて画素を構成する一例について説明する。
以下では、上述したトランジスタや上述した記憶装置などの半導体装置を含むCPUについて説明する。
以下では、本発明の一態様に係る表示装置について、図29および図30を用いて説明する。
本発明の一態様に係る半導体装置は、表示機器、パーソナルコンピュータ、記録媒体を備えた画像再生装置(代表的にはDVD:Digital Versatile Disc等の記録媒体を再生し、その画像を表示しうるディスプレイを有する装置)に用いることができる。その他に、本発明の一態様に係る半導体装置を用いることができる電子機器として、携帯電話、携帯型を含むゲーム機、携帯データ端末、電子書籍端末、ビデオカメラ、デジタルスチルカメラ等のカメラ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、ナビゲーションシステム、音響再生装置(カーオーディオ、デジタルオーディオプレイヤー等)、複写機、ファクシミリ、プリンタ、プリンタ複合機、現金自動預け入れ払い機(ATM)、自動販売機などが挙げられる。これら電子機器の具体例を図31に示す。
105 層
106 半導体
120 酸素イオン
130 過剰酸素
132 ダメージ
134 水素
136 水
138 酸素欠損
200 撮像装置
201 スイッチ
202 スイッチ
203 スイッチ
210 画素部
211 画素
212 副画素
212B 副画素
212G 副画素
212R 副画素
220 光電変換素子
230 画素回路
231 配線
247 配線
248 配線
249 配線
250 配線
253 配線
254 フィルタ
254B フィルタ
254G フィルタ
254R フィルタ
255 レンズ
256 光
257 配線
260 周辺回路
270 周辺回路
280 周辺回路
290 周辺回路
291 光源
300 シリコン基板
310 層
320 層
330 層
340 層
351 トランジスタ
352 トランジスタ
353 トランジスタ
360 フォトダイオード
361 アノード
363 低抵抗領域
370 プラグ
371 配線
372 配線
373 配線
380 絶縁体
400 基板
402 絶縁体
404 導電体
406 半導体
406a 半導体
406c 半導体
408 絶縁体
412 絶縁体
413 導電体
414 導電体
416 導電体
416a 導電体
416b 導電体
418 絶縁体
442 絶縁体
450 半導体基板
452 絶縁体
454 導電体
456 領域
460 領域
462 絶縁体
464 絶縁体
466 絶縁体
468 絶縁体
472a 領域
472b 領域
474a 導電体
474b 導電体
474c 導電体
476a 導電体
476b 導電体
478a 導電体
478b 導電体
478c 導電体
480a 導電体
480b 導電体
480c 導電体
490 絶縁体
492 絶縁体
494 絶縁体
496a 導電体
496b 導電体
496c 導電体
496d 導電体
498a 導電体
498b 導電体
498c 導電体
498d 導電体
700 基板
704a 導電体
704b 導電体
706 半導体
712a 絶縁体
712b 絶縁体
714a 導電体
714b 導電体
716a 導電体
716b 導電体
718a 絶縁体
718b 絶縁体
718c 絶縁体
719 発光素子
720 絶縁体
721 絶縁体
731 端子
732 FPC
733a 配線
734 シール材
735 駆動回路
736 駆動回路
737 画素
741 トランジスタ
742 容量素子
743 スイッチ素子
744 信号線
750 基板
751 トランジスタ
752 容量素子
753 液晶素子
754 走査線
755 信号線
781 導電体
782 発光層
783 導電体
784 隔壁
791 導電体
792 絶縁体
793 液晶層
794 絶縁体
795 スペーサ
796 導電体
797 基板
901 筐体
902 筐体
903 表示部
904 表示部
905 マイクロフォン
906 スピーカー
907 操作キー
908 スタイラス
911 筐体
912 筐体
913 表示部
914 表示部
915 接続部
916 操作キー
921 筐体
922 表示部
923 キーボード
924 ポインティングデバイス
931 筐体
932 冷蔵室用扉
933 冷凍室用扉
941 筐体
942 筐体
943 表示部
944 操作キー
945 レンズ
946 接続部
951 車体
952 車輪
953 ダッシュボード
954 ライト
1189 ROMインターフェース
1190 基板
1191 ALU
1192 ALUコントローラ
1193 インストラクションデコーダ
1194 インタラプトコントローラ
1195 タイミングコントローラ
1196 レジスタ
1197 レジスタコントローラ
1198 バスインターフェース
1199 ROM
1200 記憶素子
1201 回路
1202 回路
1203 スイッチ
1204 スイッチ
1206 論理素子
1207 容量素子
1208 容量素子
1209 トランジスタ
1210 トランジスタ
1213 トランジスタ
1214 トランジスタ
1220 回路
2100 トランジスタ
2200 トランジスタ
3001 配線
3002 配線
3003 配線
3004 配線
3005 配線
3200 トランジスタ
3300 トランジスタ
3400 容量素子
5100 ペレット
5100a ペレット
5100b ペレット
5101 イオン
5102 酸化亜鉛層
5103 粒子
5105a ペレット
5105a1 領域
5105a2 ペレット
5105b ペレット
5105c ペレット
5105d ペレット
5105d1 領域
5105e ペレット
5120 基板
5130 ターゲット
5161 領域
Claims (7)
- 絶縁体を形成し、
前記絶縁体上に層を形成し、
前記層を介して前記絶縁体に酸素を添加し、
前記層を除去し、
前記酸素が添加された前記絶縁体上に酸化物半導体を形成し、
前記酸化物半導体を有する半導体素子を形成する半導体装置の作製方法であって、
前記層は、半導体又は導電体を有することを特徴とする半導体装置の作製方法。 - 絶縁体を形成し、
前記絶縁体上に層を形成し、
前記層を介して前記絶縁体に酸素を添加し、
前記層を除去し、
前記酸素が添加された前記絶縁体上に第1の酸化物半導体を形成し、
前記第1の酸化物半導体を有する半導体素子を形成する半導体装置の作製方法であって、
前記層は、第2の酸化物半導体を有することを特徴とする半導体装置の作製方法。 - 請求項1において、前記酸化物半導体を形成した後、加熱処理を行うことを特徴とする半導体装置の作製方法。
- 請求項2において、前記第1の酸化物半導体を形成した後、加熱処理を行うことを特徴とする半導体装置の作製方法。
- 請求項1乃至請求項4のいずれか一において、
前記層の除去は、ウェットエッチング法によって行うことを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項5のいずれか一において、
前記酸素の添加は、イオン注入法によって行うことを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項6のいずれか一において、
前記半導体素子がトランジスタであることを特徴とする半導体装置の作製方法。
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JP6345023B2 (ja) | 2013-08-07 | 2018-06-20 | 株式会社半導体エネルギー研究所 | 半導体装置およびその作製方法 |
KR102232133B1 (ko) | 2013-08-22 | 2021-03-24 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
JP6467171B2 (ja) | 2013-09-17 | 2019-02-06 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP6440457B2 (ja) | 2013-11-07 | 2018-12-19 | 株式会社半導体エネルギー研究所 | 半導体装置 |
TWI721409B (zh) | 2013-12-19 | 2021-03-11 | 日商半導體能源研究所股份有限公司 | 半導體裝置 |
JP6488124B2 (ja) | 2013-12-27 | 2019-03-20 | 株式会社半導体エネルギー研究所 | 半導体装置 |
-
2015
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