JP6478943B2 - ファンアウト半導体パッケージ及びその製造方法 - Google Patents

ファンアウト半導体パッケージ及びその製造方法 Download PDF

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Publication number
JP6478943B2
JP6478943B2 JP2016093940A JP2016093940A JP6478943B2 JP 6478943 B2 JP6478943 B2 JP 6478943B2 JP 2016093940 A JP2016093940 A JP 2016093940A JP 2016093940 A JP2016093940 A JP 2016093940A JP 6478943 B2 JP6478943 B2 JP 6478943B2
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layer
connection member
disposed
insulating layer
redistribution
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Japanese (ja)
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JP2016213466A (ja
JP2016213466A5 (enExample
Inventor
ヒュン パク、ダエ
ヒュン パク、ダエ
キム、ハン
ヘオン ファ、カン
ヘオン ファ、カン
グヮン コ、ヨウン
グヮン コ、ヨウン
ホ シム、ジュン
ホ シム、ジュン
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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