JP6461482B2 - 半導体製造用の内部プラズマグリッド - Google Patents
半導体製造用の内部プラズマグリッド Download PDFInfo
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- JP6461482B2 JP6461482B2 JP2014076868A JP2014076868A JP6461482B2 JP 6461482 B2 JP6461482 B2 JP 6461482B2 JP 2014076868 A JP2014076868 A JP 2014076868A JP 2014076868 A JP2014076868 A JP 2014076868A JP 6461482 B2 JP6461482 B2 JP 6461482B2
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- 239000002784 hot electron Substances 0.000 description 4
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32422—Arrangement for selecting ions or species in the plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/3244—Gas supply means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32623—Mechanical discharge control means
- H01J37/32633—Baffles
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32715—Workpiece holder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Analytical Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Plasma Technology (AREA)
- Drying Of Semiconductors (AREA)
Description
本出願は、それぞれ、その全体が全ての目的のために参照により本明細書に組み込まれる、発明の名称を「INTERNAL PLASMA GRID FOR SEMICONDUCTOR FABRICATION(半導体製造用の内部プラズマグリッド)」とする、2013年4月5日出願の米国仮特許出願第61/809,246号に基づく優先権の利益を主張して2013年11月15日に出願された発明の名称を「INTERNAL PLASMA GRID FOR SEMICONDUCTOR FABRICATION(半導体製造用の内部プラズマグリッド)」とする米国特許出願第14/082,009号に基づく優先権の利益を主張する。
グリッドは、プラズマチャンバ内に配置されて、これにより、チャンバを上部サブチャンバと下部サブチャンバとに分割している。本明細書で記載するようなグリッドを備えるように改良するのに適したチャンバの一例は、カリフォルニア州フリーモント市所在のラムリサーチ社(Lam Research Corporation)による反応器Kiyoである。条件として、以下の説明では図1を参照することを想定することができ、これについてはさらに後述する。いくつかの実現形態において、グリッドは、反応チャンバの内部底面の上方、約1〜6インチ(25.4〜152.4mm)の間に、または基台などの基板支持部の上方、約1〜6インチの間(例えば、約1.5〜3インチ(38.1〜76.2mm)の間)に配置される。これらまたは他の実現形態において、グリッドは、反応チャンバの内部天井の下方、約1〜6インチの間(例えば、約1.5〜3インチの間)に配置することができる。多くの場合、天井には、誘電体窓が装備されている。
グリッドは、スロットを有する比較的薄い板である。加えて、一部の実施形態では、グリッドは、他の形状の孔または穿孔部を有することができる。この場合、グリッドは、孔とスロットとを併せて有する。グリッド構造の非限定的な例を、図2Aおよび図2Bに示している。グリッドに含まれる材料は、絶縁体、導体、またはそれらの組み合わせとすることができる。いくつかの実現形態において、グリッドは1つ以上の材料を含み、それらの材料には、限定するものではないが、金属と、ステンレス鋼、アルミニウム、チタンなどの金属合金と、セラミック、シリコン、炭化ケイ素、窒化ケイ素、およびそれらの組み合わせが含まれる。材料は、例えば耐食性のための陽極酸化または他の不動態化が施されていても、または施されていないものであってもよい。一部の例では、グリッドは、セラミック、ガラス、厳しいプラズマ環境に耐えることができる堅牢なポリマ、またはこれらの材料のいずれかによる複合材料などの絶縁性材料を含むことができる。一実施形態において、グリッドは、セラミックコーティングを有する金属材料で構成される。他のコーティングを用いることもできる。コーティングされたグリッドを用いることは、特に被エッチング層が揮発性である場合に有効である。いくつかの実現形態において、グリッドは、純粋なコーティングで被覆することができ、それには、例えば、Y2O3、YF3、YAG、窒化チタン、またはCeO2のコーティングが含まれるが、ただし、これらに限定されない。また、グリッドは、接地するか、フローティングとするか、またはバイアスすることができる。いくつかの実現形態において、接地されたグリッドは、陰極の拡張バイアス電流帰路として機能する。
グリッドは、プラズマチャンバを、2つのゾーン、すなわちプラズマ生成用のコイル(または他のプラズマ生成機構)に近接した上部ゾーンと、基板ホルダに近接した下部ゾーンとに、効果的に分割する。いくつかの実施形態において、上部ゾーンのプラズマは、比較的「高温」の高エネルギー電子を含んでいる。このプラズマは、しばしば電子−イオンプラズマとして特徴付けられる。いくつかの実施形態において、下部ゾーンのプラズマは、比較的「低温」の低エネルギー電子を含んでいる。この下部ゾーン・プラズマは、しばしばイオン−イオンプラズマとして特徴付けられる。
いくつかの実現形態において、ウェハは処理中にバイアスされる。これは、ウェハを保持/支持するのに用いられる静電チャックにバイアスを印加することにより実現される。ウェハは、下部サブチャンバにおいて(イオン−イオンプラズマなどの)より低Teの低電子密度プラズマに暴露されるので、そのイオン−イオンプラズマに特有の効果が享受/促進されるように、チャックにバイアスを印加することができる。さらに、下部サブチャンバにおいて電子−イオンプラズマの形成が回避されるように、バイアスを印加することができる。例えば、バイアスは、電子−イオンプラズマの形成を防ぐのに適した周波数および電力とすることができ、その場合、イオン−イオンプラズマは、チャックバイアスにより与えられる電力を用いることなく形成される。例えば、基板へのバイアス電力の印加により発生する電子加熱量を抑えるように、RFバイアスは、約20MHz未満の周波数、好ましくは約100kHz〜約13.56MHzの間の周波数とすることができる。一部の実施形態では、(周波数にかかわらず)バイアスは、約1%〜99%の間のデューティサイクルで、約1Hz〜約10kHzの範囲でパルス化される。
本明細書で開示する装置およびプラズマ条件は、シリコン(多結晶、アモルファス、単結晶、および/または微結晶シリコンを含む)、金属(TiN、W、TaNなどを含むが、これらに限定されない)、酸化物および窒化物(SiO、SiOC、SiN、SiONなどを含むが、これらに限定されない)、有機物(フォトレジスト、アモルファスカーボンなどを含むが、これらに限定されない)など、様々な材料のいずれかをエッチングするために用いることができ、さらに他の様々な材料として、限定するものではないが、W、Pt、Ir、PtMn、PdCo、Co、CoFeB、CoFe、NiFe、W、Ag、Cu、Mo、TaSn、Ge2Sb2Te2、InSbTe Ag−Ge−S、Cu−Te−S、IrMn、および/またはRuが含まれる。このコンセプトは、NiOx、SrTiOx、ペロブスカイト(CaTiO3)、PrCaMnO3、PZT(PbZr1−xTixO3)、(SrBiTa)O3などの材料に拡張することができる。本装置は、現今の製造設備で使用可能な任意のガスの組み合わせ(HBr、CO、NH3、CH3OHなどを含む)で用いることが可能である。
本明細書で記載する方法は、任意の適切な装置によって実施することができる。適切な装置は、グリッド構造により上部サブチャンバと下部サブチャンバとに分割されたチャンバと、本明細書で記載するようなエッチング条件を提供および維持するための電子ハードウェアと、を備えるものである。適切な装置は、さらに、そのような条件を達成するようにハードウェアを制御するため、さらにはFETのゲート電極をエッチングするなどの応用に適した一連のプロセス工程を実行するための、命令を有するシステムコントローラを備える。いくつかの実施形態において、ハードウェアには、プロセスツールに含まれる1つ以上の処理ステーションを含むことができる。
いくつかの実施形態において、システムコントローラ(1つ以上の物理コントローラまたは論理コントローラを含むことができる)により、エッチングチャンバの動作の一部またはすべてを制御する。システムコントローラは、1つ以上のメモリデバイスと、1つ以上のプロセッサとを備えることができる。プロセッサは、中央処理装置(CPU)またはコンピュータ、アナログおよび/またはデジタル入力/出力接続、ステッピングモータ・コントローラボード、および他の同様の構成要素を含むことができる。適切な制御動作を実現するための命令が、プロセッサ上で実行される。これらの命令は、コントローラに関連付けられたメモリデバイスに格納されていてもよいし、あるいはネットワークを介して提供されるものであってもよい。いくつかの実施形態において、システムコントローラは、システム制御ソフトウェアを実行する。
本開示の方法および装置によって、半導体基板上の半製品のデバイスのエッチングが改善されることを、実験により確認した。プラズマグリッドを使用した場合には、エッチングされた製品は、良好な選択性、プロファイル角、疎/密ローディング、および全面エッチング均一性を示している。
Claims (28)
- 基板上のフィーチャをエッチングするための装置であって、
プラズマが提供され得る内部を画定するチャンバと、
エッチング中に前記チャンバ内で基板を保持するための基板ホルダと、
前記チャンバ内でプラズマを生成するためのプラズマ発生器と、
前記チャンバの内部を、前記プラズマ発生器に近接する上部サブチャンバと、前記基板ホルダに近接する下部サブチャンバと、に分割するグリッドと、
前記上部サブチャンバ内で上部ゾーン・プラズマを生成し、前記下部サブチャンバ内で下部ゾーン・プラズマを生成するという条件で、前記チャンバ内でプラズマを発生させるように設計または構成されているコントローラと、を備え、
前記上部ゾーン・プラズマのプラズマ電位は、前記下部ゾーン・プラズマのプラズマ電位よりも高く、
前記上部サブチャンバは、前記下部サブチャンバの高さの少なくとも約1/6の高さを有し、
前記グリッドは、略径方向外向きに延びる複数のスロットを有し、前記スロットにより、前記チャンバ内でプラズマが生成される際に前記グリッドに誘導電流が発生することを実質的に防止する、装置。 - 請求項1に記載の装置において、
前記下部ゾーン・プラズマの実効電子温度は、約1eV以下であって、前記上部ゾーン・プラズマの実効電子温度よりも低く、
前記下部ゾーン・プラズマの電子密度は、約5×109cm-3以下であって、前記上部ゾーン・プラズマの電子密度よりも低い、装置。 - 請求項1に記載の装置において、前記コントローラは、さらに、前記グリッドにバイアスを印加するように設計または構成されている、装置。
- 請求項1に記載の装置において、前記コントローラは、さらに、前記基板ホルダにバイアスを印加するように設計または構成されている、装置。
- 請求項1から請求項4のいずれか一項に記載の装置において、前記コントローラは、さらに、前記チャンバにエッチャントガスを供給するように設計または構成されている、装置。
- 請求項1から請求項5のいずれか一項に記載の装置において、前記コントローラは、さらに、前記プラズマにより前記基板をエッチングする間、前記チャンバ内の圧力を約267Pa未満とするように設計または構成されている、装置。
- 請求項1から請求項6のいずれか一項に記載の装置において、前記コントローラは、さらに、前記下部サブチャンバ内でイオン−イオンプラズマを発生させるように設計または構成されている、装置。
- 請求項1から請求項7のいずれか一項に記載の装置において、前記グリッドは、約1〜50mmの間の平均厚さを有する、装置。
- 請求項1から請求項8のいずれか一項に記載の装置において、前記グリッドの前記スロットは、幅に対する高さのアスペクト比が、約0.3〜5の間である、装置。
- 請求項1から請求項9のいずれか一項に記載の装置において、前記スロットは、隣接スロットから約60度以下の方位角で離間されている、装置。
- 請求項1から請求項10のいずれか一項に記載の装置において、前記プラズマ発生器は、前記チャンバの天井の上方に配置されているコイルを有する、装置。
- 請求項1から請求項11のいずれか一項に記載の装置において、前記基板ホルダは、静電チャックである、装置。
- 請求項1から請求項12のいずれか一項に記載の装置において、さらに、真空接続部を備える、装置。
- 半導体基板を処理するためのシステムであって、
真空搬送モジュールと、
前記真空搬送モジュール内のロボットと、
前記真空搬送モジュールにおけるファセットに接続される複数の処理モジュールと、
プロセッサを有するコントローラと、を備え、
前記複数の処理モジュールのうち少なくとも1つは、
プラズマが提供され得る内部を画定するチャンバと、
エッチング中に前記チャンバ内で基板を保持するための基板ホルダと、
前記チャンバ内でプラズマを生成するためのプラズマ発生器と、
前記チャンバの内部を、前記プラズマ発生器に近接する上部サブチャンバと、前記基板ホルダに近接する下部サブチャンバと、に分割するグリッドと、を備え、
前記コントローラは、上部サブチャンバ内で上部ゾーン・プラズマを生成し、前記下部サブチャンバ内で下部ゾーン・プラズマを生成するという条件で、前記チャンバ内でプラズマを発生させるように設計または構成され、前記上部ゾーン・プラズマのプラズマ電位は、前記下部ゾーン・プラズマのプラズマ電位よりも高く、
前記上部サブチャンバは、前記下部サブチャンバの高さの少なくとも約1/6の高さを有し、
前記グリッドは、略径方向外向きに延びる複数のスロットを有し、該スロットにより、前記チャンバ内でプラズマが生成される際に前記グリッドに誘導電流が発生することを実質的に防止する、システム。 - 半導体エッチング装置と関連して用いられるグリッドであって、
半導体デバイス製造用の標準的な半導体基板の直径と略同じ直径を有するプレートと、
前記プレートにおいて略径方向外向きに延びる複数のスロットであって、前記プレートがプラズマに暴露される際に前記プレートに誘導電流が発生することを実質的に防止するための複数のスロットと、を備え、
前記スロットは、幅に対する高さのアスペクト比が、約0.3〜5の間である、グリッド。 - 請求項15に記載のグリッドにおいて、前記グリッドは、半導体エッチング装置の処理チャンバ内に配置されると、前記処理チャンバを上部サブチャンバと下部サブチャンバとに分割し、前記上部サブチャンバ内で生成されるプラズマに曝されると、前記上部サブチャンバにおける上部電子密度よりも少なくとも約10倍低い前記下部サブチャンバの下部電子密度を維持するように機能する、グリッド。
- 請求項16に記載のグリッドにおいて、前記グリッドは、前記上部電子密度よりも少なくとも約100倍低い前記下部電子密度を維持するように機能する、グリッド。
- 請求項15から請求項17のいずれか一項に記載のグリッドにおいて、前記標準的な半導体基板は、約300mmまたは約450mmの直径を有する、グリッド。
- 請求項15から請求項18のいずれか一項に記載のグリッドにおいて、方位角的に隣接する方位角隣接スロットは、少なくとも約10°、かつ約60°以下で離間されている、グリッド。
- 請求項15から請求項19のいずれか一項に記載のグリッドにおいて、前記グリッドは、金属を含んでいる、グリッド。
- 請求項15から請求項19のいずれか一項に記載のグリッドにおいて、前記グリッドは、絶縁性材料を含んでいる、グリッド。
- 基板上のフィーチャをエッチングする方法であって、
チャンバ内の基板ホルダに基板を供給し、前記チャンバはプラズマ発生器とグリッドとを備え、前記グリッドは、前記チャンバの内部を前記プラズマ発生器に近接する上部サブチャンバと、前記基板ホルダに近接する下部サブチャンバとに分割し、前記上部サブチャンバは、前記下部サブチャンバの高さの少なくとも約1/6の高さを有し、
前記上部サブチャンバ内で上部ゾーン・プラズマを生成し、前記下部サブチャンバ内で下部ゾーン・プラズマを生成するという条件で、前記チャンバ内でプラズマを発生させ、
前記下部ゾーン・プラズマと前記基板との相互作用によって、前記基板のフィーチャをエッチングすること、を備え、
前記上部ゾーン・プラズマのプラズマ電位は、前記下部ゾーン・プラズマのプラズマ電位よりも高く、
前記下部ゾーン・プラズマの実効電子温度は、約1eV以下であって、前記上部ゾーン・プラズマの実効電子温度よりも低く、
前記下部ゾーン・プラズマの電子密度は、約5×109cm-3以下であって、前記上部ゾーン・プラズマの電子密度よりも低い、方法。 - 請求項22に記載の方法において、前記プラズマを発生させる際に、前記グリッドに電流は実質的に生じない、方法。
- 請求項22または請求項23に記載の方法において、さらに、前記グリッドにバイアスを印加することを備える、方法。
- 請求項22または請求項23に記載の方法において、さらに、前記基板ホルダにバイアスを印加することを備える、方法。
- 請求項22から請求項25のいずれか一項に記載の方法において、さらに、前記チャンバにエッチャントガスを供給することを備える、方法。
- 請求項22から請求項26のいずれか一項に記載の方法において、前記エッチングは、約267Pa未満のチャンバ圧力で実施される、方法。
- 請求項22から請求項27のいずれか一項に記載の方法において、前記下部ゾーン・プラズマは、イオン−イオンプラズマである、方法。
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TWI677025B (zh) | 2019-11-11 |
SG10201708121VA (en) | 2017-11-29 |
KR102284325B1 (ko) | 2021-08-02 |
KR20140121367A (ko) | 2014-10-15 |
CN107578973A (zh) | 2018-01-12 |
US10224221B2 (en) | 2019-03-05 |
TWI636481B (zh) | 2018-09-21 |
US20160141188A1 (en) | 2016-05-19 |
JP6506915B2 (ja) | 2019-04-24 |
SG10201401254VA (en) | 2014-11-27 |
US20140302680A1 (en) | 2014-10-09 |
TW201511066A (zh) | 2015-03-16 |
CN104103477A (zh) | 2014-10-15 |
JP2014239210A (ja) | 2014-12-18 |
CN104103477B (zh) | 2017-08-11 |
TW201511067A (zh) | 2015-03-16 |
CN104103478B (zh) | 2017-05-10 |
SG10201401112YA (en) | 2014-11-27 |
US11171021B2 (en) | 2021-11-09 |
US9245761B2 (en) | 2016-01-26 |
KR20140121368A (ko) | 2014-10-15 |
CN107578973B (zh) | 2020-03-13 |
KR102270841B1 (ko) | 2021-06-29 |
JP2014204127A (ja) | 2014-10-27 |
TW201836012A (zh) | 2018-10-01 |
US20140302681A1 (en) | 2014-10-09 |
CN104103478A (zh) | 2014-10-15 |
TWI665709B (zh) | 2019-07-11 |
US20160203990A1 (en) | 2016-07-14 |
US20160181130A1 (en) | 2016-06-23 |
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