JP6461482B2 - Internal plasma grid for semiconductor manufacturing - Google Patents

Description

[Cross-reference of related applications]
Each of the present applications is entitled “INTERNAL PLASMA GRID FOR SEMICONDUCTOR FABRICATION”, 2013, which is incorporated herein by reference in its entirety for all purposes. Claimed the benefit of the priority based on US Provisional Patent Application No. 61 / 809,246 filed on April 5, the name of the invention filed on November 15, 2013 is “INTERNAL PLASMA GRID FOR SEMICONDUCTOR FACRICATION” Claim of priority based on US patent application Ser. No. 14 / 082,009, “Internal Plasma Grid for Manufacturing”.

  One of the processes often employed in semiconductor manufacturing is an etching process. In the etching process, one or more materials are partially or completely removed from the semi-finished integrated circuit. Plasma etching is often used, especially when the geometry involved is small, a high aspect ratio is employed, or precise pattern transfer is required.

  In general, a plasma contains electrons, positive and negative ions, and several radicals. Radicals, positive ions, and negative ions interact with the substrate to etch features, surfaces, and materials on the substrate. In the etching process, the chamber coil performs the same function as the primary coil of the transformer, and the plasma functions similar to the secondary coil of the transformer.

  Moving from planar to 3D transistor structures (eg, FinFET gate structures for logic devices), the plasma etching process is required to be increasingly precise and uniform in order to produce good products. The plasma etch process must have good selectivity, profile angle, Iso / Dense loading, and overall uniformity, among other factors.

  The etching process is useful when the selectivity between the material being etched and the material being left is good. In the field of finFET gate structures, this means that the selectivity of the etched gate must be good with respect to other exposed parts such as a silicon nitride mask. The profile angle is measured as the angle between the most recently etched (substantially vertical) sidewall and the horizontal plane. For many applications, the ideal profile angle is 90 degrees and the opening is made by vertical etching. In some cases, the local feature density on the wafer can affect the etching process. For example, a wafer region with dense features may be etched (eg, it may be a faster, slower, more isotropic, more anisotropic etch) than a wafer region with less features. There may be a slight difference. The difference caused by the difference in feature density is called I / D loading. It is useful to minimize such differences during manufacturing. In addition to meeting these and other potential device specific requirements, it is often required that the etching process be performed consistently across the entire surface of the substrate (e.g., etching characteristics are Must be uniform from the center to the edge of the semiconductor wafer).

  In etching advanced structures such as finFET gates, it has been found difficult to achieve multiple objectives as described above.

  Disclosed herein are various methods and apparatus for etching a semiconductor substrate and layers thereon in the manufacture of semiconductor devices. In one aspect of the embodiments described herein, an apparatus for etching features on a substrate is provided. The apparatus includes a chamber defining an interior (chamber) in which plasma can be provided, a substrate holder for holding a substrate in the chamber during etching, a plasma generator for generating plasma in the chamber, and a plasma chamber A grid that divides the interior of the substrate into an upper sub-chamber adjacent to the plasma generator and a lower sub-chamber adjacent to the substrate holder, the upper sub-chamber being at least about 1/6 the height of the lower sub-chamber. The grid has a plurality of slots extending substantially radially outward, and these slots substantially prevent an induced current from being generated in the grid when plasma is generated in the chamber.

The apparatus further comprises a controller designed or configured to generate plasma in the chamber provided that the upper zone plasma is generated in the upper sub-chamber and the lower zone plasma is generated in the lower sub-chamber. The effective electron temperature of the lower zone plasma is about 1 eV or less, which is lower than the effective electron temperature of the upper zone plasma, and the electron density of the lower zone plasma is about 5 × 10 ⁹ cm ^{−. 3} or less, lower than the electron density of the upper zone plasma. The controller can further be designed and configured to apply a bias to the grid and / or substrate holder. The controller can further be designed and configured to supply an etchant gas to the chamber. In some examples, the controller, while etching the substrate by the plasma, designed or configured the pressure in the chamber about 267Pa to less than (2000 milliTorr (mTorr)). However, in some examples, the controller is designed or configured to provide a lower pressure within the chamber being etched, such as a pressure of less than about 26.7 Pa ( 200 millitorr ) . In other examples, the controller maintains the pressure in the reaction chamber between about 0.133 to 2.67 Pa ( 1 to 20 mTorr ) , or between about 0.667 to 2.67 Pa ( 5 to 20 mTorr ). Can be designed or configured to. The controller can further be designed or configured to generate an ion-ion plasma in the lower sub-chamber.

  In some embodiments, the grid can have an average thickness between about 1-50 mm, or between about 5-20 mm. The slots in the grid typically have an aspect ratio between about 0.3-5. In some embodiments, the aspect ratio of the slot is between about 0.5-2, or between about 1-4. The slots are often arranged to extend radially outward. In some cases, azimuthally adjacent azimuth adjacent slots are separated by at least about 15 °. In these or other examples, azimuthal adjacent slots can be spaced apart by about 60 ° or less, for example, can be spaced apart by about 50 ° or less.

  The plasma generator in some embodiments has a coil disposed above the ceiling of the chamber. In some embodiments, the substrate holder is an electrostatic chuck. The device can include various other elements. For example, the apparatus can further comprise a process gas inlet. Furthermore, the device can comprise a vacuum connection.

  In a further aspect of the disclosed embodiment, a system for processing a semiconductor substrate is provided. The system can include a vacuum transfer module, a robot in the vacuum transfer module, a plurality of stations connected to the vacuum transfer module, and a controller having a processor, at least one of the plurality of stations being: A chamber defining an interior capable of applying plasma, a substrate holder for holding a substrate in the chamber during etching, a plasma generator for generating plasma in the chamber, and an interior of the plasma chamber A grid that divides into an upper sub-chamber adjacent to the plasma generator and a lower sub-chamber close to the substrate holder, the upper sub-chamber having a height of at least about 1/6 of the height of the lower sub-chamber, and The grid has a plurality of slots extending substantially radially outward, and the slots Ri, induced in the grid current substantially prevented from occurring when the plasma is generated within the chamber.

  In some embodiments, the station is interfaced to facets in the vacuum transfer module. Multiple sensors can be provided at each facet.

  In yet another aspect of the embodiments described herein, a grid for use in connection with a semiconductor etching apparatus is disclosed, which has a diameter that is approximately the same as the diameter of a standard semiconductor substrate for semiconductor device manufacturing. A plate and a plurality of slots extending substantially radially outward in the plate, the plurality of slots for substantially preventing an induced current from being generated in the plate when the plate is exposed to plasma, The slot has an aspect ratio that is between about 0.3-5.

  When the grid is placed in the processing chamber of the semiconductor etching apparatus, it divides the processing chamber into an upper sub-chamber and a lower sub-chamber and is exposed to plasma generated in the upper sub-chamber, so that the upper portion of the upper sub-chamber is exposed. It functions to maintain the lower electron density of the lower sub-chamber at least about 10 times lower than the electron density. In some embodiments, the grid can function to maintain a lower electron density that is at least about 100 times lower than the upper electron density. In many cases, standard semiconductor substrates have a diameter of about 200 mm, 300 mm, or 450 mm. The azimuth adjacent slots can be spaced at least about 10 °. Also, the azimuth adjacent slots can be separated by about 60 ° or less. In some embodiments, the grid is composed of metal. In another example, the grid is made of an insulating material. In some examples, the grid can include both metal and insulating materials.

In another aspect of the embodiments described herein, a method for etching features on a substrate is provided, the method comprising a chamber comprising a plasma generator and a grid, the grid being an interior of the plasma chamber. Is divided into an upper sub-chamber close to the plasma generator and a lower sub-chamber close to the substrate holder, the upper sub-chamber having a height at least about 1/6 of the height of the lower sub-chamber in the chamber. Supplying a substrate to the substrate holder; generating a plasma in the chamber under the condition that an upper zone plasma is generated in the upper sub-chamber and a lower zone plasma is generated in the lower sub-chamber; Etching the features of the substrate by the interaction of the plasma and the substrate; Seen, this time, the effective electron temperature of the lower zone plasma is a less than or equal to about 1 eV, lower than the effective electron temperature of the upper zone plasma, also, the electron density of the lower zone plasma, about 5 × 10 ⁹ Less than cm ^{-3 and} lower than the electron density of the upper zone plasma.

  In some examples, substantially no current is generated in the grid when generating the plasma. The method can further include applying a bias to the grid and / or applying a bias to the substrate holder. In some embodiments, the method further includes supplying an etchant gas to the chamber. Etching can be performed at a chamber pressure of less than about 2000 millitorr, and in some examples, etching is between about 1-200 millitorr, or between about 1-20 millitorr, or about 5-20 millitorr. It is carried out at a chamber pressure between. The lower zone plasma may be an ion-ion plasma as described herein.

  These and other features are described below with reference to the associated drawings.

1 is a cross-sectional schematic diagram illustrating a plasma processing system used in an etching process according to some embodiments disclosed herein. FIG.

1 is a simplified top view of a grid structure according to some embodiments disclosed herein. FIG.

2 is a photograph of a grid structure according to some embodiments described herein.

It is explanatory drawing which shows some problems which arise by dissociation of an etching by-product. It is explanatory drawing which shows some problems which arise by dissociation of an etching by-product. It is explanatory drawing which shows some problems which arise by dissociation of an etching by-product.

FIG. 6 is an illustration showing an embodiment of a multi-station cluster tool according to disclosed embodiments.

It is explanatory drawing which shows the SEM image of the fin FET structure etched by the conventional high voltage | pressure technique (FIG. 5A). It is explanatory drawing which shows the SEM image of the fin FET structure etched by one Embodiment (FIG. 5B) using a plasma grid.

It is explanatory drawing which shows the SEM image of the feature etched by the conventional low voltage | pressure technique (FIG. 6A). FIG. 6 is an illustration showing an SEM image of an etched feature, according to one embodiment of the present disclosure (FIG. 6B) using a plasma grid.

FIG. 6 is an illustration showing various SEM images of features etched according to several regimes without using a plasma grid.

  In this application, the terms “semiconductor wafer”, “wafer”, “substrate”, “wafer substrate”, and “semi-finished integrated circuit” are used interchangeably. One skilled in the art will appreciate that the term “semi-finished integrated circuit” can refer to a device on a semiconductor wafer at any of the many stages upon which the integrated circuit is fabricated. In the following detailed description, it is assumed that the present invention is implemented on a wafer. Exemplary workpieces include 200 mm, 300 mm, and 450 mm diameter semiconductor substrates (sometimes referred to as standard semiconductor substrates). However, the present invention is not limited to this. The workpiece can be of various shapes, sizes and materials.

  In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments presented. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments are described in connection with specific embodiments, it should be understood that they are not intended to limit the disclosed embodiments.

  An apparatus for use in etching a semiconductor substrate and layers formed thereon in the manufacture of a semiconductor device is disclosed. The apparatus is defined by the chamber in which the etching is performed. In some embodiments, the chamber comprises a planar window, a substantially planar excitation coil, and a base or chuck for holding the semiconductor substrate during etching. Of course, the present disclosure is not limited to a particular type of plasma source. In addition to the planar excitation coil, dome type and flat type plasma sources can be employed. Plasma sources include inductively coupled plasma (ICP) sources, capacitively coupled plasma (CCP) sources, and others well known to those skilled in the art. The embodiments described herein utilize a grid that is disposed within the chamber and divides the chamber into two sub-chambers. In operation, each subchamber contains a plasma of different characteristics. The plasma is generated primarily or exclusively in the upper subchamber, and some species can pass through the grid without impact and enter the lower subchamber. The grid has slots that penetrate the thickness of the grid. In some implementations, these slots extend generally / substantially radially outward. As used herein, “extends generally radially outward” means that the feature being described has at least some radial component. That is, it is only necessary that the main part of the feature part extends in the direction from the substantially center to the edge, and it is not necessary that the whole feature part is oriented in the radial direction. Also, “center to edge direction” is defined to include a range of angles around the true direction from the center to the edge (eg, within about 20 ° of the true direction from the center to the edge). Is done.

The grid can include a plurality of radial slots through the thickness of the grid. The grid and slot are designed so that only a few high energy electrons can pass through the grid, and the passage of low energy electrons is effectively blocked by the sheath surrounding the grid. In general, higher energy electrons become lower energy “cold” electrons as they pass through the grid and enter the lower subchamber. Although high-energy electrons can have enough energy to pass through the grid, many of them approach the grid at an angle that collides with the grid and lose energy. The high energy electrons that actually pass through the grid are already disconnected from the excitation source and therefore collectively do not have enough energy to maintain the plasma under the grid. The mechanisms by which hot electrons cool down in the lower chamber include collisions with the grid, collisions with neutral species under the grid, and elimination of the excitation source from electrons under the grid. included. Thus, the grid may have the function of generating a low electron density (n _e ) and low average effective electron temperature (T _e ) plasma in the lower subchamber. Above the grid, in general, the plasma is a normal electron-ion plasma, and a very large portion of the negatively charged species in it is electrons. Below the grid, the plasma contains a much higher percentage of negative ions and may actually be an ion-ion plasma. Some characteristics of the ion-ion plasma will be described later. Broadly speaking, ion-ion plasmas contain a much higher proportion of ions (rather than electrons) as negatively charged species compared to electron-ion plasmas.

[Position of the grid in the reactor]
The grid is disposed within the plasma chamber, thereby dividing the chamber into an upper subchamber and a lower subchamber. One example of a chamber suitable for modification to include a grid as described herein is a reactor Kiyo from Lam Research Corporation, Fremont, California. As conditions, it can be assumed in the following description that reference is made to FIG. 1, which will be further described later. In some implementations, the grid is between about 1-6 inches (25.4-152.4 mm) above the inner bottom surface of the reaction chamber, or above a substrate support such as a base, about 1- Between 6 inches (e.g. between about 1.5 to 3 inches (38.1 to 76.2 mm)). In these or other implementations, the grid can be positioned between about 1-6 inches (eg, between about 1.5-3 inches) below the internal ceiling of the reaction chamber. In many cases, the ceiling is equipped with a dielectric window.

In some embodiments, the height of the upper and lower subchambers is approximately the same (eg, within about 5%), while in other embodiments, their heights are more significantly different. obtain. The ratio of the height of the upper chamber to the height of the lower chamber ( _hu / _hl ), also called the subchamber height ratio, is between about 0.1-10, or between about 0.2-5. be able to. In some embodiments, the subchamber height ratio is greater than about 1/6.

  If the grid is too close to the wafer, it can cause grid marks on the wafer surface and should not be so arranged. That is, an undesirable grid slot pattern may occur on the processed wafer surface, causing severe etch non-uniformities on the substrate surface. In many applications, it is sufficient that the separation from the top surface of the substrate to the grid is at least about 1 inch.

[Grid design]
The grid is a relatively thin plate with slots. In addition, in some embodiments, the grid can have other shaped holes or perforations. In this case, the grid has both holes and slots. A non-limiting example of a grid structure is shown in FIGS. 2A and 2B. The material included in the grid can be an insulator, a conductor, or a combination thereof. In some implementations, the grid includes one or more materials, including but not limited to metals, metal alloys such as stainless steel, aluminum, titanium, and ceramic, silicon, carbonized. Silicon, silicon nitride, and combinations thereof are included. The material may or may not have been subjected to, for example, anodization or other passivation for corrosion resistance. In some examples, the grid can include an insulating material such as ceramic, glass, a robust polymer that can withstand harsh plasma environments, or a composite material from any of these materials. In one embodiment, the grid is composed of a metallic material having a ceramic coating. Other coatings can also be used. Using a coated grid is particularly effective when the layer to be etched is volatile. In some implementations, the grid can be coated with a pure coating, including, for example, a coating of Y ₂ O ₃ , YF ₃ , YAG, titanium nitride, or CeO ₂ , provided that It is not limited to these. The grid can also be grounded, floated, or biased. In some implementations, the grounded grid serves as an extended bias current return for the cathode.

  The grid when grounded generally extends across the entire horizontal cross section of the chamber. When the grid is biased, a spacing of about 5 cm or more can be maintained between the grid and the nearest ground plane. If the chamber is circular (viewed from above), the grid will also be circular. This allows the grid to effectively divide the reaction chamber into two subchambers. In some designs, the circular shape of the grid is defined by the geometry of the substrate, which is typically a circular wafer. As is well known, wafers are generally provided in a variety of sizes, such as 200 mm, 300 mm, and 450 mm. In the case of a square or smaller substrate, other shapes are possible depending on the etching process performed in the chamber. The cross section of the grid can have various shapes. A flat planar grid cross section is suitable for some embodiments. However, in other embodiments, grid cross sections such as a dish shape, a dome shape, a periodic shape (for example, a sine wave shape, a rectangular wave shape, a mountain shape), and an inclined shape are suitable. A slot or hole that passes through any of these cross-sectional shapes will have characteristics (including aspect ratios) as described elsewhere herein.

  The grid on average can be between about 1-50 mm thick, preferably between about 5-20 mm thick. If the grid is too thick, it may not function properly (e.g., there are too many species blocked from passing through, too much mass, too much space occupied by the reaction chamber, etc.). If the grid is too thin, it may not be able to withstand the plasma treatment and may require fairly frequent replacement. Since the slot height is determined by the grid thickness, the grid thickness is also limited by the desired aspect ratio of the slots in the grid, as described below.

  In some embodiments, the grid functions as a separator between the upstream plasma and the downstream plasma, where the downstream plasma is in the lower subchamber and can be radical rich. Thus, the grid-equipped plasma chamber allows existing remote plasmas, such as the GAMMA® platform tool currently available from Novellus Systems, Lam Research, Fremont, California. • You can get results similar to those achieved with the tool. When functioning for this purpose, the grid can be relatively thick, for example about 20-50 mm thick.

  In some embodiments, the grid has slots, which in one exemplary embodiment have a long and thin shape. The slot extends radially outward from the center of the grid. The slot has a height, width, and thickness (width and length are clearly labeled in FIG. 2A). The slot height is measured along an axis perpendicular to the grid plane, and this height is approximately equal to the thickness of the grid. The width of the slot can be variable or constant over the radial range of the slot. In some examples, the slots can be fan-shaped (ie, thinner toward the center of the grid and thicker toward the edges). In some embodiments, the slots extend outward (i.e., radially) in the length direction from the center of the grid. In some embodiments, the slot width is about 25 mm or less. The length of the slot can be varied or constant approximately in the azimuthal direction of the grid. The separation angle of the radial slots can be variable or constant around the grid.

  If there are no slots in the grid, current will be induced in the grid during plasma generation. This current will flow approximately annularly around the grid or form a local eddy current and power consumption will increase. However, the presence of the slot prevents such parasitic currents from being generated, thereby saving power and resulting in a more efficient process. An opening having a shape such as a substantially circular hole may have a relatively low effect of preventing the generation of such current. Therefore, as described above, the circular opening can be used together with the slot-like opening.

  The aspect ratio of a slot is defined as the ratio of its height to the width of the slot (h / w). Typically, this aspect ratio geometry can be viewed as a cross-section perpendicular to the slot length direction (often radial). Since the slot width can be variable, the aspect ratio can be variable as well. In some embodiments, the aspect ratio of the slot is between about 0.3-5, or between about 1-4, or between about 0.5-2. In many embodiments, a grid having such an aspect ratio reduces the electron density and effective electron temperature in the lower subchamber compared to the upper subchamber. As described above, when the electrons pass through the slot, it is considered that the effective electron temperature is lowered at least due to the collision of many hot electrons with the grid. Also, since the electrons in the lower subchamber are shielded by the grid and do not receive induction heating from the plasma coil (or other plasma source), the effective electron temperature in the lower subchamber is lower than that in the upper subchamber. descend.

  If a hole is used with a slot, the hole can serve the same purpose as the slot. Therefore, they usually have the aspect ratio as described above. In some embodiments, the holes have a diameter ranging from about 0.05 (1.27 mm) inches to about 0.2 (5.08 mm) inches. They penetrate the entire thickness of the grid.

  A further effect obtained by the grid is that the convection effect from the main injector can be mitigated. As a result, the gas flow to the wafer surface can be made more uniform. Because of the grid between the wafer and the gas injector (s) in the upper chamber, the grid prevents gas flow, resulting in a more diffusive flow regime on the wafer. It is possible to significantly reduce the influence of convection of the gas delivered from the gas injector.

  In some embodiments, the grid includes gas ejection holes. In such an embodiment, the grid may serve the additional purpose of being a showerhead for the upper and / or lower subchamber. In such embodiments, one or more grids can include one or more channels. These channels can be supplied with gas from the inlet (or inlets) and delivered to the outlet holes of the grid (s). The outlet holes can form a gas distribution showerhead that delivers process gas to either or both of the upper and lower subchambers.

  In some implementations, the grid has a region, such as a central region that includes features that allow the probing device to be placed through the grid. A probing device may be provided to probe process parameters associated with the active plasma processing system. Probing processes can include emission endpoint detection, interferometric endpoint detection, plasma density measurement, ion density measurement, and other metrological probing operations. In some embodiments, the central region of the grid is open. In other embodiments, the central region of the grid includes an optically transparent material (eg, quartz, sapphire, etc.) to allow light to pass through the grid.

  In some embodiments, for a 300 mm wafer etcher, it may be preferable to have a slot in the grid about every 15-40 mm near the outer edge of the grid. This corresponds to azimuthally adjacent azimuth adjacent slots that are separated by about 18 ° or about 48 °, respectively. Thus, in some embodiments, the azimuthal adjacent slots are separated by at least about 10 ° or at least about 15 °. In these or other embodiments, the azimuthal adjacent slots are spaced apart by no more than about 40 °, or no more than about 50 °, or no more than about 60 °.

  In some embodiments, the grid does not play an important role in plasma formation. However, the grid can serve to keep the electron-ion plasma in the upper subchamber and to filter and transmit the species that are delivered to the lower subchamber.

[Plasma characteristics]
The grid effectively divides the plasma chamber into two zones: an upper zone proximate to the plasma generating coil (or other plasma generating mechanism) and a lower zone proximate to the substrate holder. In some embodiments, the upper zone plasma includes relatively “hot” high energy electrons. This plasma is often characterized as an electron-ion plasma. In some embodiments, the lower zone plasma includes relatively “cold” low energy electrons. This lower zone plasma is often characterized as an ion-ion plasma.

  The plasma can be generated primarily or exclusively in the upper subchamber. In one embodiment, inductively coupled plasma is generated in the upper subchamber by passing current through a coil located above the upper subchamber. A single coil or multiple coils can be employed. In other embodiments, a capacitively coupled plasma is generated, for example, using a VHF CCP source. Due to the grid, the upper subchamber plasma has distinctly different characteristics than the lower subchamber plasma.

In many embodiments, the upper zone plasma is a normal electron-ion plasma. In this type of plasma, most of the positively charged species are positive ions, and most of the negatively charged species are electrons. Although negative ions are present, they are only at relatively low concentrations. In contrast, the plasma in the lower subchamber is often an ion-ion plasma. Ion-ion plasma has a higher proportion of negatively charged species that are negative ions and a lower proportion of negatively charged species that are electrons compared to electron-ion plasma. In some implementations, ions - the ratio of positive ion concentration for the electron concentration in the ion plasma (also referred to as the ratio n _i / n _e of the positive ions to electrons) is from about 2 or more, in some instances, It is about 5 or more, or even about 10 or more. In some examples, the ratio of positive ions to electrons is at least about 2 times greater (eg, at least 5 times greater) in the lower plasma than in the upper plasma.

A related difference between the two plasmas is that the upper zone plasma has a significantly higher electron density. For example, the electron density of the lower zone plasma can be about 5 × 10 ⁹ cm ⁻³ or less (eg, about 1 × 10 ⁹ cm ⁻³ or less). Such a range is particularly applicable to electron negative process gases. The upper zone plasma can have an electron density that is at least about 10 times greater (eg, at least about 100 times greater, or at least about 1000 times greater) than that of the lower zone plasma. In some examples, the lower subchamber has an ion-ion plasma, where the electron density is at least an order of magnitude less than the negative ion density and the positive ion density. In an example of a specific lower subchamber plasma, the electron density (Ne) is about 10 ⁸ cm ⁻³ , the positive ion density (Ni +) is about 10 ⁹ cm ⁻³ , and the negative ion density (Ni−). Is about 10 ⁹ cm ⁻³ .

  An additional difference between the upper zone plasma and the lower zone plasma is that the lower zone plasma typically has a higher ratio of negative ions to positive ions. The upper zone electron-ion plasma usually contains mainly positive ions and electrons, and since there are relatively few negative ions, the negative ion: positive ion ratio is low. The negative ion: positive ion ratio in the lower zone plasma can be between about 0.5-1 (eg, between about 0.8-0.95).

  One possible non-limiting explanation for the relatively low electron concentration in the lower zone plasma is that electrons in the lower zone (eg, electrons that have passed through the grid from the upper zone to the lower zone) are generally RF It is not heated by an electric field and loses energy rapidly due to inelastic collisions with gas molecules, resulting in a low effective electron temperature. These low energy electrons are more likely to interact with neutral species to produce negative ions (compared to high energy electrons in the upper zone plasma). Electrons must be relatively low energy in order to attach to neutral particles and generate negative ions. Such negative ion production does not occur with high-energy electrons, and when they collide with neutral species, they do not combine to produce negative ions, but “kick” other electrons. There is.

  As pointed out, the effective electron temperature is higher in the upper zone plasma than in the lower zone plasma. The electrons can be cooled as they pass through the slots in the grid. Typically, the effective electron temperature of the lower zone plasma is about 1 eV or less. In some examples, the effective electron temperature of the lower zone plasma can be between about 0.1 and 1 eV (eg, between about 0.2 and 0.9 eV). The effective electron temperature, when measured in electron volts, can be at least about 2 times higher (eg, at least about 3 times higher) in the upper zone plasma than in the lower zone plasma. In a specific implementation, the upper zone plasma has an effective electron temperature of about 2.5 eV and the lower zone plasma has an effective electron temperature of about 0.8 eV. In some embodiments, this difference in effective electron temperature occurs due to the presence of a grid, in whole or in part.

  The role of the grid can be explained as follows without being limited to a specific theory or mechanism. The grid can partially shield the lower subchamber so that charged species therein do not receive power directly from the plasma coil. Furthermore, the specific aspect ratio of the grid slot allows some of the high energy electrons to collide with the grid as it passes through the slot. This generates two qualitatively different plasmas in the two plasma zones.

  Another distinguishing feature of upper zone plasma and lower zone plasma is their plasma potential. In general, the plasma potential in the upper chamber is higher than in the lower chamber. For example, the plasma potential in the upper plasma can be between about 8-35V (eg, between about 10-20V) and the plasma potential in the lower plasma is between about 0.4-10V (eg, about 0.5-3V). Such a difference in plasma potential can arise because the lower zone plasma does not need to be aggressive in preventing the loss of electrons because the lower subchamber has lower electron energy.

  The two plasmas usually have different energy distribution functions (for example, an ion energy distribution function and an electron energy distribution function). Both the electron energy distribution function and the ion energy distribution function are narrower in the lower plasma and wider in the upper plasma. By using the grid, an extremely narrow ion energy distribution function can be obtained without using sophisticated control by a waveform generator. For example, the ion energy distribution function of the lower plasma can have a full width at half maximum of only about 5V. As a result, it is possible to draw a negative current from the negative ions, which reaches the substrate surface and maintains electrical neutrality (instead of electrons serving this purpose). In this way, a unique etching mechanism is obtained.

  The radical concentration in the lower zone plasma ranges from about 1% total neutral density to about 70% total neutral density, or from about 10% to about 70% total neutral density, or about 10%. It can range from about 50% total neutral density.

Chamber pressure during the etching process, such as between about 1 to 2000 mTorr (e.g., between about 0.267～26.7Pa (2 to 200 mTorr)), may be less than about 2000 mtorr. In one specific example, the chamber pressure is maintained below about 20 millitorr. Such pressure is particularly useful when used with a lower zone plasma having an effective electron temperature of about 0.5 eV or less and / or an electron density of about 5 × 10 ⁸ cm ⁻³ or less. These pressures are also particularly useful when used in the lower zone ion-ion plasma.

  Ion-ion plasma is considered to have several effects in semiconductor processing. For example, a semi-finished semiconductor device etched with ion-ion plasma exhibits very good selectivity, profile angle, sparse / dense (I / D) loading, and overall uniformity across the surface of the substrate to be etched. In the prior art, all of these effects could not be obtained simultaneously (i.e., process designers, for example, between achieving good overall etch uniformity and obtaining other effects, Had to choose). Accordingly, the embodiments described herein represent a significant advance in etching methods.

3A-3C illustrate the effect of etch byproduct decomposition on the features being etched. Initially, FIG. 3A shows a substrate with three layers deposited thereon. The bottom layer 303 represents the gate oxide, the middle layer 305 represents the polysilicon, and the top layer 307 (shown as three individual blocks) represents the hard mask. In a conventional etching process, it is believed that the plasma in the chamber acts to partially dissociate the etching byproduct 310 as shown in FIG. 3B. This mechanism may include ion-assisted chemical etching, some of which are represented by positive ions 309. These by-products 310 are often volatile components (eg, SiBr ₄ ) and are removed from the substrate when conditions are met. However, when high effective electron temperature plasma, characteristic of electron-ion plasma, comes into contact with the wafer, the high-energy electrons in the plasma react with the volatile by-product 310 to cause physicochemical reaction. There is a possibility of dissociation into a “sticky” dissociation product 312 (eg, SiBr ₂ ). These dissociation products 312 can attach to the substrate, as shown in FIG. 3B, and often attach to the sidewalls of the feature being etched, as shown in FIG. Generate in non-vertical or other undesired form. Such attachment / reattachment of dissociation products leads to a local loading effect that results in non-vertical etching.

These undesirable effects are mitigated by using a grid to suppress the effective electron temperature of the plasma close to the substrate to be etched. The grid can eventually generate an ion-ion plasma, which reduces these undesirable effects by reducing the electron density and effective electron temperature accordingly. In general, ions have much lower energy than electrons, so the ions in the ion-ion plasma of embodiments of the present invention do not cause such by-product dissociation. In embodiments of the present invention, an electron-ion plasma can be generated, but this high electron density / high effective electron temperature plasma can remain in the upper subchamber. For this reason, etching by-products tend to contact only the lower zone plasma and not the upper zone plasma with high effective electron temperature. The ion - although some electrons in the ion plasma exists, their electrons generally have a low T _e, therefore, usually, do not have sufficient energy to cause dissociation of the by-products. In this way, etching by-products are not dissociated into compounds that cause “stickiness” problems.

[Wafer bias]
In some implementations, the wafer is biased during processing. This is accomplished by applying a bias to the electrostatic chuck used to hold / support the wafer. Since the wafer is exposed to a lower _Te , low electron density plasma (such as an ion-ion plasma) in the lower subchamber, the chuck can have a unique effect on that ion-ion plasma. A bias can be applied. Furthermore, a bias can be applied so that the formation of electron-ion plasma is avoided in the lower subchamber. For example, the bias can be of a frequency and power suitable to prevent the formation of an electron-ion plasma, in which case the ion-ion plasma is formed without using the power provided by the chuck bias. For example, the RF bias can be at a frequency of less than about 20 MHz, preferably between about 100 kHz and about 13.56 MHz, so as to reduce the amount of electronic heating generated by the application of bias power to the substrate. In some embodiments, the bias (regardless of frequency) is pulsed in the range of about 1 Hz to about 10 kHz with a duty cycle between about 1% and 99%.

  As described above, in normal electron-ion plasma, the plasma potential is a fairly high positive potential. Such a plasma potential effectively limits the ability of those electrons to escape from the plasma. On the other hand, the lower zone plasma generally has an unusually low electron density and effective electron temperature, so that only a much lower plasma potential is needed to keep the electrons effectively. Absent. This low plasma potential relaxes the operating window limitations and optionally accelerates collisions towards the wafer by the presence of negative ions in the ion-ion plasma during the positive cycle of the bias waveform. Is possible. Such an etching regime could not be obtained with conventional continuous wave plasma.

  The frequency of the bias applied to the electrostatic chuck can be designed to optimize the formation and attraction of ions in the ion-ion plasma, including but not limited to negative ions.

  The power level of the bias applied to the electrostatic chuck can be designed to prevent electron-ion plasma formation in the lower subchamber. In some embodiments, the power supplied to bias the chuck is between about 3-300 W, such as between about 5-150 W. This may correspond to a bias voltage between about 0-500V.

  In some embodiments, the frequency of the bias applied to the electrostatic chuck is between about 0.1 to 15 MHz (eg, between about 400 kHz to 13.56 MHz). In a specific example, the bias is about 8 MHz. Such a frequency can be particularly useful because it corresponds to an ion transfer frequency. Other frequencies may be used, but the effect may be reduced. For example, frequencies between about 100 kHz and 1 MHz may function to some extent but are less effective than the higher frequencies. Another consideration regarding the bias applied to the chuck / wafer is that if the frequency of the bias is too high, the bias can act to form an electron-ion plasma in the lower subchamber. In order to avoid such conditions, the frequency of the bias applied to the electrostatic chuck must be less than about 30 MHz. In some embodiments, the frequency of the bias is between about 100 kHz to 13 MHz.

  It should be noted that when a grid is used and an AC bias of the appropriate frequency is applied to the electrostatic chuck / wafer, negative and positive ions are alternately extracted from the plasma and accelerated toward the wafer surface. Thus, the plasma sheath above the wafer can be made to function. That is, the plasma sheath attracts negative ions in the positive cycle and positive ions in the negative cycle, and these cycles are repeated with an AC bias. As mentioned above, this negative ion attraction (to the wafer) is too high before the realization of embodiments of the present invention, so that it attracts that half of the AC bias cycle. It was impossible by canceling the effect.

  As described above, the bias can be applied in pulses. However, there are many cases where pulsing is not necessary. In the embodiment of the present invention, a stable ion-ion plasma is obtained above the wafer in the entire etching process. Thus, it is not necessary to pulse the bias to the chuck / wafer to achieve the effects described herein. However, in some embodiments, the bias may still be applied in pulses, for example, to reduce etch rate or substrate ion bombardment, thereby improving etch selectivity to the underlying layer. . Bias pulsing in ion-ion plasma can be particularly useful by improving selectivity by using ions and radicals alternately. That is, by pulsing, the flow of ions and radicals to the substrate surface can be separated (pulse on: radical + ion; pulse off: radical only).

[Process / Application]
The apparatus and plasma conditions disclosed herein include silicon (including but not limited to polycrystalline, amorphous, single crystal, and / or microcrystalline silicon), metals (including but not limited to TiN, W, TaN, etc.) Any of a variety of materials such as oxides and nitrides (including but not limited to SiO, SiOC, SiN, SiON, etc.), organics (including but not limited to photoresist, amorphous carbon, etc.) Other various materials that can be used for etching include, but are not limited to, W, Pt, Ir, PtMn, PdCo, Co, CoFeB, CoFe, NiFe, W, Ag, Cu, Mo, TaSn, Ge ₂ Sb ₂ Te ₂ , InSbTe Ag—Ge—S, Cu—Te—S, IrMn, and / or Includes Ru. This _concept, NiO _x, SrTiO _x, perovskite _{(CaTiO 3), PrC a MnO} 3, PZT (PbZr 1 - x Ti x O 3), can be extended to materials such as (SrBiTa) O _3. This apparatus can be used in any combination of gases (including HBr, CO, NH ₃ , CH ₃ OH, etc.) that can be used in current production facilities.

  The apparatus and plasma conditions disclosed herein can be employed to etch features in any technology node device or other structure. In some embodiments, etching is used in the manufacture of 20-10 nm nodes or later. Etching can be performed before both the front end of the manufacturing procedure and the back end of the manufacturing procedure. Etching can provide excellent vertical profile, material selectivity, I / D loading, and / or wafer center-to-edge uniformity better than about 2%. Some examples of suitable etching applications include shallow trench isolation, gate etching, spacer etching, source / drain recess etching, oxide recess, and hard mask opening etching.

[apparatus]
The methods described herein can be performed by any suitable apparatus. A suitable apparatus comprises a chamber that is divided into an upper subchamber and a lower subchamber by a grid structure, and electronic hardware for providing and maintaining etching conditions as described herein. . Appropriate equipment further provides instructions for controlling the hardware to achieve such conditions, and for performing a series of process steps suitable for applications such as etching the gate electrode of the FET. Having a system controller. In some embodiments, the hardware can include one or more processing stations included in the process tool.

  FIG. 1 schematically illustrates a cross-sectional view of an inductively coupled plasma etching apparatus 100 according to some embodiments described herein. The inductively coupled plasma etching apparatus 100 includes an overall etching chamber that is structurally defined by a chamber wall 101 and a window 111. The chamber wall 101 is typically made of stainless steel or aluminum. Window 111 is typically made of quartz or other dielectric material. The entire etching chamber is divided into an upper subchamber 102 and a lower subchamber 103 by an internal plasma grid 150. A chuck 117 is disposed near the inner bottom surface in the lower subchamber 103. The chuck 117 is configured to receive and hold a semiconductor wafer (or “wafer”) 119 on which an etching process is performed. The chuck 117 may be an electrostatic chuck for supporting a wafer when it is present. In some embodiments, an edge ring (not shown) surrounds the chuck 117, which has a top surface that is generally planar with the wafer surface when the wafer is on the chuck 117. The chuck 117 further has electrostatic electrodes to allow wafer chucking and dechucking. For this purpose, a filter and a DC clamp power supply can be provided. Other control systems for lifting the wafer from the chuck 117 can also be provided. The chuck 117 can be charged using an RF power source 123. The RF power source 123 is connected to the matching circuit 121 via the connection 127. Matching circuit 121 is connected to chuck 117 via connection 125. In this way, the RF power source 123 is connected to the chuck 117.

  A coil 133 is disposed above the window 111. The coil 133 is made of a conductive material and includes at least one complete turn. The exemplary coil 133 shown in FIG. 1 includes three turns. The cross section of the coil 133 is shown with a symbol, and the coil with “X” is rotated to extend into the paper surface, and the coil with “•” is rotated to come out of the paper surface. Stretch to. The RF power source 141 is configured to supply RF power to the coil 133. Usually, the RF power supply 141 is connected to the matching circuit 139 via the connection 145. Matching circuit 139 is connected to coil 133 via connection 143. In this way, the RF power source 141 is connected to the coil 133. An optional Faraday shield 149 is disposed between the coil 133 and the window 111. The Faraday shield 149 is maintained in a spaced relationship with the coil 133. The Faraday shield 149 is disposed immediately above the window 111. The coil 133, the Faraday shield 149, and the window 111 are each configured to be substantially parallel to each other. Faraday shielding can prevent metal or other species from adhering to the dielectric window of the plasma chamber.

  Process gas may be supplied through a main inlet 160 located in the upper chamber and / or through a side inlet 170, also referred to as STG. The gas outlet is not shown. Also not shown is a pump connected to the chamber 101 to allow vacuum control and removal of gaseous by-products from the chamber during operational plasma processing.

  During operation of the apparatus, one or more reactive gases can be supplied via inlets 160 and / or 170. In some embodiments, the gas can be supplied only through the main inlet or only through the side inlet. In some examples, the inlet can be replaced with a showerhead. Faraday shield 149 and / or grid 150 may have internal channels and holes that allow delivery of process gas to the chamber. That is, either or both of the Faraday shield 149 and the grid 150 can function as a shower head for delivering the processing gas.

  High frequency power is applied from the RF power source 141 to the coil 133, whereby an RF current flows through the coil 133. An electromagnetic field is generated around the coil 133 by the RF current flowing in the coil 133. This electromagnetic field generates an induced current in the upper subchamber 102. This induced current acts on the gas in the upper subchamber 102 to generate electron-ion plasma in the upper subchamber 102. The internal plasma grid 150 limits the amount of hot electrons in the lower subchamber 103. In some embodiments, the apparatus is designed and operated such that the plasma in the lower subchamber is an ion-ion plasma.

  The upper electron-ion plasma and the lower ion-ion plasma both contain positive ions and negative ions, but the ion-ion plasma has a larger negative ion: positive ion ratio. The physical and chemical interactions of the various ions and radicals with the wafer 119 selectively etch the wafer features. Volatile etching by-products are removed from the lower subchamber via an outlet (not shown). Importantly, since such volatile by-products are virtually unexposed to hot electrons, they are not likely to be dissociated into non-volatile “sticky” dissociation products.

Typically, the chucks disclosed herein operate at high temperatures in the range of about 30 ° C to about 250 ° C, preferably in the range of about 30-150 ° C. This temperature depends on the etching process treatment and the specific recipe. The chamber 101 may also operate at a pressure in the range of about 1 millitorr to about 12.7 Pa ( 95 millitorr ) , or in the range of about 5 to 20 millitorr . However, in some embodiments, higher pressures as disclosed above can be used.

  Although not shown, the chamber 101 is usually connected to various facilities when installed in a clean room or a manufacturing facility. These facilities include piping facilities that provide process gas, vacuum, temperature control, and environmental particle control. When the chamber 101 is installed in the target manufacturing facility, such equipment is connected. Furthermore, the chamber 101 can be connected to the transfer chamber, which makes it possible to transfer the semiconductor wafer into and out of the chamber 101 using a normal automatic operation by robot technology.

  2A-2B illustrate an example of an internal plasma grid according to embodiments described herein. The grid can have slots extending radially outward. In the embodiment of FIG. 2B, there are three types of slots. Each of the three types of slots has a different slot length. The slot shown in FIG. 2B has an aspect ratio suitable for generating an ion-ion plasma in the lower subchamber, as described above. The slots shown in FIG. 2A may not be drawn to scale.

  In some embodiments, the semiconductor etcher can be incorporated into a multi-station tool. Multi-station tools can include multiple plasma etch reactors as disclosed herein and can include additional stations for performing other semiconductor manufacturing processes. A multi-station integrated processing tool and a method using such a tool were filed on Feb. 8, 2006 and the title of the invention is “WAFER MOVEENT CONTROL MACROS” (PCT application No. PCT). / US2006 / 004625 and on May 7, 2008, the name of the invention is “DYNAMIC ALIGNMENT OF WAFERS USING COMPENSATION VALUES OBTAINED THROUGH A SERIES OF WAFER MOVEMENTS” Is further described and described in US patent application Ser. No. 12 / 116,897. Each of which is hereby incorporated by reference in its entirety.

  FIG. 4 illustrates a typical semiconductor process cluster architecture, illustrating various modules interfaced with a vacuum transfer module 38 (VTM: Vacuum Transfer Module). As is well known to those skilled in the art, the configuration of a transfer module for “transferring” wafers between multiple storage facilities and processing modules is often referred to as a “cluster tool architecture” system. Shown in VTM 38 is an air lock 30, also referred to as a load lock or transport module, along with four processing modules 20 a-20 d that can be individually optimized to perform various manufacturing processes. By way of example, the processing modules 20a-20d can be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and / or other common semiconductor processes. One or more of the substrate etch processing modules (any of 20a-20d), as disclosed herein, i.e. with a grid structure that divides the reaction chamber into an upper subchamber and a lower subchamber. Can be realized. When referring generally to the airlock 30 or processing module 20, the term station is used when referring to either an airlock or a processing module. Each station has a facet 36 that interfaces the station to a vacuum transfer module 38. Inside each facet, sensors 1-18 are used to detect the passage of wafer 26 entering and exiting each station.

  The robot 26 transfers the wafer 26 between the stations. In one embodiment, the robot 22 has one arm and in other embodiments the robot 22 has two arms, where each arm is an end effector for picking up a wafer for transfer. 24. Front Opening Robot 32 in an Atmospheric Transfer Module (ATM) 40, from a cassette or in a front port integrated pod (FOUP) in a Loadport Module (LPM) 42 : Front Opening Unified Pod) 34 to transfer the wafer to the airlock 30. The module center 28 inside the processing module 20 indicates an ideal position for placing the wafer 26. The aligner 44 in the ATM 40 is used to align the wafer.

  In the exemplary processing method, a wafer is placed in any one of the hoops 34 in the loadport module 42. The front end robot 32 transports the wafer from the hoop 34 to the aligner 44 so that the wafer can be properly centered before being etched. After alignment, the wafer is transferred into the airlock module 30 by the front end robot 32. Since the airlock module has the ability to adapt the environment between the atmospheric transfer module and the vacuum transfer module, it is possible to transfer the wafer between the two pressure environments without damage. Wafers are transferred from the airlock module 30 by the robot 22 through the vacuum transfer module 38 and into any one of the processing modules 20a-20d. To accomplish such wafer movement, the robot 22 uses the end effector 24 of each of its arms. Once the wafer has been processed, it is transferred by robot 22 from processing modules 20a-20d to airlock module 30. From there, the front end robot 32 can transfer the wafer to any one of the hoops 34 or to the aligner 44.

  It should be noted that the computer that controls the movement of the wafer can be local to this cluster architecture, or it can be located somewhere in the manufacturing site or at a remote location, over the network. It can be connected to.

[System controller]
In some embodiments, a system controller (which may include one or more physical or logical controllers) controls some or all of the operation of the etching chamber. The system controller can comprise one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor controller boards, and other similar components. Instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored in a memory device associated with the controller or may be provided over a network. In some embodiments, the system controller executes system control software.

  The system control software can include instructions for controlling the timing and / or magnitude of one or more of the following chamber operating conditions: gas mixing and / or composition, chamber pressure, chamber temperature, Wafer / wafer support temperature, bias applied to the wafer, frequency and power applied to coils or other plasma generating elements, wafer position, wafer travel speed, and other parameters of the specific process performed by the tool. The system control software can be configured in any suitable manner. For example, various process tool component subroutines or control objects can be created to control the operation of the process tool components necessary to implement the various process tool processes. The system control software can be coded in any suitable computer readable programming language.

  In some embodiments, the system control software includes input / output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each stage of the semiconductor manufacturing process can include one or more instructions for execution on the system controller. For example, instructions for setting process conditions for an etch stage can be included in the corresponding etch recipe stage. In some embodiments, the recipe stages can be arranged in sequence so that all instructions for a process stage are executed simultaneously with the process stage.

  In some embodiments, other computer software and / or programs may be employed. Examples of programs or program portions for this purpose include substrate positioning programs, process gas composition control programs, pressure control programs, heater control programs, and RF power supply control programs.

  In some examples, the controller controls gas concentration, wafer movement, and / or power supplied to the coil and / or electrostatic chuck. The controller controls the gas concentration, for example, by opening and closing associated valves to generate one or more incoming gas streams that supply the required reactant (s) at the appropriate concentration. be able to. The movement of the wafer can be controlled, for example, by instructing the desired positioning to the wafer positioning system. The power supplied to the coil and / or chuck generates a specific RF power level to generate the desired electron-ion plasma in the upper subchamber and the desired ion-ion plasma in the lower subchamber. Can be controlled to give. Furthermore, the controller can be configured such that power is supplied to the electrostatic chuck under conditions such that no electron-ion plasma is formed in the lower subchamber. That is, the controller is configured to maintain an ion-ion plasma (or at least a plasma having an appropriate low effective electron temperature and density) in the lower subchamber. The controller determines these or other aspects based on sensor output (eg, when power, potential, pressure, etc. reach a predetermined threshold), timing of operation (eg, opening a valve at a predetermined point in the process) Or based on an instruction received from the user.

  The various hardware and method embodiments described above can be used with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, solar panels, and the like. In general, such tools / processes, although not necessarily, are used or performed together in a common manufacturing facility.

  Lithographic film patterning typically includes some or all of the following steps, each of which can be performed by several possible tools. (1) For example, a photoresist is applied on a workpiece, which is a substrate on which a silicon nitride film is formed, using a spin or spray tool, (2) a hot plate or a furnace or other Use a suitable curing tool to cure the photoresist, (3) Expose the photoresist with visible light, ultraviolet light, or X-rays with a tool such as a wafer stepper, (4) such as a wet bench or spray developer Using a tool, develop the resist to selectively remove the resist, thereby forming a pattern. (5) Using a dry or plasma assisted etching tool, apply the resist pattern to the underlying film or workpiece. (6) RF or microwave plasma resist stripper tools Stomach, the resist is removed. In some embodiments, an assurable hard mask layer (such as an amorphous carbon layer) and other suitable hard masks (such as an antireflective layer) can be deposited prior to applying the photoresist.

  The configurations and / or techniques described herein are, of course, exemplary in nature and these specific embodiments or examples should not be construed in a limiting sense. Many variations are possible. The specific routines or methods described herein may present one or more of a number of processing strategies. Accordingly, the various illustrated processing operations can be performed in the illustrated order, in other orders, in parallel, or in some cases, omitted. Similarly, the order of the above processes can be changed.

  This disclosure includes all novel and non-obvious combinations and subcombinations of various processes, systems and configurations disclosed herein, as well as other features, functions, processing operations, and / or characteristics. , As well as any equivalents thereof.

[Experiment]
Experiments have confirmed that the method and apparatus of the present disclosure improves the etching of semi-finished devices on a semiconductor substrate. When using a plasma grid, the etched product shows good selectivity, profile angle, sparse / dense loading, and overall etch uniformity.

  FIGS. 5A and 5B show a scanning electron microscope (SEM) of a fin FET structure etched by a conventional high voltage technique (5A) and by an embodiment of the present invention using a plasma grid (5B). The image is shown. As shown in FIG. 5A, the prior art results in a serious non-uniformity between the center and edge of the wafer. For example, the feature bottom was etched much more in the center than at the edge of the wafer. This suggests that reattachment of dissociation byproducts was a greater problem near the edge than at the center of the wafer. I / D loading was large and selectivity between materials was low. Sparse / dense loading can be considered in several ways. Etch depth sparse / dense loading means that the etch depth for sparse features (typically large features, eg, 500 nm spacing) and dense features (typically small features). Thus, for example, it can be calculated as a difference from the etching depth at a wiring having a spacing of 30 nm. Profile sparse / dense loading can be calculated as the difference between the profile angle at the sparse feature and the profile angle at the dense feature. Sparse / dense loading may also refer to a critical dimension (CD) comparison. In that case, sparse / dense loading can be calculated as (sparse feature (bottom CD-top CD))-(dense feature (bottom CD-top CD)). Unless otherwise specified, I / D loading shall refer to this critical dimension comparison.

  On the other hand, as shown in FIG. 5B, the uniformity from the center to the edge is substantially improved by using the plasma grid. Also, I / D loading was much lower and selectivity was improved. This experiment was performed on a Si carrier wafer thinned to a thickness representing the height of the FinFET and covered with a 50% SiN coupon to simulate full pattern wafer etching. The finFET structure was over-etched at 65% to minimize profile taper.

  6A and 6B show SEM images of features etched by conventional low pressure techniques (6A) and by an embodiment of the present invention using a plasma grid (6B). The prior art showed a relatively low selectivity between silicon and oxide, the etched features had a tapered profile, and the I / D loading was not good. On the other hand, as shown in FIG. 6B, an improved selectivity (infinite selectivity), a more vertical profile angle was obtained by the plasma grid, and I / D loading was almost eliminated. This experiment was performed on a chip that was cut from the pattern wafer and placed in the center of the carrier wafer. This experiment was performed on a Si carrier wafer thinned to a thickness representing the height of the FinFET and covered with a 50% SiN coupon to simulate full pattern wafer etching.

  FIG. 7 shows various SEM images of features etched according to several regimes without using a plasma grid. Two different pressures and four different total flow rates were used. The effective electron temperature (Te) decreases with increasing pressure. Residence time decreases with increasing total flow rate. When the total flow rate is increased at each pressure, the etching result is improved. In particular, the high flow case shows a better (more vertical) profile angle and improved selectivity (more mask residue). However, these improvements are mitigated by poorer I / D loading and center-to-edge uniformity. The result at this high flow rate is that some by-products and / or dissociation products when not scavenged in the form of gas may adhere to the feature sidewalls and / or bottom as shown in FIGS. This supports the idea that poor etching results. The higher the total flow rate, the more effectively these by-products are scavenged from the reaction chamber, making it less likely that etch failure will occur.

  Various experiments have shown that using a plasma grid results in an etching process with very good selectivity, profile angle, I / D loading, center to edge uniformity. In some examples, the selectivity (ie, Si etch rate: oxide etch rate) is greater than about 10 or greater than about 100. In fact, in some cases, infinite selectivity may be obtained by using a plasma grid. In such cases, the oxide material is almost never etched, but rather a small amount of deposition may occur on the oxide surface. The profile angle obtained in many cases is approximately vertical (eg, greater than about 89 °). In some implementations, I / D loading has been shown to be less than about 2 °. Also, center to edge uniformity in some implementations was less than about 2 nm.

Claims (28)

An apparatus for etching features on a substrate comprising:
A chamber defining an interior in which a plasma can be provided;
A substrate holder for holding the substrate in the chamber during etching;
A plasma generator for generating plasma in the chamber;
A grid that divides the interior of the chamber into an upper subchamber proximate to the plasma generator and a lower subchamber proximate to the substrate holder;
A controller designed or configured to generate a plasma in the chamber, with the condition that an upper zone plasma is generated in the upper subchamber and a lower zone plasma is generated in the lower subchamber; With
The plasma potential of the upper zone plasma is higher than the plasma potential of the lower zone plasma,
The upper subchamber has a height of at least about 1/6 of the height of the lower subchamber;
The grid includes a plurality of slots extending substantially radially outward, and the slots substantially prevent an induced current from being generated in the grid when plasma is generated in the chamber. . The apparatus of claim 1.
The effective electron temperature of the lower zone plasma is about 1 eV or less and lower than the effective electron temperature of the upper zone plasma,
The electron density of the lower zone plasma is about 5 × 10 ⁹ cm ⁻³ or less and lower than the electron density of the upper zone plasma.   The apparatus of claim 1, wherein the controller is further designed or configured to apply a bias to the grid.   The apparatus of claim 1, wherein the controller is further designed or configured to apply a bias to the substrate holder.   The apparatus according to any one of the preceding claims, wherein the controller is further designed or configured to supply an etchant gas to the chamber. The apparatus according to any one of claims 1 to 5, wherein the controller is further during the etching of the substrate by the plasma, designed to pressure of about 267P a less than said chamber Or configured device.   The apparatus according to any one of the preceding claims, wherein the controller is further designed or configured to generate an ion-ion plasma in the lower subchamber.   8. The apparatus according to any one of claims 1 to 7, wherein the grid has an average thickness between about 1-50 mm.   9. The apparatus according to any one of claims 1 to 8, wherein the slot of the grid has an aspect ratio of height to width between about 0.3-5.   10. The apparatus according to any one of claims 1 to 9, wherein the slot is spaced from an adjacent slot with an azimuth angle of no more than about 60 degrees.   11. The apparatus according to any one of claims 1 to 10, wherein the plasma generator has a coil disposed above the ceiling of the chamber.   The apparatus according to any one of claims 1 to 11, wherein the substrate holder is an electrostatic chuck.   The apparatus according to any one of claims 1 to 12, further comprising a vacuum connection. A system for processing a semiconductor substrate,
A vacuum transfer module;
A robot in the vacuum transfer module;
A plurality of processing modules connected to facets in the vacuum transfer module;
A controller having a processor,
At least one of the plurality of processing modules is
A chamber defining an interior in which a plasma can be provided;
A substrate holder for holding the substrate in the chamber during etching;
A plasma generator for generating plasma in the chamber;
A grid that divides the interior of the chamber into an upper subchamber proximate to the plasma generator and a lower subchamber proximate to the substrate holder;
The controller is designed or configured to generate a plasma in the chamber on the condition that an upper zone plasma is generated in the upper subchamber and a lower zone plasma is generated in the lower subchamber; The plasma potential of the upper zone plasma is higher than the plasma potential of the lower zone plasma,
The upper subchamber has a height of at least about 1/6 of the height of the lower subchamber;
The grid has a plurality of slots extending substantially radially outward, the slots substantially preventing inductive current from being generated in the grid when plasma is generated in the chamber. . A grid used in connection with a semiconductor etching apparatus,
A plate having a diameter substantially the same as the diameter of a standard semiconductor substrate for manufacturing semiconductor devices;
A plurality of slots extending substantially radially outward in the plate for substantially preventing induction current from being generated in the plate when the plate is exposed to plasma; Prepared,
The slot is a grid, wherein the aspect ratio of height to width is between about 0.3-5.   16. The grid according to claim 15, wherein when the grid is disposed in a processing chamber of a semiconductor etching apparatus, the grid is generated in the upper subchamber by dividing the processing chamber into an upper subchamber and a lower subchamber. A grid that functions to maintain a lower electron density in the lower subchamber that is at least about 10 times lower than an upper electron density in the upper subchamber when exposed to a plasma.   The grid of claim 16, wherein the grid functions to maintain the lower electron density at least about 100 times lower than the upper electron density.   18. A grid according to any one of claims 15 to 17, wherein the standard semiconductor substrate has a diameter of about 300 mm or about 450 mm.   19. A grid according to any one of claims 15 to 18, wherein azimuthally adjacent azimuth adjacent slots are separated by at least about 10 degrees and no more than about 60 degrees.   The grid according to any one of claims 15 to 19, wherein the grid includes a metal.   20. A grid according to any one of claims 15 to 19, wherein the grid includes an insulating material. A method for etching features on a substrate, comprising:
A substrate is supplied to a substrate holder in the chamber, and the chamber includes a plasma generator and a grid, and the grid is close to the substrate holder and an upper sub-chamber that is close to the plasma generator. A lower subchamber, wherein the upper subchamber has a height of at least about 1/6 of the height of the lower subchamber;
A plasma is generated in the chamber under the condition that an upper zone plasma is generated in the upper subchamber and a lower zone plasma is generated in the lower subchamber;
Etching features of the substrate by interaction of the lower zone plasma and the substrate;
The plasma potential of the upper zone plasma is higher than the plasma potential of the lower zone plasma,
The effective electron temperature of the lower zone plasma is about 1 eV or less and lower than the effective electron temperature of the upper zone plasma,
The electron density of the lower zone plasma is about 5 × 10 ⁹ cm ⁻³ or less and lower than the electron density of the upper zone plasma.   23. The method of claim 22, wherein substantially no current is generated in the grid when generating the plasma.   24. The method of claim 22 or claim 23, further comprising applying a bias to the grid.   24. The method of claim 22 or claim 23, further comprising applying a bias to the substrate holder.   26. The method according to any one of claims 22 to 25, further comprising supplying an etchant gas to the chamber.   27. The method according to any one of claims 22 to 26, wherein the etching is performed at a chamber pressure of less than about 267 Pa.   28. The method according to any one of claims 22 to 27, wherein the lower zone plasma is an ion-ion plasma.