JP6367956B2 - メモリセル及びサポート回路の縦ストリングを有する方法及び機器 - Google Patents
メモリセル及びサポート回路の縦ストリングを有する方法及び機器 Download PDFInfo
- Publication number
- JP6367956B2 JP6367956B2 JP2016548071A JP2016548071A JP6367956B2 JP 6367956 B2 JP6367956 B2 JP 6367956B2 JP 2016548071 A JP2016548071 A JP 2016548071A JP 2016548071 A JP2016548071 A JP 2016548071A JP 6367956 B2 JP6367956 B2 JP 6367956B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- memory cell
- sst
- memory
- surface side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000015654 memory Effects 0.000 title claims description 121
- 238000000034 method Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims description 152
- 239000000463 material Substances 0.000 claims description 39
- 239000004065 semiconductor Substances 0.000 claims description 32
- 239000004020 conductor Substances 0.000 claims description 21
- 239000012212 insulator Substances 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 14
- 230000000295 complement effect Effects 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 19
- 239000012777 electrically insulating material Substances 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 230000008569 process Effects 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 230000009471 action Effects 0.000 description 6
- 239000000872 buffer Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
- H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
本出願は、本明細書に参照として組み込まれる。2014年1月22日に出願された米国特許出願整理番号14/161,170の利益の優先性を主張する。
メモリ装置は通常、コンピュータまたは他の電子装置内において、内部の、半導体、集積回路として提供される。ランダムアクセスメモリ(RAM)、読み取り専用メモリ(ROM)、ダイナミックランダムアクセスメモリ(DRAM)、同期型ダイナミックランダムアクセスメモリ(SDRAM)及び不揮発性(たとえば、フラッシュ)メモリを含む多くの異なるタイプのメモリが存在する。
1つ以上の実施形態に、たとえばサポート回路が直面するサーマルバジェットの低減に役立つ、基板の裏面にサポート回路を有する機器が含まれる。これにより、複数のメモリセルのストリングを形成することがまず可能になり、その後、熱感応性がより高い可能性のあるサポート回路(たとえば、CMOS)を基板の裏面に形成することができる。
Claims (13)
- 基板の第1面側の複数のメモリセルストリングと、
前記基板の第2面側にあり、複数のトランジスタを有するサポート回路と、
前記基板内に形成されて前記複数のメモリセルストリングと前記サポート回路とを接続する接続構成と、を含み、
前記接続構成は、
前記基板を貫通する穴と、
前記穴をライニングするゲートインシュレータと、
前記ゲートインシュレータ内の前記穴を充填するゲート導体材料と、
前記基板の前記第1面側の前記穴の周囲に形成された環状の第1の拡散領域と、
前記基板の前記第2面側の前記穴の周囲に形成された環状の第2の拡散領域と、
を含むサラウンド基板トランジスタ(SST)を有する、
メモリ機器。 - 前記サポート回路が相補型金属酸化膜半導体(CMOS)回路である、請求項1に記載のメモリ機器。
- 前記SSTは、前記複数のメモリセルストリングの制御ゲートのための制御ゲートドライバとして作用する、請求項1または2に記載のメモリ機器。
- 前記基板は、前記SSTが形成される部分に凹部を有することにより、前記SSTのチャネル長が短縮されている、請求項1乃至3のいずれか一項に記載のメモリ機器。
- 前記接続構成は、前記基板から絶縁されて前記基板を貫通する貫通ビアをさらに有する、請求項1乃至4のいずれか一項に記載のメモリ機器。
- 前記接続構成は、前記SSTの周囲に複数のアシストゲートをさらに有し、前記SSTのチャネル領域は前記複数のアシストゲートにより完全空乏化される、請求項1乃至5のいずれか一項に記載のメモリ機器。
- 基板の第1面側の複数のメモリセルストリングと、
前記基板の第2面側にあり、複数のトランジスタを有するサポート回路と、
前記基板内に形成されて前記メモリセルストリングと前記サポート回路とを接続する接続構成と、を含み、
前記接続構成は、
前記基板を貫通する穴と、
前記穴をライニングするゲートインシュレータと、
前記ゲートインシュレータ内の前記穴を充填する半導体材料と、
前記ゲートインシュレータの周囲に形成された環状のゲート材料と、
前記基板の前記第1面側の前記半導体材料に形成された第1の拡散領域と、
前記基板の前記第2面側の前記半導体材料に形成された第2の拡散領域と、
を含むサラウンドゲートトランジスタ(SGT)を有する、
メモリ機器。 - 前記複数のメモリセルストリングが、前記基板から外側へ延在する複数のメモリセルピラーを含み、前記複数のメモリセルピラーのソースが前記基板から最も遠い前記複数のメモリセルピラーの上部にあり、前記複数のメモリセルピラーに接続されたデータラインが前記基板と前記複数のメモリセルピラーとの間の前記複数のメモリセルピラーの底部にある、請求項1に記載のメモリ機器。
- 前記基板の逆導電性を有するウェルを前記基板の上面にさらに含み、前記複数のメモリセルストリングが前記ウェルに接続される複数のメモリセルピラーを含み、前記ウェルが前記複数のメモリセルストリングのためのソースである、請求項1に記載のメモリ機器。
- 前記基板は、前記SGTが形成される部分に凹部を有することにより、前記SGTのチャネル長が短縮されている、請求項7に記載のメモリ機器。
- 前記SSTは、前記データラインに接続されている、請求項8に記載のメモリ機器。
- 前記SSTは、前記複数のメモリセルストリングの制御ゲートに接続され、
前記貫通ビアは、前記複数のメモリセルストリングのデータラインに接続される、
請求項5に記載のメモリ機器。 - 基板の一方の一表面から前記基板の途中にまで至る複数の穴を形成することと、
前記複数の穴をそれぞれライニングする複数のインシュレータを形成することと、
前記複数のインシュレータ内の前記複数の穴をそれぞれ充填する複数の導体材料を形成することと、
前記複数の穴、前記複数のインシュレータおよび前記複数の導体材料を有する前記基板の前記一方の一表面側に複数のメモリセルストリングを形成することと、
前記基板の他方の一主面から前記基板を薄型化して前記複数の導体材料および前記複数のインシュレータを露出することと、
前記基板の薄型化された面側に、複数のトランジスタを有するサポート回路を形成することと、
を含む方法であって、
前記複数の穴のうちの少なくとも一つの穴について、前記少なくとも一つの穴の前記基板の前記一方の一表面側の周囲に環状の第1の拡散領域を形成することと、前記少なくとも一つの穴の前記基板の前記薄型化された面側の周囲に環状の第2の拡散領域を形成することと、を行ってサラウンド基板トランジスタ(SST)を形成すること、
をさらに含み、前記SSTを介して前記複数のメモリセルストリングと前記サポート回路とを接続する、
方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/161,170 | 2014-01-22 | ||
US14/161,170 US9252148B2 (en) | 2014-01-22 | 2014-01-22 | Methods and apparatuses with vertical strings of memory cells and support circuitry |
PCT/US2015/012185 WO2015112557A1 (en) | 2014-01-22 | 2015-01-21 | Methods and apparatuses with vertical strings of memory cells and support circuitry |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017504217A JP2017504217A (ja) | 2017-02-02 |
JP6367956B2 true JP6367956B2 (ja) | 2018-08-01 |
Family
ID=53545372
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016548071A Active JP6367956B2 (ja) | 2014-01-22 | 2015-01-21 | メモリセル及びサポート回路の縦ストリングを有する方法及び機器 |
Country Status (6)
Country | Link |
---|---|
US (4) | US9252148B2 (ja) |
EP (1) | EP3097561A4 (ja) |
JP (1) | JP6367956B2 (ja) |
KR (2) | KR102193562B1 (ja) |
CN (2) | CN106104693B (ja) |
WO (1) | WO2015112557A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10910389B2 (en) | 2014-01-22 | 2021-02-02 | Micron Technology, Inc. | Methods and apparatuses with vertical strings of memory cells and support circuitry |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8797806B2 (en) * | 2011-08-15 | 2014-08-05 | Micron Technology, Inc. | Apparatus and methods including source gates |
US10541029B2 (en) | 2012-08-01 | 2020-01-21 | Micron Technology, Inc. | Partial block memory operations |
US9698153B2 (en) * | 2013-03-12 | 2017-07-04 | Sandisk Technologies Llc | Vertical NAND and method of making thereof using sequential stack etching and self-aligned landing pad |
KR20150122369A (ko) * | 2014-04-22 | 2015-11-02 | 삼성전자주식회사 | 반도체 장치 |
KR102135181B1 (ko) * | 2014-05-12 | 2020-07-17 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
JP6203152B2 (ja) | 2014-09-12 | 2017-09-27 | 東芝メモリ株式会社 | 半導体記憶装置の製造方法 |
US9780112B2 (en) * | 2015-10-26 | 2017-10-03 | Sandisk Technologies Llc | Methods and apparatus for three-dimensional NAND non-volatile memory devices with side source line and mechanical support |
KR102604053B1 (ko) | 2016-05-09 | 2023-11-20 | 삼성전자주식회사 | 수직형 메모리 장치 |
US10446606B2 (en) | 2017-07-19 | 2019-10-15 | International Business Machines Corporation | Back-side memory element with local memory select transistor |
KR102342853B1 (ko) * | 2017-07-21 | 2021-12-23 | 삼성전자주식회사 | 수직형 메모리 소자를 구비한 집적회로 소자 |
CN107527918B (zh) | 2017-08-31 | 2019-02-12 | 长江存储科技有限责任公司 | 一种3d nand存储器存储单元结构及其制造方法 |
KR102566771B1 (ko) | 2018-01-31 | 2023-08-14 | 삼성전자주식회사 | 3차원 반도체 소자 |
JP2020047814A (ja) * | 2018-09-20 | 2020-03-26 | キオクシア株式会社 | 半導体記憶装置 |
US10804293B2 (en) * | 2018-10-25 | 2020-10-13 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, vertical NAND flash memory device and SSD device including the same |
CN113366637A (zh) * | 2018-12-31 | 2021-09-07 | 美光科技公司 | 三维动态随机存取存储器阵列 |
US10734388B1 (en) * | 2019-01-15 | 2020-08-04 | Micron Technology, Inc. | Integrated assemblies having threshold-voltage-inducing-structures proximate gated-channel-regions, and methods of forming integrated assemblies |
KR102286428B1 (ko) * | 2019-01-22 | 2021-08-05 | 서울대학교 산학협력단 | 3차원 적층형 메모리 장치 및 상기 장치에서의 수직 상호 연결 구조 |
JP7414411B2 (ja) * | 2019-06-14 | 2024-01-16 | キオクシア株式会社 | 半導体記憶装置 |
US11094704B2 (en) * | 2019-10-31 | 2021-08-17 | Sandisk Technologies Llc | Method of forming a three-dimensional memory device and a driver circuit on opposite sides of a substrate |
JP2021150511A (ja) * | 2020-03-19 | 2021-09-27 | キオクシア株式会社 | 半導体記憶装置 |
KR20210117728A (ko) | 2020-03-20 | 2021-09-29 | 삼성전자주식회사 | 수직형 메모리 소자 |
KR20210121335A (ko) | 2020-03-26 | 2021-10-08 | 삼성전자주식회사 | 반도체 소자 |
CN113113417B (zh) * | 2020-04-17 | 2024-04-26 | 长江存储科技有限责任公司 | 存储器件 |
US11538827B2 (en) * | 2020-07-23 | 2022-12-27 | Macronix International Co., Ltd. | Three-dimensional memory device with increased memory cell density |
KR20220043315A (ko) * | 2020-09-29 | 2022-04-05 | 삼성전자주식회사 | 메모리 소자 |
Family Cites Families (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02194560A (ja) * | 1989-01-23 | 1990-08-01 | Oki Electric Ind Co Ltd | 半導体装置 |
GB9023096D0 (en) | 1990-10-24 | 1990-12-05 | Int Computers Ltd | Database search processor |
JP3289101B2 (ja) | 1996-01-25 | 2002-06-04 | 東京エレクトロン株式会社 | フラッシュ・ディスク・システムの初期化方法及び装置 |
JPH11177071A (ja) * | 1997-12-11 | 1999-07-02 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2001140133A (ja) | 1999-11-11 | 2001-05-22 | Murata Mach Ltd | 紡績装置 |
US6516380B2 (en) | 2001-02-05 | 2003-02-04 | International Business Machines Corporation | System and method for a log-based non-volatile write cache in a storage controller |
KR100422412B1 (ko) * | 2001-12-20 | 2004-03-11 | 동부전자 주식회사 | 수직 실리콘-온-인슐레이터 구조의 원통형 트랜지스터 및그 제조 방법 |
JP2004140133A (ja) * | 2002-10-17 | 2004-05-13 | Seiko Epson Corp | 半導体集積回路及びその製造方法 |
US7498652B2 (en) | 2004-04-26 | 2009-03-03 | Texas Instruments Incorporated | Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof |
US7442976B2 (en) * | 2004-09-01 | 2008-10-28 | Micron Technology, Inc. | DRAM cells with vertical transistors |
US7120046B1 (en) * | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
US7687400B2 (en) * | 2005-06-14 | 2010-03-30 | John Trezza | Side stacking apparatus and method |
US7534722B2 (en) | 2005-06-14 | 2009-05-19 | John Trezza | Back-to-front via process |
US7902598B2 (en) * | 2005-06-24 | 2011-03-08 | Micron Technology, Inc. | Two-sided surround access transistor for a 4.5F2 DRAM cell |
KR101088061B1 (ko) * | 2005-10-24 | 2011-11-30 | 삼성전자주식회사 | 플로팅 게이트를 갖는 비휘발성 기억 소자 및 그 형성 방법 |
KR100673020B1 (ko) * | 2005-12-20 | 2007-01-24 | 삼성전자주식회사 | 전계효과 소오스/드레인 영역을 가지는 반도체 장치 |
US7902643B2 (en) | 2006-08-31 | 2011-03-08 | Micron Technology, Inc. | Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods |
US7657705B2 (en) | 2006-09-27 | 2010-02-02 | Lsi Corporation | Method and apparatus of a RAID configuration module |
US8285707B2 (en) | 2006-11-08 | 2012-10-09 | International Business Machines Corporation | Method of querying relational database management systems |
JP5016928B2 (ja) | 2007-01-10 | 2012-09-05 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
KR100886429B1 (ko) | 2007-05-14 | 2009-03-02 | 삼성전자주식회사 | 반도체 소자 및 제조방법 |
KR20090037690A (ko) | 2007-10-12 | 2009-04-16 | 삼성전자주식회사 | 비휘발성 메모리 소자, 그 동작 방법 및 그 제조 방법 |
JP2009146942A (ja) * | 2007-12-11 | 2009-07-02 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2009212280A (ja) * | 2008-03-04 | 2009-09-17 | Toshiba Corp | 不揮発性半導体記憶装置の製造方法 |
JP5370802B2 (ja) | 2008-03-25 | 2013-12-18 | 株式会社大一商会 | 遊技機 |
US7977962B2 (en) | 2008-07-15 | 2011-07-12 | Micron Technology, Inc. | Apparatus and methods for through substrate via test |
US7964912B2 (en) | 2008-09-18 | 2011-06-21 | Power Integrations, Inc. | High-voltage vertical transistor with a varied width silicon pillar |
KR101502585B1 (ko) * | 2008-10-09 | 2015-03-24 | 삼성전자주식회사 | 수직형 반도체 장치 및 그 형성 방법 |
US20100157644A1 (en) * | 2008-12-19 | 2010-06-24 | Unity Semiconductor Corporation | Configurable memory interface to provide serial and parallel access to memories |
JP5388600B2 (ja) | 2009-01-22 | 2014-01-15 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
US8334704B2 (en) * | 2009-02-20 | 2012-12-18 | Apple Inc. | Systems and methods for providing a system-on-a-substrate |
KR101307490B1 (ko) | 2009-03-30 | 2013-12-11 | 메기가 코포레이션 | 상부 포스트-패시베이션 기술 및 하부 구조물 기술을 이용한 집적 회로 칩 |
US7986042B2 (en) | 2009-04-14 | 2011-07-26 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US9711407B2 (en) | 2009-04-14 | 2017-07-18 | Monolithic 3D Inc. | Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer |
JP2011003833A (ja) * | 2009-06-22 | 2011-01-06 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2011023687A (ja) * | 2009-07-21 | 2011-02-03 | Toshiba Corp | 不揮発性半導体記憶装置 |
US8101438B2 (en) | 2009-07-27 | 2012-01-24 | Silverbrook Research Pty Ltd | Method of fabricating printhead integrated circuit with backside electrical connections |
JP2011142276A (ja) * | 2010-01-08 | 2011-07-21 | Toshiba Corp | 不揮発性半導体記憶装置、及びその製造方法 |
US8288795B2 (en) * | 2010-03-02 | 2012-10-16 | Micron Technology, Inc. | Thyristor based memory cells, devices and systems including the same and methods for forming the same |
JP5144698B2 (ja) * | 2010-03-05 | 2013-02-13 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
JP2011204829A (ja) * | 2010-03-25 | 2011-10-13 | Toshiba Corp | 半導体記憶装置 |
KR101688598B1 (ko) * | 2010-05-25 | 2017-01-02 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 |
US8803214B2 (en) * | 2010-06-28 | 2014-08-12 | Micron Technology, Inc. | Three dimensional memory and methods of forming the same |
KR101683814B1 (ko) * | 2010-07-26 | 2016-12-08 | 삼성전자주식회사 | 관통 전극을 구비하는 반도체 장치 |
KR101703106B1 (ko) | 2011-01-04 | 2017-02-06 | 삼성전자주식회사 | 부분-이레이즈 동작을 수행할 수 있는 비휘발성 메모리 장치와 상기 비휘발성 메모리 장치를 포함하는 장치들 |
JP2012159903A (ja) | 2011-01-31 | 2012-08-23 | Fujitsu Semiconductor Ltd | データ処理システム、データ処理装置、及びデータ処理方法 |
US8478736B2 (en) | 2011-02-08 | 2013-07-02 | International Business Machines Corporation | Pattern matching accelerator |
KR101855169B1 (ko) * | 2011-10-13 | 2018-05-09 | 삼성전자주식회사 | 불휘발성 메모리 장치, 불휘발성 메모리 장치의 프로그램 방법, 불휘발성 메모리 장치를 포함하는 메모리 시스템 |
US20130173655A1 (en) | 2012-01-04 | 2013-07-04 | International Business Machines Corporation | Selective fetching of search results |
KR20130100459A (ko) * | 2012-03-02 | 2013-09-11 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그 제조 방법 |
US8519516B1 (en) | 2012-03-12 | 2013-08-27 | Micron Technology, Inc. | Semiconductor constructions |
KR102008422B1 (ko) * | 2012-12-17 | 2019-08-08 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 및 그 제조 방법 |
US20150060971A1 (en) * | 2013-09-03 | 2015-03-05 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing the same |
US9252148B2 (en) * | 2014-01-22 | 2016-02-02 | Micron Technology, Inc. | Methods and apparatuses with vertical strings of memory cells and support circuitry |
-
2014
- 2014-01-22 US US14/161,170 patent/US9252148B2/en active Active
-
2015
- 2015-01-21 CN CN201580011706.0A patent/CN106104693B/zh active Active
- 2015-01-21 CN CN201910599243.4A patent/CN110400589A/zh active Pending
- 2015-01-21 JP JP2016548071A patent/JP6367956B2/ja active Active
- 2015-01-21 WO PCT/US2015/012185 patent/WO2015112557A1/en active Application Filing
- 2015-01-21 KR KR1020187027206A patent/KR102193562B1/ko active IP Right Grant
- 2015-01-21 EP EP15740682.8A patent/EP3097561A4/en not_active Withdrawn
- 2015-01-21 KR KR1020167022761A patent/KR101939109B1/ko active IP Right Grant
-
2016
- 2016-02-01 US US15/011,819 patent/US10319729B2/en active Active
-
2019
- 2019-05-21 US US16/418,743 patent/US10910389B2/en active Active
-
2021
- 2021-02-01 US US17/164,375 patent/US11430798B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10910389B2 (en) | 2014-01-22 | 2021-02-02 | Micron Technology, Inc. | Methods and apparatuses with vertical strings of memory cells and support circuitry |
US11430798B2 (en) | 2014-01-22 | 2022-08-30 | Micron Technology, Inc. | Methods and apparatuses with vertical strings of memory cells and support circuitry |
Also Published As
Publication number | Publication date |
---|---|
CN110400589A (zh) | 2019-11-01 |
CN106104693B (zh) | 2019-07-26 |
US11430798B2 (en) | 2022-08-30 |
US20160148943A1 (en) | 2016-05-26 |
US9252148B2 (en) | 2016-02-02 |
WO2015112557A1 (en) | 2015-07-30 |
US10910389B2 (en) | 2021-02-02 |
EP3097561A4 (en) | 2018-01-03 |
KR20160111978A (ko) | 2016-09-27 |
EP3097561A1 (en) | 2016-11-30 |
KR20180107316A (ko) | 2018-10-01 |
KR101939109B1 (ko) | 2019-04-11 |
CN106104693A (zh) | 2016-11-09 |
US20150206587A1 (en) | 2015-07-23 |
US20190341394A1 (en) | 2019-11-07 |
US20210265370A1 (en) | 2021-08-26 |
US10319729B2 (en) | 2019-06-11 |
KR102193562B1 (ko) | 2020-12-23 |
JP2017504217A (ja) | 2017-02-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6367956B2 (ja) | メモリセル及びサポート回路の縦ストリングを有する方法及び機器 | |
US9385138B2 (en) | Memory devices including vertical pillars and methods of manufacturing and operating the same | |
US20150054090A1 (en) | 3dic system with a two stable state memory | |
KR20130005430A (ko) | 불휘발성 메모리 소자 및 그 제조방법 | |
TW201448234A (zh) | 非揮發性記憶體結構 | |
JP2022545251A (ja) | 集積アセンブリ及び集積アセンブリを形成する方法 | |
CN113841240A (zh) | 具有延伸穿过交替材料的堆叠的导电柱的集成组合件 | |
TW202143436A (zh) | 記憶體裝置及形成記憶體裝置之方法 | |
US9337145B2 (en) | Semiconductor memory device | |
TW202125784A (zh) | 半導體記憶裝置 | |
US10177163B1 (en) | SOI-based floating gate memory cell | |
JP7399990B2 (ja) | コンデンサ構造体 | |
TWI792353B (zh) | 半導體裝置以及形成半導體裝置的方法 | |
TWI594401B (zh) | 簡單及免費的多次可程式結構 | |
CN110034121A (zh) | 形成集成电路阱结构的方法 | |
TWI843366B (zh) | 半導體器件、記憶體器件及半導體器件的形成方法 | |
WO2023130203A1 (en) | Semiconductor devices, memory devices, and methods for forming the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20161012 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160824 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170824 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170829 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170922 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180109 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180208 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180605 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180705 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6367956 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |