JP6008582B2 - 半導体パッケージ、放熱板及びその製造方法 - Google Patents
半導体パッケージ、放熱板及びその製造方法 Download PDFInfo
- Publication number
- JP6008582B2 JP6008582B2 JP2012121193A JP2012121193A JP6008582B2 JP 6008582 B2 JP6008582 B2 JP 6008582B2 JP 2012121193 A JP2012121193 A JP 2012121193A JP 2012121193 A JP2012121193 A JP 2012121193A JP 6008582 B2 JP6008582 B2 JP 6008582B2
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- metal foil
- layer
- insulating member
- metal
- insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012121193A JP6008582B2 (ja) | 2012-05-28 | 2012-05-28 | 半導体パッケージ、放熱板及びその製造方法 |
| US13/894,565 US8994168B2 (en) | 2012-05-28 | 2013-05-15 | Semiconductor package including radiation plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012121193A JP6008582B2 (ja) | 2012-05-28 | 2012-05-28 | 半導体パッケージ、放熱板及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013247293A JP2013247293A (ja) | 2013-12-09 |
| JP2013247293A5 JP2013247293A5 (enExample) | 2015-07-09 |
| JP6008582B2 true JP6008582B2 (ja) | 2016-10-19 |
Family
ID=49620955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012121193A Active JP6008582B2 (ja) | 2012-05-28 | 2012-05-28 | 半導体パッケージ、放熱板及びその製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8994168B2 (enExample) |
| JP (1) | JP6008582B2 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11309228B2 (en) | 2019-10-08 | 2022-04-19 | Samsung Electronics Co., Ltd. | Packaged semiconductor devices having enhanced thermal transport and methods of manufacturing the same |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6059074B2 (ja) * | 2013-04-26 | 2017-01-11 | アオイ電子株式会社 | 半導体装置の製造方法 |
| DE102013216709B4 (de) * | 2013-08-22 | 2021-03-25 | Infineon Technologies Ag | Halbleiteranordnung, verfahren zur herstellung einer anzahl von chipbaugruppen und verfahren zur herstellung einer halbleiteranordnung |
| KR102392202B1 (ko) * | 2015-04-09 | 2022-05-02 | 삼성전자주식회사 | 방열막을 구비한 반도체 패키지 및 그 제조방법 |
| CN104916602A (zh) * | 2015-04-22 | 2015-09-16 | 华进半导体封装先导技术研发中心有限公司 | 用于埋入晶圆级球栅阵列封装的散热结构 |
| US10692794B2 (en) * | 2016-01-14 | 2020-06-23 | Mitsubishi Electric Corporation | Radiation plate structure, semiconductor device, and method for manufacturing radiation plate structure |
| KR102486784B1 (ko) * | 2016-08-26 | 2023-01-09 | 삼성전기주식회사 | 반도체 패키지 |
| CN107960004A (zh) * | 2016-10-14 | 2018-04-24 | 鹏鼎控股(深圳)股份有限公司 | 可伸缩电路板及其制作方法 |
| CN111341750B (zh) * | 2018-12-19 | 2024-03-01 | 奥特斯奥地利科技与系统技术有限公司 | 包括有导电基部结构的部件承载件及制造方法 |
| KR102600004B1 (ko) | 2018-12-26 | 2023-11-08 | 삼성전자주식회사 | 반도체 패키지 |
| KR102584991B1 (ko) * | 2019-06-14 | 2023-10-05 | 삼성전기주식회사 | 반도체 패키지 |
Family Cites Families (28)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS5513970Y2 (enExample) * | 1973-07-24 | 1980-03-29 | ||
| JPS62238653A (ja) * | 1986-04-09 | 1987-10-19 | Nec Corp | 冷却構造 |
| JPH04207061A (ja) * | 1990-11-30 | 1992-07-29 | Shinko Electric Ind Co Ltd | 半導体装置 |
| JPH0520365U (ja) * | 1991-08-22 | 1993-03-12 | 日本電気株式会社 | 集積回路の放熱実装構造 |
| JPH0897336A (ja) * | 1994-09-29 | 1996-04-12 | Shinko Electric Ind Co Ltd | 半導体装置 |
| JP3269397B2 (ja) * | 1995-09-19 | 2002-03-25 | 株式会社デンソー | プリント配線基板 |
| US6489668B1 (en) * | 1997-03-24 | 2002-12-03 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
| JP2000223627A (ja) | 1999-01-29 | 2000-08-11 | Nec Corp | フリップチップパッケージ |
| JP2001210761A (ja) * | 2000-01-24 | 2001-08-03 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| JP2001274196A (ja) * | 2000-03-28 | 2001-10-05 | Rohm Co Ltd | 半導体装置 |
| JP2004172489A (ja) * | 2002-11-21 | 2004-06-17 | Nec Semiconductors Kyushu Ltd | 半導体装置およびその製造方法 |
| KR20050001930A (ko) * | 2003-06-28 | 2005-01-07 | 삼성전기주식회사 | 고밀도 칩 스케일 패키지 및 그 제조 방법 |
| TWI246760B (en) * | 2004-12-22 | 2006-01-01 | Siliconware Precision Industries Co Ltd | Heat dissipating semiconductor package and fabrication method thereof |
| US8022532B2 (en) * | 2005-06-06 | 2011-09-20 | Rohm Co., Ltd. | Interposer and semiconductor device |
| JP2007123524A (ja) * | 2005-10-27 | 2007-05-17 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板 |
| CN102098876B (zh) * | 2006-04-27 | 2014-04-09 | 日本电气株式会社 | 用于电路基板的制造工艺 |
| JP4277036B2 (ja) * | 2006-09-29 | 2009-06-10 | Tdk株式会社 | 半導体内蔵基板及びその製造方法 |
| JP5326269B2 (ja) * | 2006-12-18 | 2013-10-30 | 大日本印刷株式会社 | 電子部品内蔵配線板、及び電子部品内蔵配線板の放熱方法 |
| US20090057903A1 (en) * | 2007-03-29 | 2009-03-05 | Yoshio Okayama | Semiconductor module, method for manufacturing semiconductor modules, semiconductor apparatus, method for manufacturing semiconductor apparatuses, and portable device |
| JP4993754B2 (ja) * | 2008-02-22 | 2012-08-08 | 新光電気工業株式会社 | Pga型配線基板及びその製造方法 |
| US8569892B2 (en) * | 2008-10-10 | 2013-10-29 | Nec Corporation | Semiconductor device and manufacturing method thereof |
| JP2010103244A (ja) * | 2008-10-22 | 2010-05-06 | Sony Corp | 半導体装置及びその製造方法 |
| JP5295932B2 (ja) * | 2009-11-02 | 2013-09-18 | 新光電気工業株式会社 | 半導体パッケージ及びその評価方法、並びにその製造方法 |
| JP2012015225A (ja) | 2010-06-30 | 2012-01-19 | Hitachi Ltd | 半導体装置 |
| KR101131288B1 (ko) * | 2010-12-06 | 2012-03-30 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
| JP2012186393A (ja) * | 2011-03-07 | 2012-09-27 | Fujitsu Ltd | 電子装置、携帯型電子端末機、及び電子装置の製造方法 |
| JP5838065B2 (ja) * | 2011-09-29 | 2015-12-24 | 新光電気工業株式会社 | 熱伝導部材及び熱伝導部材を用いた接合構造 |
| JP5940799B2 (ja) * | 2011-11-22 | 2016-06-29 | 新光電気工業株式会社 | 電子部品搭載用パッケージ及び電子部品パッケージ並びにそれらの製造方法 |
-
2012
- 2012-05-28 JP JP2012121193A patent/JP6008582B2/ja active Active
-
2013
- 2013-05-15 US US13/894,565 patent/US8994168B2/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11309228B2 (en) | 2019-10-08 | 2022-04-19 | Samsung Electronics Co., Ltd. | Packaged semiconductor devices having enhanced thermal transport and methods of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| US8994168B2 (en) | 2015-03-31 |
| JP2013247293A (ja) | 2013-12-09 |
| US20130313697A1 (en) | 2013-11-28 |
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