CN111696950A - 具有部分凹进电容器的封装衬底 - Google Patents

具有部分凹进电容器的封装衬底 Download PDF

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Publication number
CN111696950A
CN111696950A CN202010173333.XA CN202010173333A CN111696950A CN 111696950 A CN111696950 A CN 111696950A CN 202010173333 A CN202010173333 A CN 202010173333A CN 111696950 A CN111696950 A CN 111696950A
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China
Prior art keywords
capacitor
electrical contacts
solder
package
conductive layer
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CN202010173333.XA
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English (en)
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J·M·威廉姆森
S·辛哈
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Texas Instruments Inc
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Texas Instruments Inc
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Publication of CN111696950A publication Critical patent/CN111696950A/zh
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Abstract

本申请公开具有部分凹进电容器的封装衬底。一种半导体封装(100)，其包括多层衬底(110)，该多层衬底包括：介电层(114、116A、116B)；形成第一组电触点(124)的第一导电层(120)；形成封装电触点(134)和两个电容器电触点(136)的第二导电层(130)；在第一导电层与第二导电层之间延伸穿过介电层的导电通孔(118、119)；以及第二导电层的上方的阻焊层(146)。该半导体封装进一步包括多层衬底的第一侧(111)上的半导体管芯(140)，该半导体管芯电连接多层衬底的第二侧(112)上的电容器(160)。电容器的凹进部分在两个电容器电触点与阻焊层的板侧表面之间的阻焊层的电容器开口(158)内。

Description

具有部分凹进电容器的封装衬底
相关申请
本申请要求2019年12月31日提交的美国临时申请号62/955,504以及2019年3月13日提交的美国临时申请号62/817,936的权益和优先权，两者在此均通过引用整体并入本文。
技术领域
本公开涉及半导体封装。
背景技术
在半导体技术的长期趋势中，小型化、集成化和速度化的趋势有增无减。这些趋势包括在不改变封装的形状因素的情况下减薄现有封装设计，并且在现有封装设计中添加诸如一个或多个附加的半导体管芯和/或附加的无源组件或有源组件(诸如传感器、电容器、变压器等)的组件。
在特定方面，用于滤波数据和/或功率信号的电容器可以被集成在封装内。一般而言，优选将封装电容器定位在半导体管芯附近，以减小包括半导体管芯和电容器的导电回路的电阻抗。
发明内容
电容器以路侧(land side)电容器(LSC)配置被安装到与半导体管芯相对的封装的衬底上，诸如在半导体管芯的剖面下方。与管芯侧(die side)电容器(DSC)配置相比，因为电容器和半导体管芯之间的衬底导体延伸穿过衬底的厚度，而不是延伸到半导体管芯的剖面的外面的位置，所以LSC配置支持更低的电感。
与以DSC配置被安装的电容器相比，以LSC配置被安装的电容器允许更低的电感；然而，这种电容器必须适合在半导体封装的衬底和板之间的距离(gap)内。对于具有球栅阵列连接的封装，此距离由球栅阵列的塌陷焊球的焊点互连高度(standoff height)设置。具有低剖面的电容器更适合以LSC配置安装。一般而言，随着阵列的间距(pitch)(间隔(spacing))减小，球栅阵列的塌陷焊球的焊点互连高度减小。
如本文中进一步公开的，封装衬底的阻焊层(solder mask layer)包括在衬底的导电层的两个电容器电触点的上方的电容器开口。电容器被安装在电容器开口内，其中电容器的厚度至少部分地凹进电容器开口内。这样的设计允许电容器具有比将电容器安装在封装衬底的阻焊层上方的可替代设计更厚的剖面。
在一个示例中，半导体封装包括多层衬底，该多层衬底包括：介电层；在介电层的第一侧上形成第一组电触点的第一导电层；在介电层的第二侧上形成第二组电触点的第二导电层，该第二组电触点包括封装电触点和两个电容器电触点；在第一导电层与第二导电层之间延伸穿过介电层的导电通孔；以及在第二导电层上方的阻焊层，该阻焊层形成与封装电触点相邻的电触点开口，并且在两个电容器电触点的上方形成电容器开口。该半导体封装进一步包括半导体管芯和电容器，该半导体管芯在多层衬底的第一侧上并且电连接到第一组电触点，该电容器在多层衬底的第二侧上并且经由两个电容器电触点和多层衬底衬底电连接到半导体管芯，其中电容器的凹进部分在两个电容器电触点与阻焊层的板侧表面之间的电容器开口内。
在另一个示例中，半导体封装衬底包括：介电层；在介电层的第一侧上形成第一组电触点的第一导电层；在介电层的第二侧上形成第二组电触点的第二导电层，该第二组电触点包括封装电触点和两个电容器电触点；穿过介电层电连接第一导电层与第二导电层的导电通孔；以及在第二导电层上方的阻焊层，该阻焊层形成与每个封装电触点相邻的电触点开口，并且在两个电容器电触点的上方形成电容器开口。电容器开口具有半径至少是阻焊层厚度的50％的圆角(rounded)形状。
在另一个示例中，形成封装的方法包括将半导体管芯安装在多层衬底上，以将半导体管芯电连接到多层衬底的第一组电触点。多层衬底包括：介电层；在介电层的第一侧上形成第一组电触点的第一导电层；在介电层的第二侧上形成第二组电触点的第二导电层，该第二组电触点包括封装电触点和两个电容器电触点；在第一导电层与第二导电层之间延伸穿过介电层的导电通孔；以及在第二导电层上方的阻焊层，该阻焊层形成与封装电触点相邻的电触点开口，并且在两个电容器电触点的上方形成电容器开口。该方法进一步包括将电容器安装在两个电容器电触点上，以将电容器电连接到两个电容器电触点，其中电容器的凹进部分在两个电容器电触点与阻焊层的板侧表面之间的电容器开口内。
附图说明
图1A至图1C示出具有安装在封装的阻焊层的电容器开口内的电容器的半导体封装。
图2是安装到印刷电路板(PCB)的图1A至图1C的半导体封装的组装件。
图3A至图3G示出图1A至图1C的半导体封装的制造步骤。
图4是制造具有安装在封装的阻焊层的电容器开口内的电容器的半导体封装(诸如图1A至图1C的半导体封装)的方法的流程图。
图5示出具有安装在封装的阻焊层的电容器开口内的电容器的半导体封装，该电容器开口包括圆角边。
具体实施方式
具有适合用作电容器的厚度的低剖面电容器可能无法提供期望的功能性和/或可靠性等级，特别是对于小间距球栅阵列。为了促进将具有较厚剖面的电容器用作电容器，本文公开的半导体封装包括阻焊层，该阻焊层具有在封装衬底的导电层的电容器电触点的上方的电容器开口。电容器被安装在电容器开口内，其中电容器的厚度至少部分地凹进电容器开口内。这样的配置减小电容器相对于阻焊层的板侧表面的焊点互连高度，从而允许电容器具有比其中电容器被安装在封装衬底的阻焊层的上方的替代设计更厚的剖面。较厚的电容器可以提供附加的容量或可靠性。此外，因为球栅阵列的塌陷焊球的焊点互连高度随着阵列的间距(间隔)减小而减小，所以这样的设计可以进一步促进对封装球栅阵列使用减小的间距。参照图1A至图1C示出并且描述利用这些技术的示例封装即半导体封装100。
图1A是半导体封装100的透视图，其示出安装在阻焊层156的电容器开口158内的电容器160，而图1B是半导体封装100的分解透视图，并且图1C是半导体封装100的截面侧视图。半导体封装100包括：多层衬底110；包括管芯端子142的半导体管芯140；以及包括电容器端子162的电容器160。如图1C所示，多层衬底110包括介电芯114，在其上具有图案化的内部导电层117。导电芯通孔119代表一个或多个导电通孔，该一个或多个导电通孔在内部导电层117之间穿过介电芯114形成电连接。堆积的介电层116A、堆积的介电层116B(统称为“介电层116”)覆盖内部导电层117。
在多层衬底110的第一侧111上，外部导电层120形成第一组电触点，该第一组电触点包括代表管芯附接部位122的一组管芯触点124。管芯触点124与管芯端子142相对应。半导体管芯140被安装到管芯附接部位122，其中管芯端子142被电连接到管芯触点124。例如，半导体管芯140可以使用焊料凸块或焊料尖金属(诸如铜柱)利用倒装芯片连接被安装到管芯附接部位122。多层衬底110进一步包括外部导电层130和介电层116的第二侧112。
导电层130形成第二组电触点，该第二组电触点包括封装电触点134和用于连接到电容器160的两个电容器电触点136。封装电触点134与焊球阵列150相对应。外部导电层130的封装电触点134围绕电容器电触点136。电容器160被安装在阻焊层156的电容器开口158内，其中电容器端子162电连接到两个电容器电触点136，电容器160的厚度部分地凹进电容器开口158内。具体地，电容器160的凹进部分是在电容器电触点136和阻焊层156的板侧表面之间开口的电容器开口158。这种配置减小电容器160相对于阻焊层156的板侧表面的焊点互连高度，并且允许选择较厚的电容器用作电容器160。较厚的电容器可以提供附加的容量或可靠性。
内部导电层117形成在介电芯114上和介电芯114内。介电层116代表介电芯114和内部导电层117上方的堆积层。多层衬底110的电导体包括在衬底110的侧111处的介电层116A上的外部导电层120，以及在衬底110的侧112处的介电层116B上的外部导电层130。内部导电层117包括与一个或多个导电通孔(诸如导电芯通孔119)互连的二维图案的金属迹线。进而，内部导电盲孔118提供内部导电层117与外部导电层120、外部导电层130之间的电连接。类似地，外部导电层120、外部导电层130包括与盲孔118和内部导电层117结合以提供封装100的组件和焊球阵列150之间的电连接的图案化金属迹线。
介电芯114和介电层116可以代表层压衬底，并且内部导电层117可以在介电芯114和介电层116的层压层之间延伸。如图1C所示的内部导电层117、多层衬底110的内部导电盲孔118和导电通孔119的数量和布局仅是概念性的，并且多层衬底110的导体的任何数量的配置都是可能的。在图1C的示例中，介电芯114和介电层116代表具有两个内部导电层117的三层介电衬底。其他示例可以包括不同数量的层，诸如具有六个内部导电层的七层介电衬底。
多种材料可以被选择用于介电芯114和介电层116，并且每层可以包括相同或不同的材料成分。作为非限制性示例，介电芯114和介电层116可以由包括诸如聚酰亚胺的惰性聚合物材料的陶瓷材料或有机材料形成。诸如树脂(包括环氧树脂、聚氨酯树脂或硅树脂)的其他有机材料还可以被选择用于介电芯114和介电层116。在一些示例中，介电芯114和介电层116的各种层可以被填充或不被填充并且包括以下材料的一种或多种：树脂、硬化剂、固化剂、熔融二氧化硅、无机填料、催化剂、阻燃剂、应力改性剂、增粘剂和其他合适的组分。可以选择填料(如果有的话)，以修改树脂基体材料的性能和特性。可以选择惰性无机填料以降低CTE，增加热导率和/或增加弹性模量。与树脂基体材料相比，可以选择颗粒状填料以降低诸如拉伸强度和挠曲强度的强度特性。
多层衬底110的厚度可以在0.1mm至1mm的范围内，诸如约0.20mm、0.40mm或0.80mm，诸如在0.15mm至0.50mm的范围内。在厚度小于0.1mm或甚至小于0.15mm的情况下，取决于电流和所选择的衬底材料，多层衬底110的导电层120、导电层130之间的介电芯114和介电层116可能无效。
封装100可以进一步包括在多层衬底110的侧111上的导电层120的上方的阻焊层146。阻焊层146是覆盖外部导电层120的电迹线的电绝缘层，并且包括用于管芯附接部位122的电触点的开口。
半导体管芯140的有源侧在外部导电层120的管芯附接部位122处被安装到多层衬底110，并且在管芯端子142处用焊料凸块143固定。底部填充144填充半导体管芯140和多层衬底110的界面。如本文所使用的，半导体管芯的有源侧是包括导电管芯端子的一侧，该导电管芯端子用作将半导体管芯的组件连接到诸如衬底或引线框架的外部元件的端子。例如，半导体管芯140在其有源侧上包括金属化的管芯端子142。管芯端子142可以是例如铝焊盘或铜焊盘。管芯端子可以包括诸如铜焊盘上的镀铜的凸块的镀覆的凸块。
半导体管芯140的有源侧由诸如聚酰亚胺的惰性聚合物材料的电绝缘层(未示出)保护，该电绝缘层可以在晶片单片化之前已经被施加到用于形成半导体管芯140的半导体晶片的表面。半导体管芯140的电绝缘层具有多个开口以暴露管芯端子142。图1C仅是概念说明，并且各种示例可以包括半导体管芯140上的任何数量的管芯端子142，其具有形成导电层120的管芯附接部位122的电触点的对应图案。
多层衬底110将半导体管芯140连接到封装电触点134和焊球阵列150。封装100提供扇出(fan-out)配置，在该扇出配置中多层衬底110的侧112上的封装电触点134形成阵列，该阵列覆盖的面积大于半导体管芯140的有源侧上的管芯端子142。
半导体封装100进一步包括与管芯端子142相对地热耦合到半导体管芯140的散热器170。散热器170可以代表覆盖在半导体管芯140和多层衬底110的侧111的上方的成形金属(诸如冲压金属)。在包括模制的半导体封装的替代示例中，散热器170可以被省略或可以通过封装模塑料覆盖半导体管芯被固定。半导体管芯140的无源侧包括与散热器170相邻的热界面材料148，以改善散热。在各种示例中，热界面材料148可以代表导热膏或导热带。
散热器170通过粘合剂178被固定到半导体管芯140的外围之外的阻焊层146，粘合剂178也可以代表热界面材料。在一些示例中，散热器170可以被电连接到外部导电层120(诸如外部导电层120的接地部分)。在这样的示例中，粘合剂178可以代表焊料或导电的热界面材料。散热器170进一步覆盖多层衬底110的侧111的全部或部分。以这种方式，散热器170可以进一步代表用于多层衬底110的侧111上的半导体管芯140和其他组件(未示出)的保护性覆盖物。
除了散热器170和热界面材料148之外或作为散热器170和热界面材料148的替代，焊球阵列150可以利用热焊料凸块以促进从半导体管芯140和半导体封装100的其他组件到外部板的热传递。
如图1A至图1C所示，半导体封装100是无模半导体封装。在其他示例中，利用至少部分地凹进阻焊层的电容器开口内的电容器的半导体封装可以包括保护半导体管芯140和封装的其他组件的模塑料。这样的模制封装可以包括或可以不包括将半导体管芯热耦合到封装的外表面的散热器。
阻焊层156覆盖导电层130，阻焊层156形成与每个封装电触点134相邻的电触点开口159，并且在两个电容器电触点136的上方形成电容器开口158。在一些示例中，封装电触点134可以是阻焊层限定，并且电容器电触点136是非阻焊层限定。如本文所指，阻焊层限定是指阻焊层在电触点的上方形成周界，其中仅导电层(诸如导电层130)的平坦部分被暴露以(诸如与电触点开口159)形成电接触。相反，在非阻焊层限定的电触点的情况下，图案化导电层的至少一个边缘被暴露在阻焊层开口内。在非阻焊层限定的开口的情况下，焊接圆角/焊角(solder fillet)可以被形成在导电层的暴露边缘上，如直接焊料连接164，其将电容器电触点136与阻焊层156的电容器开口158内的电容器160的电容器端子162电连接。
半导体封装100进一步包括在电触点开口159内而不是在电容器开口158内的预焊料151。在一些示例中，电容器电触点136包括在形成导电层130的贱金属的上方的可焊层(诸如有机可焊保护剂)。在回流以将电容器160的电容器端子162附接到电容器开口158内的电容器电触点136之前，这种可焊层可以防止减轻电容器电触点136的氧化或其他腐蚀。这样的示例可以包括在将电容器160放置在电容器开口158内之前或之后丝网印刷焊膏到电容器开口158内的电触点136，并且加热多层衬底110的组装件和电容器160以回流焊料以形成直接焊料连接164。
在各个示例中，内部导电层117、盲孔118和外部导电层130的贱金属可以包括铜、铜合金、铝、铝合金、铁镍合金或镍钴铁合金。作为组装件，多层衬底110的大多数贱金属被覆盖。例如，内部导电层117被堆积的介电层116覆盖，并且盲孔118被外部导电层120、外部导电层130覆盖。此外，外部导电层120大部分被阻焊层146覆盖，而管芯触点124被预焊料141覆盖。类似地，外部导电层120大部分被阻焊层156覆盖，而封装电触点134被预焊料151覆盖。
电容器电触点136可以被可焊层处理以抵抗氧化。这样的可焊层可以是贱金属表面上的其他金属的薄层的涂层。在一些示例中，平面贱金属可以被镀有抗氧化的镀层。在一个示例中，镀层可以包括镀在贱金属上的镍层和镀在镍层上的钯层。在一些这样的示例中，金层可以被镀在钯层上。作为一个示例，当铜形成外部导电层130的贱金属时，可以使用锡的镀层或者镍层(在一些示例中，厚度约0.5μm至2.0μm)，随后是钯层(在相同或不同示例中，厚度约0.01μm至0.1μm)，可选地随后是最外金层(在相同或不同示例中，厚度约为0.003μm至0.009μm)。这样的贱金属和镀层的组合在外部导电层130的暴露部分处(诸如在电容器电触点136处)提供对诸如氧化的腐蚀的抵抗，同时促进电容器电触点136与电容器160的电容器端子162之间的直接焊料连接164。
虽然在完成的多层衬底110中外部导电层130的其他部分可以被覆盖衬底，但是可以优选地在应用阻焊层156之前或在图案化阻焊层156以形成电触点开口159和电容器开口158之后处理外部导电层130的整个暴露表面。在这样的示例中，封装电触点134和电容器电触点136两者都可以包括抗氧化层。
作为抗氧化的可焊金属层的替代或补充，电容器电触点136可以被有机可焊保护剂覆盖。在一些特定示例中，预焊料141可以被省略，并且封装电触点134也可以被有机可焊保护剂覆盖。在具有或不具有预焊料141的情况下，在阻焊层156被应用在外部导电层130的上方之前，外部导电层130可以被有机可焊保护剂覆盖。类似地，在阻焊层146被应用之前，外部导电层120可以被有机可焊保护剂覆盖。
电容器160被安装在电容器开口158内，其中电容器端子162电连接到两个电容器电触点136，电容器160的厚度部分地凹进电容器开口158内。具体地，电容器160的凹进部分是在电容器电触点136和阻焊层156的板侧表面之间开口的电容器开口158。例如，电容器160可以部分地凹进电容器开口158内至少0.10毫米的深度。这样的示例可以包括在将电容器160放置在电容器开口158内之前或之后丝网印刷焊膏到电容器开口158内的电触点136，并且加热多层衬底110的组装件和电容器160以回流焊料以形成直接焊料连接164。
直接焊料连接164在电容器端子162和两个电容器电触点136之间延伸。电容器开口158帮助容纳焊料，以防止由于应用直接焊料连接164而引起电容器电触点136与相邻的封装电触点134之间的短路。
在一些示例中，电容器端子162和两个电容器电触点136彼此直接物理接触或仅通过直接焊料连接164的毛细流分开。这种毛细流的厚度远小于预焊料151的厚度。例如，虽然预焊料151的厚度可以至少等于阻焊层156的厚度，但是电容器端子162和两个电容器电触点136之间的焊料的毛细流可以小于阻焊层156的厚度的一半，诸如小于阻焊层156的厚度的百分之十。此外，直接焊料连接164可以具有比预焊料151低的熔化温度，使得电容器160安装到多层衬底110不熔化预焊料151。
在一些示例中，电容器160是多层陶瓷贴片电容器160。在相同或不同的示例中，电容器160可以通过2010年6月1日修订版D的AEC-Q200应力测试认证(在本文中称为，“通过AEC-Q200认证”)。在某些需要半导体封装100稳健可靠运行的应用中，要求通过AEC-Q200认证。例如，飞机应用、汽车应用和/或军事应用要求通过AEC-Q200认证的组件。关于电容器160，通过AEC-Q200认证的各种多层陶瓷贴片电容器的厚度通常比没有通过AEC-Q200认证的多层陶瓷贴片电容器的厚度大。在通过AEC-Q200认证的多层陶瓷贴片电容器以LSC配置被安装时，该多层陶瓷贴片电容器的厚度可以减少或消除与板的间隙(clearance)，使得如果某些或全部通常可用的通过AEC-Q200认证的多层陶瓷贴片电容器被定位在阻焊层156的顶部上时，其可能不适合。将电容器160凹进电容器开口158内增加电容器160和板之间的间隙，这可以允许某些通过AEC-Q200认证的多层陶瓷贴片电容器被用作半导体封装100中的电容器160。
焊球阵列150的焊料凸块位于阻焊层156的电触点开口159处的封装电触点134的上方的预焊料151上，以促进通过例如焊料回流工艺与外部装置的连接。例如，焊球阵列150可以代表球栅阵列。在各种示例中，焊球阵列150可以符合诸如倒装芯片球栅阵列(FCBGA)或引线键合细间距球栅阵列(FBGA)的各种配置。注意，为了简化，在图1C和图2中已经减少了封装100上的焊球阵列150中的焊料凸块的数量。
图2是安装到PCB 180的半导体封装100的组装件190。PCB 180包括衬底182(诸如有机衬底)，其具有由衬底182上或衬底182内的导电迹线形成的接触焊盘184。PCB 180可以包括若干导电层和若干介电层以及任何数量的电子组件和电路。
如图2所示，焊球阵列150的塌陷焊球提供具有距离192的焊点互连高度。如关于图1A至图1C所讨论的，电容器160通过阻焊层156的厚度194部分地凹进电容器开口158内。在电容器160部分地凹进电容器开口158内时，电容器160与PCB 180具有间隙距离196。
在一些特定示例中，电容器160可以具有至少0.30毫米(mm)(诸如约0.35mm)的厚度。在相同或不同示例中，当将半导体封装100安装到诸如PCB180的外部板时，焊球阵列150的塌陷焊球可以提供不大于0.40mm的塌陷厚度。不大于0.40mm的塌陷厚度对应于0.8mm的焊球间距。在这样的示例中，电容器160在电容器开口158内部分地凹进至少0.05mm(诸如至少0.10mm)的厚度194。因此，电容器160部分地凹进电容器开口158内，以提供与PCB 180的至少0.15mm的间隙距离196。
与PCB 180的至少0.15mm的间隙距离196对于支持组装件190的可制造性是重要的。例如，当考虑到多个组装件190的制造过程中的制造差异时，这种间隙可以限制电容器160和PCB 180之间的直接接触。这种间隙可以限制由直接接触或较小的间隙距离196所导致的电容器160与PCB 180的电迹线之间的电短路。此外，电容器160与PCB 180之间的直接接触可以导致电容器160随时间推移的退化和故障，从而限制组装件190的可靠性。当然，这些尺寸仅是示例，并且其他合适的尺寸可以应用于特定的应用。
图3A至图3C示出形成多层衬底110的步骤。图3D至图3G示出由多层衬底110形成半导体封装100的步骤。图4是制造包括电容器的半导体封装的方法的流程图，该电容器被安装在诸如图1A至图1C的封装100的封装的阻焊层的电容器开口内。为了清楚起见，相对于封装100和图3A至图3G描述图4的技术；然而，所描述的技术也可以用于其他半导体封装的制造中。
在图3A中示出包括未图案化的阻焊层146、未图案化的阻焊层156的部分完成的多层衬底110。为了形成多层衬底110，将图案化的金属层与介电芯114上的介电层交替。首先，在介电芯114上形成内部导电层117和导电芯通孔119。通过钻孔(机械钻孔或激光钻孔)以产生空腔，然后例如通过电镀或溅射用金属填充该空腔，导电芯通孔119可以被形成在介电芯114内，。形成内部导电层117可以包括例如电镀或溅射，然后进行光刻。在一些示例中，在钻孔用于导电芯通孔119的介电芯114之后，导电芯通孔119和内部导电层117可以一致地形成。
介电层116是内部导电层117的上方的堆积层。可以通过钻孔(机械钻孔或激光钻孔)以产生空腔，然后例如通过电镀或溅射用金属填充该空腔，在介电层116内形成内部导电盲孔118。外部导电层120、外部导电层130例如通过电镀或溅射然后进行光刻被图案化在介电层116上。在一些示例中，可以结合相邻导电层的电镀或溅射以填充盲孔118。阻焊层146被应用在外部导电层120的上方，并且阻焊层156被应用在外部导电层130的上方。
如图3B所示，图3A的部分完成的多层衬底110的阻焊层146、阻焊层156被图案化。图案化阻焊层146、阻焊层156可以包括进行光刻。具体地，在管芯触点124的上方图案化阻焊层146以去除阻焊层以形成用于管芯附接部位122的电触点开口。在封装电触点134的上方图案化阻焊层156以去除阻焊层以形成用于焊球阵列150的电触点开口159，并且进一步形成电容器开口158(图4，步骤202)。在一些示例中，电触点开口159可以是阻焊层限定，并且电容器电触点136是非阻焊层限定，因为电容器开口158可以大于电容器电触点136和/或包括两个电容器电触点136。
如图3C所示，预焊料141被应用在用于阻焊层146的管芯附接部位122的电触点开口内。预焊料151也被应用在阻焊层156的电触点开口159内(图4，步骤204)。在该示例中，没有预焊料被应用在电容器开口158内；相反，电容器电触点136在多层衬底110的外表面上保持暴露。例如，可以通过焊料丝网印刷应用预焊料141、预焊料151。
通常在组装半导体封装之前，诸如多层衬底110的多层衬底被制造为单独的部件。由于这个原因，当多层衬底110暴露于周围环境时，多层衬底110的暴露表面应当抵抗退化。在一些示例中，在图案化阻焊层156之后，可以通过可焊层处理电容器电触点136以抵抗氧化(图4，步骤206)。在其他示例中，在应用阻焊层156之前，可以通过可焊层处理外部导电层130以抵抗氧化。在任一示例中，如先前关于半导体封装100所描述的，这种可焊层可以代表在贱金属表面上的其他金属薄层的沉积。
如图3D所示，在形成多层衬底110之后，半导体管芯140被安装在多层衬底110的管芯附接部位122上，以电连接多层衬底110的管芯触点124管芯端子142(图4，步骤208)。在管芯端子142和管芯附接部位122的电触点之间形成电连接。例如，将半导体管芯140布置在多层衬底110的管芯附接部位122上可以包括处理一组焊料凸块143。在一些示例中，焊料凸块143在被布置在管芯附接部位122上之前，可以被定位在管芯端子142上，作为半导体管芯140的部分。将半导体管芯140布置在管芯附接部位122上还经由多层衬底110将半导体管芯140电耦合至封装电触点134。焊料凸块143的回流也将半导体管芯140的有源侧固定到封装电触点134。底部填充144可以被应用在半导体管芯140和多层衬底110的界面处以通过毛细流填充半导体管芯140和多层衬底110的界面。
如图3E所示，散热器170被热耦合至半导体管芯140的无源侧(图4，步骤210)。半导体管芯140的无源侧包括与散热器170相邻的热界面材料148，以改善散热。在各种示例中，热界面材料148可以代表在将散热器170定位在半导体管芯140的上方之前被应用到半导体管芯140或散热器170的导热膏或导热带。
粘合剂178将散热器170的凸缘172固定到半导体管芯140周界外部的具有粘合剂178的阻焊层146，粘合剂178也可以代表热界面材料。在一些示例中，散热器170可以电连接到外部导电层120(诸如外部导电层120的接地部分)。在这样的示例中，粘合剂178可以代表焊料或导电的热界面材料。半导体封装100的替代方案包括模制半导体封装。在模制半导体封装中，可以用覆盖封装的半导体管芯的封装模塑料固定，或者可以根据模制半导体封装的散热要求被省略。
在将半导体管芯140布置在管芯附接部位122上以及将散热器170布置在半导体管芯140的上方之前或之后，电容器160被安装到电容器开口158内的电容器电触点136(图4，步骤212)。具体地，电容器160的两个电容器端子162被电连接到两个电容器电触点136，其中电容器160的厚度被部分地凹进电容器开口158内。具体地，电容器160的凹进部分是在电容器电触点136与阻焊层156的板侧表面之间开口的电容器开口158。例如，将电容器160安装在两个电容器电触点136上可以包括在电容器端子162和两个电容器电触点136之间应用液态焊料以形成直接焊料连接164，使得电容器端子162和两个电容器电触点136仅通过直接焊料连接164的毛细流分开。因为电容器160部分地凹进电容器开口158内，因此电容器开口158的边缘可以帮助将液态焊料容纳在电容器开口158内，从而减轻与相邻封装电触点134发生短路的风险。在电容器电触点136是非阻焊层限定的示例中，直接焊料连接164可以在电容器电触点136的暴露边缘的上方形成焊接圆角(solder fillet)/焊角，这可以改善直接焊料连接164、电容器电触点136与电容器端子162之间的粘附力。
结合电容器160在电容器开口158内的附接，焊球阵列150可以被应用到电触点开口159内的预焊料151以形成焊球阵列150(图4，步骤214)。例如，焊料凸块可以位于电触点开口159处的封装电触点134的上方的预焊料上，以促进例如通过焊料回流工艺与外部装置的连接。
在一些示例中，封装100可以被制造为在包括多个多层衬底110的公共衬底上一致地形成的至少两个封装的组的一部分。例如，多层衬底110可以被形成为多层衬底的阵列的一部分，并且散热器170可以作为散热器阵列的一部分被附接到多层衬底110，该散热器阵列由一致地附接到多层衬底阵列的公共衬底片材制成。
在组装封装100的阵列的多层衬底110、散热器170和半导体管芯140之后，可以例如通过在多层衬底的阵列的互连部分内切割以将封装100的阵列单片化。这种切割还可以包括在被附接在散热器170的阵列的上方的散热器170的阵列的互连部分内切割。锯切可以包括沿着网格的切口，使得每个封装100具有矩形剖面。
图5是半导体封装300的分解透视图。除了多层衬底110已经被多层衬底310代替之外，半导体封装300与半导体封装100类似。除了阻焊层356中的电容器开口358包括圆角边而不是正方形的角之外，多层衬底310与多层衬底110基本类似。为了简洁起见，关于半导体封装100所描述的许多细节不再关于半导体封装300重复。
与多层衬底110相比，电容器开口358的圆角边可以改善多层衬底310的电容器电触点136和电容器160之间的焊点完整性。电容器开口358的圆角形状将使接触电容器开口358的边缘的焊料流具有圆角形状。这样圆角形状的焊料可以具有减小的应力集中，从而减轻阻焊层356和焊料之间的分层。另外，圆角形状还可以减少或消除焊料与电容器开口358的角之间的接触区域中的距离的存在，这可以进一步减轻阻焊层356与焊料之间的分层。电容器开口358的形状与用于形成电容器开口358和阻焊层356中的电触点开口的光刻工艺的图案相对应。以这种方式，选择电容器开口358的形状仅涉及改变光刻工艺的图案。
在特定示例中，因为上述益处可能更限于较小的半径，所以电容器开口358的圆角形状的半径可以是阻焊层356的厚度的至少50％。最大半径仅受电容器开口358的尺寸和焊球阵列150内的可用空间的限制。在其他示例中，电容器开口358可以是不具有直边的圆角长方形，而不是具有圆角的矩形。
用于包括安装在阻焊层的电容器开口内的电容器的半导体封装的特定技术(包括关于半导体封装100、半导体封装300所描述的技术)，仅是对由所附权利要求所定义的本公开中所包括的一般发明构思的说明。

Claims (20)

1.一种半导体封装，其包括：
多层衬底，其包括：
介电层；
第一导电层，其在所述介电层的第一侧上形成第一组电触点；
第二导电层，其在所述介电层的第二侧上形成第二组电触点，所述第二组电触点包括封装电触点和两个电容器电触点；
导电通孔，其在所述第一导电层与所述第二导电层之间延伸穿过所述介电层；和
所述第二导电层的上方的阻焊层，所述阻焊层形成与所述封装电触点相邻的电触点开口，并且在所述两个电容器电触点的上方形成电容器开口；
半导体管芯，其在所述多层衬底的所述第一侧上，并且电连接到所述第一组电触点；和
电容器，其在所述多层衬底的所述第二侧上，并且经由所述两个电容器电触点和所述多层衬底电连接到所述半导体管芯，其中所述电容器的凹进部分在所述两个电容器电触点与所述阻焊层的板侧表面之间的所述电容器开口内。
2.根据权利要求1所述的半导体封装，
其中所述电触点开口是阻焊层限定，并且
其中所述两个电容器电触点是非阻焊层限定。
3.根据权利要求1所述的半导体封装，进一步包括在所述电容器的电容器端子和所述两个电容器电触点之间的直接焊料连接，所述电容器端子和所述两个电容器电触点仅通过所述直接焊料连接的毛细流分开。
4.根据权利要求1所述的半导体封装，还包括多个焊料凸块，所述多个焊料凸块形成与所述封装电触点相对应的焊球阵列，所述多个焊料凸块中的每一个在所述电触点开口内与所述封装电触点接触。
5.根据权利要求1所述的半导体封装，
其中所述两个电容器电触点是非阻焊层限定，
所述半导体封装进一步包括直接焊料连接，所述直接焊料连接在所述两个电容器电触点的暴露边缘的上方形成焊接圆角。
6.根据权利要求1所述的半导体封装，进一步包括在所述电触点开口内而不在所述电容器开口内的预焊料。
7.根据权利要求1所述的半导体封装，进一步包括在形成所述第二导电层的贱金属的上方的有机可焊保护剂。
8.根据权利要求1所述的半导体封装，其中所述电容器部分地凹进所述电容器开口内至少0.10毫米的深度。
9.根据权利要求1所述的半导体封装，进一步包括形成与所述封装电触点相对应的焊球阵列的多个焊料凸块，所述多个焊料凸块中的每一个在所述电触点开口内与所述封装电触点接触，
其中所述电容器的厚度至少为0.30毫米(mm)，
其中所述多个焊料凸块被配置为当所述半导体封装被安装到外部板时提供不大于0.40mm的塌陷厚度，并且
其中所述电容器部分地凹进所述电容器开口内，以当所述半导体封装被安装到所述外部板时提供与所述外部板的至少0.15mm的间隙距离。
10.根据权利要求1所述的半导体封装，其中所述半导体管芯通过倒装芯片连接被电连接至所述第一组电触点。
11.根据权利要求1所述的半导体封装，其中所述电容器是多层陶瓷贴片电容器。
12.根据权利要求11所述的半导体封装，其中所述多层陶瓷贴片电容器通过2010年6月1日修订版D的AEC-Q200应力测试认证。
13.一种半导体封装衬底，其包括：
介电层；
第一导电层，其在所述介电层的第一侧上形成第一组电触点；
第二导电层，其在所述介电层的第二侧上形成第二组电触点，所述第二组电触点包括封装电触点和两个电容器电触点；
导电通孔，其穿过所述介电层，电连接所述第一导电层与所述第二导电层；和
所述第二导电层的上方的阻焊层，所述阻焊层形成与所述封装电触点中的每一个相邻的电触点开口，并且在所述两个电容器电触点的上方形成电容器开口；
其中所述电容器开口具有圆角形状，其半径至少为所述阻焊层的厚度的50％。
14.根据权利要求13所述的半导体封装衬底，
其中所述电触点开口是阻焊层限定，并且
其中所述两个电容器电触点是非阻焊层限定。
15.一种形成半导体封装的方法，其包括：
将半导体管芯安装在多层衬底上，以将所述半导体管芯电连接到所述多层衬底的第一组电触点，
其中所述多层衬底包括：
介电层；
第一导电层，其在所述介电层的第一侧上形成所述第一组电触点；
第二导电层，其在所述介电层的第二侧上形成第二组电触点，所述第二组电触点包括封装电触点和两个电容器电触点；
导电通孔，其在所述第一导电层与所述第二导电层之间延伸穿过所述介电层；和
所述第二导电层的上方的阻焊层，所述阻焊层形成与所述封装电触点相邻的电触点开口，并且在所述两个电容器电触点的上方形成电容器开口；并且
将电容器安装在所述两个电容器电触点上以将所述电容器电连接到所述两个电容器电触点，其中所述电容器的凹进部分在所述两个电容器电触点与所述阻焊层的板侧表面之间的所述电容器开口内。
16.根据权利要求15所述的方法，其中将所述电容器安装在所述两个电容器电触点上包括在所述电容器的电容器端子与所述两个电容器电触点之间回流焊膏以形成直接焊料连接，其中所述电容器端子和所述两个电容器电触点仅通过所述直接焊料连接的毛细流分开。
17.根据权利要求15所述的方法，进一步包括：
在所述第二导电层的上方应用所述阻焊层；和
图案化所述阻焊层，以形成与所述封装电触点中的每个相邻的所述电触点开口，并且在所述两个电容器电触点的上方形成所述电容器开口，以使所述电触点开口是阻焊层限定，并且所述两个电容器电触点是非阻焊层限定。
18.根据权利要求17所述的方法，进一步包括在所述电触点开口内而不在所述电容器开口内应用预焊料。
19.根据权利要求15所述的方法，其中将所述半导体管芯安装在所述多层衬底上包括处理一组焊料凸块，以在所述半导体管芯与所述第一组电触点之间形成电连接。
20.根据权利要求15所述的方法，进一步包括将多个焊料凸块应用到所述电触点开口以形成焊球阵列。
CN202010173333.XA 2019-03-13 2020-03-13 具有部分凹进电容器的封装衬底 Pending CN111696950A (zh)

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Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH045844A (ja) 1990-04-23 1992-01-09 Nippon Mektron Ltd Ｉｃ搭載用多層回路基板及びその製造法
JP2842378B2 (ja) 1996-05-31 1999-01-06 日本電気株式会社 電子回路基板の高密度実装構造
US6272020B1 (en) 1997-10-16 2001-08-07 Hitachi, Ltd. Structure for mounting a semiconductor device and a capacitor device on a substrate
US6507119B2 (en) 2000-11-30 2003-01-14 Siliconware Precision Industries Co., Ltd. Direct-downset flip-chip package assembly and method of fabricating the same
US20020086561A1 (en) * 2000-12-12 2002-07-04 Ngk Spark Plug Co., Ltd. Wiring board
US7061102B2 (en) 2001-06-11 2006-06-13 Xilinx, Inc. High performance flipchip package that incorporates heat removal with minimal thermal mismatch
SG115456A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
SG115459A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Flip chip packaging using recessed interposer terminals
JP2003347741A (ja) 2002-05-30 2003-12-05 Taiyo Yuden Co Ltd 複合多層基板およびそれを用いたモジュール
JP4305808B2 (ja) 2002-07-03 2009-07-29 太陽誘電株式会社 積層コンデンサ
US20040022038A1 (en) 2002-07-31 2004-02-05 Intel Corporation Electronic package with back side, cavity mounted capacitors and method of fabrication therefor
US7084500B2 (en) 2003-10-29 2006-08-01 Texas Instruments Incorporated Semiconductor circuit with multiple contact sizes
JP4387231B2 (ja) * 2004-03-31 2009-12-16 新光電気工業株式会社 キャパシタ実装配線基板及びその製造方法
US6953893B1 (en) 2004-03-31 2005-10-11 Infineon Technologies Ag Circuit board for connecting an integrated circuit to a support and IC BGA package using same
US8264846B2 (en) 2006-12-14 2012-09-11 Intel Corporation Ceramic package substrate with recessed device
JP5284155B2 (ja) * 2008-03-24 2013-09-11 日本特殊陶業株式会社 部品内蔵配線基板
US8276269B2 (en) 2008-06-20 2012-10-02 Intel Corporation Dual epoxy dielectric and photosensitive solder mask coatings, and processes of making same
US20100073894A1 (en) * 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
JP2012156193A (ja) 2011-01-24 2012-08-16 Tdk Corp 積層コンデンサ
WO2013190718A1 (ja) 2012-06-19 2013-12-27 太陽誘電株式会社 積層セラミックコンデンサ
US9293426B2 (en) 2012-09-28 2016-03-22 Intel Corporation Land side and die side cavities to reduce package Z-height
US20140183744A1 (en) 2012-12-28 2014-07-03 Texas Instruments Incorporated Package substrate with bondable traces having different lead finishes
US10373884B2 (en) * 2016-03-31 2019-08-06 Samsung Electronics Co., Ltd. Fan-out semiconductor package for packaging semiconductor chip and capacitors
EP3639173A1 (en) * 2017-06-12 2020-04-22 Grail, Inc. Alignment free filtering for identifying fusions
US10396047B2 (en) * 2017-06-14 2019-08-27 Intel Corporation Semiconductor package with package components disposed on a package substrate within a footprint of a die
US11160163B2 (en) 2017-11-17 2021-10-26 Texas Instruments Incorporated Electronic substrate having differential coaxial vias
MY202351A (en) * 2018-04-04 2024-04-24 Intel Corp Composite stacked interconnects for high-speed applications and methods of assembling same
US10998247B2 (en) * 2018-08-16 2021-05-04 Samsung Electronics Co., Ltd. Board with embedded passive component
US11540395B2 (en) * 2018-10-17 2022-12-27 Intel Corporation Stacked-component placement in multiple-damascene printed wiring boards for semiconductor package substrates

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