MY202351A - Composite stacked interconnects for high-speed applications and methods of assembling same - Google Patents

Composite stacked interconnects for high-speed applications and methods of assembling same

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Publication number
MY202351A
MY202351A MYPI2018701348A MYPI2018701348A MY202351A MY 202351 A MY202351 A MY 202351A MY PI2018701348 A MYPI2018701348 A MY PI2018701348A MY PI2018701348 A MYPI2018701348 A MY PI2018701348A MY 202351 A MY202351 A MY 202351A
Authority
MY
Malaysia
Prior art keywords
methods
speed applications
assembling same
composite
composite stacked
Prior art date
Application number
MYPI2018701348A
Inventor
Bok Eng Cheah
Ping Ping Ooi
Shaw Fong Wong
Jackson Chung Peng Kong
Hungying Lo
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to MYPI2018701348A priority Critical patent/MY202351A/en
Priority to US16/280,850 priority patent/US20190311978A1/en
Publication of MY202351A publication Critical patent/MY202351A/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3494—Heating methods for reflowing of solder
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor package substrate (110, 210, 310, 410) includes a composite and stacked vertical interconnect on a land side (114, 214, 314, 414) of the substrate (110, 210, 310, 410). The composite and stacked vertical interconnect (120, 220, 320, 420) includes a smaller contact end against the semiconductor package substrate (110, 210, 310, 410), and a larger contact end for board (150, 250, 350, 550) mounting. (The most illustrative drawing is Figure 1A)
MYPI2018701348A 2018-04-04 2018-04-04 Composite stacked interconnects for high-speed applications and methods of assembling same MY202351A (en)

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JP7251951B2 (en) * 2018-11-13 2023-04-04 新光電気工業株式会社 Semiconductor device and method for manufacturing semiconductor device
US11289412B2 (en) 2019-03-13 2022-03-29 Texas Instruments Incorporated Package substrate with partially recessed capacitor
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
CN113056098B (en) * 2021-02-10 2022-09-23 华为数字能源技术有限公司 Electronic element packaging body, electronic element assembling structure and electronic equipment
KR20220140290A (en) * 2021-04-09 2022-10-18 삼성전자주식회사 Package device comprising a capacitor disposed on the opposite side of the die relative to the substrate
US20230014450A1 (en) * 2021-07-16 2023-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US11916004B2 (en) * 2021-09-03 2024-02-27 Advanced Semiconductor Engineering, Inc. Electronic device

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JP3752949B2 (en) * 2000-02-28 2006-03-08 日立化成工業株式会社 Wiring substrate and semiconductor device
US6610591B1 (en) * 2000-08-25 2003-08-26 Micron Technology, Inc. Methods of ball grid array
US9281292B2 (en) * 2012-06-25 2016-03-08 Intel Corporation Single layer low cost wafer level packaging for SFF SiP
US9293426B2 (en) * 2012-09-28 2016-03-22 Intel Corporation Land side and die side cavities to reduce package Z-height
US9129981B2 (en) * 2013-11-26 2015-09-08 Freescale Semiconductor Inc. Methods for the production of microelectronic packages having radiofrequency stand-off layers
KR20150094135A (en) * 2014-02-10 2015-08-19 삼성전자주식회사 Semiconductor package and manufacturing the same
DE102015100771B4 (en) * 2015-01-20 2022-05-05 Infineon Technologies Ag Chip carrier laminate with high-frequency dielectric and thermomechanical damper
TWI585904B (en) * 2016-04-22 2017-06-01 矽品精密工業股份有限公司 Electronic package and substrate structure
US10249561B2 (en) * 2016-04-28 2019-04-02 Ibiden Co., Ltd. Printed wiring board having embedded pads and method for manufacturing the same

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