JP5924953B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5924953B2 JP5924953B2 JP2012013422A JP2012013422A JP5924953B2 JP 5924953 B2 JP5924953 B2 JP 5924953B2 JP 2012013422 A JP2012013422 A JP 2012013422A JP 2012013422 A JP2012013422 A JP 2012013422A JP 5924953 B2 JP5924953 B2 JP 5924953B2
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- transistor
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- oxide semiconductor
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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Description
本実施の形態では、本発明の一態様であるトランジスタの構造および作製方法について、図1及び図2を用いて説明する。図1(A)はトランジスタ162のチャネル長方向の断面図の一例を示している。また、図1(B)はトランジスタ162とトランジスタ163の素子分離領域165の断面図の一例を示している。また、図1(C)はトランジスタ162とトランジスタ163の上面図の一例を示している。なお、図1(B)はトランジスタ162のチャネル幅方向の断面図の一部であり、図1(C)中の鎖線D1−D2で切断した断面に相当する。また、図1(A)は、図1(C)中の鎖線A1−A2で切断した断面に相当する。
図1に示すトランジスタ162を使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置の一例を図3に示す。
本実施の形態においては、図1に示すトランジスタ162を使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置について、実施の形態2に示した構成と異なる構成について図4を用いて説明を行う。
本実施の形態においては、図1に示すトランジスタ162を使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置について、実施の形態2、及び実施の形態3に示した構成と異なる構成について、図5、及び図6を用いて説明を行う。
本実施の形態では、先の実施の形態で説明した半導体装置を携帯電話、スマートフォン、電子書籍などの携帯機器に応用した場合の例を図10乃至図13を用いて説明する。
108 ゲート絶縁層
110 ゲート電極
116 チャネル形成領域
120 不純物領域
124 金属化合物領域
126 電極
130 絶縁層
142a、142b 電極
143a、143b 絶縁層
144 酸化物半導体層
146 ゲート絶縁層
148a、148b ゲート電極
149 絶縁層
150 絶縁層
151 絶縁層
152 絶縁層
153 電極
154 電極
156 配線
160 トランジスタ
161 素子分離領域
162 トランジスタ
163 トランジスタ
164 キャパシタ
165 素子分離領域
250 メモリセル
251 メモリセルアレイ
253 周辺回路
254 キャパシタ
310 半導体基板
312 STI領域
314 ゲート絶縁層
316 半導体層
318 導電層
320 保護絶縁層
322 サイドウォール絶縁層
324 不純物領域
325 接続電極
326 絶縁層
328 電極
329 絶縁層
330 接続電極
331 接続電極
332 電極
334 接続電極
336 電極
338 接続電極
350 トランジスタ
400 周辺回路
402 基板
403 素子分離絶縁層
404 チャネル形成領域
406 不純物領域
408 高濃度不純物領域
410 金属化合物領域
411 ゲート絶縁層
412 ゲート電極
414 サイドウォール絶縁層
418a ソース電極またはドレイン電極
418b ソース電極またはドレイン電極
420 層間絶縁層
422 層間絶縁層
424a 接続電極層
424b 接続電極層
424c 接続電極層
425 絶縁層
426 接続電極
428 電極
430 接続電極
450 トランジスタ
452 メモリセル
801 トランジスタ
803 トランジスタ
804 トランジスタ
805 トランジスタ
806 トランジスタ
807 Xデコーダー
808 Yデコーダー
811 トランジスタ
812 保持容量
813 Xデコーダー
814 Yデコーダー
901 RF回路
902 アナログベースバンド回路
903 デジタルベースバンド回路
904 バッテリー
905 電源回路
906 アプリケーションプロセッサ
907 CPU
908 DSP
909 インターフェイス
910 フラッシュメモリ
911 ディスプレイコントローラ
912 メモリ回路
913 ディスプレイ
914 表示部
915 ソースドライバ
916 ゲートドライバ
917 音声回路
918 キーボード
919 タッチセンサ
950 メモリ回路
951 メモリコントローラ
952 メモリ
953 メモリ
954 スイッチ
955 スイッチ
956 ディスプレイコントローラ
957 ディスプレイ
1001 バッテリー
1002 電源回路
1003 マイクロプロセッサ
1004 フラッシュメモリ
1005 音声回路
1006 キーボード
1007 メモリ回路
1008 タッチパネル
1009 ディスプレイ
1010 ディスプレイコントローラ
Claims (4)
- 第1の絶縁層と、第2の絶縁層と、トランジスタと、を有し、
前記第1の絶縁層は、第1のトレンチと、第2のトレンチと、を有し、
前記トランジスタは、
前記第1のトレンチの底面及び内壁面に接する領域を有する酸化物半導体層と、
前記酸化物半導体層上にゲート絶縁層と、
前記ゲート絶縁層上にゲート電極と、を有し、
前記ゲート絶縁層は、前記第2のトレンチの底面及び内壁面に接する領域を有し、
前記ゲート電極は、前記第1のトレンチ内を充填する領域を有し、
前記第2の絶縁層は、前記第2のトレンチ内を充填する領域を有することを特徴とする半導体装置。 - 請求項1において、
さらに前記酸化物半導体層に接するソース電極またはドレイン電極を有することを特徴とする半導体装置。 - 請求項1または請求項2において、
前記ゲート絶縁層は、前記酸化物半導体層の側面に接することを特徴とする半導体装置。 - 請求項1乃至3のいずれか一において、
前記酸化物半導体層は、断面形状がU字形状であり、
前記酸化物半導体層は、前記U字形状である酸化物半導体層の表面に対して概略垂直な方向にc軸を有している結晶を含むことを特徴とする半導体装置。
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JP (1) | JP5924953B2 (ja) |
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