JP5903281B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5903281B2 JP5903281B2 JP2012011677A JP2012011677A JP5903281B2 JP 5903281 B2 JP5903281 B2 JP 5903281B2 JP 2012011677 A JP2012011677 A JP 2012011677A JP 2012011677 A JP2012011677 A JP 2012011677A JP 5903281 B2 JP5903281 B2 JP 5903281B2
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- transistor
- insulating layer
- electrode
- oxide semiconductor
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
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- G—PHYSICS
- G11—INFORMATION STORAGE
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
Description
本実施の形態では、本発明の一態様であるトランジスタの構造および作製方法について、図1及び図2を用いて説明する。図1(A)はトランジスタ162のチャネル長方向の断面図の一例を示している。また、図1(B)はトランジスタ162とトランジスタ163の素子分離領域165に垂直な断面図の一例を示している。また、図1(C)はトランジスタ162とトランジスタ163の上面図の一例を示している。なお、図1(B)はトランジスタ162のチャネル幅方向の断面図の一部であり、図1(C)中の鎖線D1−D2で切断した断面に相当する。また、図1(A)は、図1(C)中の鎖線A1−A2で切断した断面に相当する。
(a―A)2+(b―B)2+(c―C)2≦r2
を満たすことをいい、rは、例えば、0.05とすればよい。他の酸化物でも同様である。
図1に示すトランジスタ162を使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置の一例を図3、及び図17に示す。
本実施の形態においては、図1に示すトランジスタ162を使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置について、実施の形態2に示した構成と異なる構成について図4を用いて説明を行う。
本実施の形態においては、図1に示すトランジスタ162を使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置について、実施の形態2、及び実施の形態3に示した構成と異なる構成について、図5、及び図6を用いて説明を行う。
本実施の形態では、先の実施の形態で説明した半導体装置を携帯電話、スマートフォン、電子書籍などの携帯機器に応用した場合の例を図10乃至図13を用いて説明する。
108 ゲート絶縁層
110 ゲート電極
116 チャネル形成領域
120 不純物領域
124 金属化合物領域
126 電極
130 絶縁層
142a 電極
142b 電極
143a 絶縁層
143b 絶縁層
144 酸化物半導体層
146 ゲート絶縁層
148a ゲート電極
148b ゲート電極
149 絶縁層
150 絶縁層
151 絶縁層
152 絶縁層
153 電極
154 電極
156 配線
160 トランジスタ
161 素子分離領域
162 トランジスタ
163 トランジスタ
164 容量素子
165 素子分離領域
250 メモリセル
251 メモリセルアレイ
252 メモリセルアレイ
253 周辺回路
254 容量素子
310 半導体基板
312 STI領域
314 ゲート絶縁層
316 半導体層
318 導電層
320 保護絶縁層
322 サイドウォール絶縁層
324 不純物領域
325 接続電極
326 絶縁層
328 電極
329 絶縁層
330 接続電極
331 接続電極
332 電極
334 接続電極
336 電極
338 接続電極
350 トランジスタ
400 周辺回路
402 基板
403 素子分離絶縁層
404 チャネル形成領域
406 不純物領域
408 高濃度不純物領域
410 金属化合物領域
411 ゲート絶縁層
412 ゲート電極層
414 サイドウォール絶縁層
418a ドレイン電極
418b ドレイン電極
420 層間絶縁層
422 層間絶縁層
424a 電極
424b 電極
424c 電極
425 絶縁層
426 接続電極
428 電極
430 接続電極
432 配線
434 接続電極
436 電極
438 接続電極
440 配線
450 トランジスタ
452a メモリセル
452b メモリセル
502 絶縁膜
504 電極
801 トランジスタ
803 トランジスタ
804 トランジスタ
805 トランジスタ
806 トランジスタ
807 Xデコーダー
808 Yデコーダー
811 トランジスタ
812 保持容量
813 Xデコーダー
814 Yデコーダー
901 RF回路
902 アナログベースバンド回路
903 デジタルベースバンド回路
904 バッテリー
905 電源回路
906 アプリケーションプロセッサ
907 CPU
908 DSP
909 インターフェイス
910 フラッシュメモリ
911 ディスプレイコントローラ
912 メモリ回路
913 ディスプレイ
914 表示部
915 ソースドライバ
916 ゲートドライバ
917 音声回路
918 キーボード
919 タッチセンサ
950 メモリ回路
951 メモリコントローラ
952 メモリ
953 メモリ
954 スイッチ
955 スイッチ
956 ディスプレイコントローラ
957 ディスプレイ
1001 バッテリー
1002 電源回路
1003 マイクロプロセッサ
1004 フラッシュメモリ
1005 音声回路
1006 キーボード
1007 メモリ回路
1008 タッチパネル
1009 ディスプレイ
1010 ディスプレイコントローラ
Claims (4)
- 第1のトランジスタを含む周辺回路と、
第2のトランジスタと容量素子とを有する記憶素子と、
を有し、
前記第1のトランジスタは、酸化物半導体以外の材料を有し、
前記容量素子は、前記第2のトランジスタのソース電極またはドレイン電極の一方と電気的に接続されており、
前記第2のトランジスタは、
第1の絶縁層に第1のトレンチと、
前記第1のトレンチの底面に接する第1の領域と、前記第1のトレンチの内壁面に接する第2の領域と、を有する酸化物半導体層と、
前記酸化物半導体層に接する領域を有するゲート絶縁層と、
前記ゲート絶縁層に接する領域を有するゲート電極と、
前記酸化物半導体層に接する領域を有する前記ソース電極または前記ドレイン電極と、
を有し、
前記周辺回路の上に、前記記憶素子が積層されており、
前記第1の領域は、第1の結晶を有し、
前記第2の領域は、第2の結晶を有し、
前記第1の結晶は、第1の方向に沿うように配向したc軸を有し、
前記第2の結晶は、前記第1の方向とは異なる第2の方向に沿うように配向したc軸を有し、
前記第1の方向は、前記第1のトレンチの底面に対して概略垂直な方向であり、
前記第2の方向は、前記第1のトレンチの内壁面に対して概略垂直な方向であることを特徴とする半導体装置。 - 第1のトランジスタを含む周辺回路と、
第2のトランジスタと容量素子とを有する記憶素子と、
を有し、
前記第1のトランジスタは、酸化物半導体以外の材料を有し、
前記容量素子は、前記第2のトランジスタのソース電極またはドレイン電極の一方と電気的に接続されており、
前記第2のトランジスタは、
第1の絶縁層に第1のトレンチと、
前記第1のトレンチの底面に接する第1の領域と、前記第1のトレンチの内壁面に接する第2の領域と、を有する酸化物半導体層と、
前記酸化物半導体層に接する領域を有するゲート絶縁層と、
前記ゲート絶縁層に接する領域を有するゲート電極と、
前記酸化物半導体層に接する領域を有する前記ソース電極または前記ドレイン電極と、
を有し、
前記周辺回路の上に、前記記憶素子が積層されており、
前記第1の領域は、第1の結晶を有し、
前記第2の領域は、第2の結晶を有し、
前記第1の結晶は、第1の方向に沿うように配向したc軸を有し、
前記第2の結晶は、前記第1の方向とは異なる第2の方向に沿うように配向したc軸を有し、
前記第1の方向は、前記第1の領域の前記酸化物半導体層の表面に対して概略垂直な方向であり、
前記第2の方向は、前記第2の領域の前記酸化物半導体層の表面に対して概略垂直な方向であることを特徴とする半導体装置。 - 請求項1または請求項2において、
前記第1の絶縁層に第2のトレンチを有し、
前記第2のトレンチの底面及び内壁面上に前記ゲート絶縁層を有し、
前記第2のトレンチ内を充填する第2の絶縁層を有することを特徴とする半導体装置。 - 請求項1乃至請求項3のいずれか一において、
前記酸化物半導体以外の材料は、シリコン、ゲルマニウム、シリコンゲルマニウム、炭化シリコン、またはガリウムヒ素を含むことを特徴とする半導体装置。
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