JP5720805B2 - 絶縁ゲート型半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 230000015556 catabolic process Effects 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 22
- 230000005684 electric field Effects 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 239000010410 layer Substances 0.000 description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
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Description
2 n-ドリフト層、第1導電型ドリフト層
3 pベース領域、第2導電型ベース領域
4 n+エミッタ領域、第1導電型エミッタ領域
5a ゲ−ト絶縁膜
5b 絶縁膜
6 ゲート電極
7 絶縁膜、層間絶縁膜
8 エミッタ電極
9 コレクタ電極
10 トレンチ
11 フローティングp型領域
20 フローティングp型領域
21 接合
30 フィールドストップ領域
40 p型ガードリング
50 リサーフ領域
60 フィールドプレート
100 素子活性部
200 耐圧構造部
Claims (5)
- 半導体基板からなる第1導電型ドリフト層と、
前記第1導電型ドリフト層の一方の主面に選択的に形成される第2導電型ベース領域と、
前記第2導電型ベース領域内の表面に選択的に形成される第1導電型エミッタ領域と、
前記第1導電型ドリフト層の他方の主面に形成される第2導電型半導体層と、
前記第1導電型エミッタ領域の表面から前記第2導電型ベース領域を超える深さと前記第1導電型エミッタ領域の長手方向に沿う平行ストライプ状平面パターンとを有する複数のトレンチと、
前記複数のトレンチ内にそれぞれ絶縁膜を介して充填されるゲート電極と、
を備え、
前記複数のトレンチ間に挟まれる複数の表面領域が、エミッタ電極に導電接触する第2導電型ベース領域と第1導電型エミッタ領域とともに、交互に配置される電気的に絶縁される第2導電型フローティング領域とを有し、
前記第2導電型フローティング領域は、深さが前記トレンチよりも深く、不純物濃度が前記第2導電型ベース領域よりも低く、
前記第2導電型フローティング領域内の、前記トレンチに接する部分全体に、前記第2導電型フローティング領域よりも不純物濃度の高いフィールドストップ領域を有することを特徴とする絶縁ゲート型半導体装置。 - 前記第2導電型フローティング領域が、オフ時の定格電圧印加により前記第2導電型フローティング領域の接合から伸びる空乏層が少なくとも前記第2導電型ベース領域の底部と同レベルの位置まで伸びることができる低い不純物濃度にされていることを特徴とする請求項1に記載の絶縁ゲート型半導体装置。
- 前記絶縁ゲート型半導体装置がトレンチゲート型IGBTであることを特徴とする請求項1または2に記載の絶縁ゲート型半導体装置。
- 半導体基板からなる第1導電型ドリフト層と、前記第1導電型ドリフト層の一方の主面に選択的に形成される第2導電型ベース領域と、前記第2導電型ベース領域内の表面に選択的に形成される第1導電型エミッタ領域と、前記第1導電型ドリフト層の他方の主面に形成される第2導電型半導体層と、前記第1導電型エミッタ領域の表面から前記第2導電型ベース領域を超える深さと前記第1導電型エミッタ領域の長手方向に沿う平行ストライプ状平面パターンとを有する複数のトレンチと、前記複数のトレンチ内にそれぞれ絶縁膜を介して充填されるゲート電極と、を備え、前記複数のトレンチ間に挟まれる複数の表面領域が、エミッタ電極に導電接触する第2導電型ベース領域と第1導電型エミッタ領域とともに、交互に配置される電気的に絶縁される第2導電型フローティング領域とを有し、前記第2導電型フローティング領域の深さが前記トレンチよりも深く、不純物濃度が前記第2導電型ベース領域よりも低く、前記第2導電型フローティング領域内の、前記トレンチに接する部分全体に、前記第2導電型フローティング領域よりも不純物濃度の高いフィールドストップ領域を有する絶縁ゲート型半導体装置の製造方法であって、
前記第2導電型フローティング領域が、該領域の最外周を取り巻く耐圧構造領域に電界緩和のために設けられるガードリングと同時に形成されることを特徴とする絶縁ゲート型半導体装置の製造方法。 - 半導体基板からなる第1導電型ドリフト層と、前記第1導電型ドリフト層の一方の主面に選択的に形成される第2導電型ベース領域と、前記第2導電型ベース領域内の表面に選択的に形成される第1導電型エミッタ領域と、前記第1導電型ドリフト層の他方の主面に形成される第2導電型半導体層と、前記第1導電型エミッタ領域の表面から前記第2導電型ベース領域を超える深さと前記第1導電型エミッタ領域の長手方向に沿う平行ストライプ状平面パターンとを有する複数のトレンチと、前記複数のトレンチ内にそれぞれ絶縁膜を介して充填されるゲート電極と、を備え、前記複数のトレンチ間に挟まれる複数の表面領域が、エミッタ電極に導電接触する第2導電型ベース領域と第1導電型エミッタ領域とともに、交互に配置される電気的に絶縁される第2導電型フローティング領域とを有し、前記第2導電型フローティング領域の深さが前記トレンチよりも深く、不純物濃度が前記第2導電型ベース領域よりも低く、前記第2導電型フローティング領域内の、前記トレンチに接する部分全体に、前記第2導電型フローティング領域よりも不純物濃度の高いフィールドストップ領域を有する絶縁ゲート型半導体装置の製造方法であって、
前記第2導電型フローティング領域が、該領域の最外周を取り巻く耐圧構造領域に電界緩和のために設けられる第2導電型リサーフ領域と同時に形成されることを特徴とする絶縁ゲート型半導体装置の製造方法。
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KR20150011185A (ko) * | 2013-07-22 | 2015-01-30 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
WO2015141327A1 (ja) * | 2014-03-19 | 2015-09-24 | 富士電機株式会社 | 半導体装置 |
JP6420175B2 (ja) * | 2014-05-22 | 2018-11-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6479533B2 (ja) * | 2015-03-31 | 2019-03-06 | ラピスセミコンダクタ株式会社 | 半導体装置および半導体装置の製造方法 |
JP6624973B2 (ja) * | 2016-03-03 | 2019-12-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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