JP5654206B2 - Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置 - Google Patents

Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置 Download PDF

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Publication number
JP5654206B2
JP5654206B2 JP2009069537A JP2009069537A JP5654206B2 JP 5654206 B2 JP5654206 B2 JP 5654206B2 JP 2009069537 A JP2009069537 A JP 2009069537A JP 2009069537 A JP2009069537 A JP 2009069537A JP 5654206 B2 JP5654206 B2 JP 5654206B2
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single crystal
crystal semiconductor
semiconductor layer
substrate
layer
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Japanese (ja)
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JP2009260314A5 (OSRAM
JP2009260314A (ja
Inventor
山崎　舜平
舜平 山崎
恵里子 西田
恵里子 西田
貴志 島津
貴志 島津
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Recrystallisation Techniques (AREA)
JP2009069537A 2008-03-26 2009-03-23 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置 Expired - Fee Related JP5654206B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009069537A JP5654206B2 (ja) 2008-03-26 2009-03-23 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008079592 2008-03-26
JP2008079592 2008-03-26
JP2009069537A JP5654206B2 (ja) 2008-03-26 2009-03-23 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置

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JP2009260314A JP2009260314A (ja) 2009-11-05
JP2009260314A5 JP2009260314A5 (OSRAM) 2012-04-19
JP5654206B2 true JP5654206B2 (ja) 2015-01-14

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US (1) US8530332B2 (OSRAM)
JP (1) JP5654206B2 (OSRAM)

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JP5755931B2 (ja) 2010-04-28 2015-07-29 株式会社半導体エネルギー研究所 半導体膜の作製方法、電極の作製方法、２次電池の作製方法、および太陽電池の作製方法
JP5565128B2 (ja) * 2010-06-17 2014-08-06 信越半導体株式会社 貼り合わせウエーハの製造方法
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JP6056516B2 (ja) * 2013-02-01 2017-01-11 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
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KR102737609B1 (ko) * 2018-07-19 2024-12-03 도쿄엘렉트론가부시키가이샤 기판 처리 시스템 및 기판 처리 방법
US11643724B2 (en) * 2019-07-18 2023-05-09 Asm Ip Holding B.V. Method of forming structures using a neutral beam
CN114005753B (zh) * 2021-10-29 2023-07-11 西安微电子技术研究所 一种igbt产品的氧化工艺方法及氧化后igbt产品

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JP2009260314A (ja) 2009-11-05
US8530332B2 (en) 2013-09-10
US20090261449A1 (en) 2009-10-22

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