JP5524547B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

Info

Publication number
JP5524547B2
JP5524547B2 JP2009211300A JP2009211300A JP5524547B2 JP 5524547 B2 JP5524547 B2 JP 5524547B2 JP 2009211300 A JP2009211300 A JP 2009211300A JP 2009211300 A JP2009211300 A JP 2009211300A JP 5524547 B2 JP5524547 B2 JP 5524547B2
Authority
JP
Japan
Prior art keywords
diffusion layer
type
transistor
layer
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009211300A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011061110A5 (enExample
JP2011061110A (ja
Inventor
富士雄 舛岡
紳太郎 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisantis Electronics Singapore Pte Ltd
Original Assignee
Unisantis Electronics Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisantis Electronics Singapore Pte Ltd filed Critical Unisantis Electronics Singapore Pte Ltd
Priority to JP2009211300A priority Critical patent/JP5524547B2/ja
Priority to TW099130837A priority patent/TW201110327A/zh
Priority to CN2010102843051A priority patent/CN102024815B/zh
Priority to EP10009572.8A priority patent/EP2296176B1/en
Priority to KR1020100089932A priority patent/KR101160105B1/ko
Priority to US12/881,554 priority patent/US8169030B2/en
Publication of JP2011061110A publication Critical patent/JP2011061110A/ja
Publication of JP2011061110A5 publication Critical patent/JP2011061110A5/ja
Application granted granted Critical
Publication of JP5524547B2 publication Critical patent/JP5524547B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0195—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
JP2009211300A 2009-09-14 2009-09-14 半導体記憶装置 Expired - Fee Related JP5524547B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2009211300A JP5524547B2 (ja) 2009-09-14 2009-09-14 半導体記憶装置
TW099130837A TW201110327A (en) 2009-09-14 2010-09-13 Semiconductor memory device and production method thereof
EP10009572.8A EP2296176B1 (en) 2009-09-14 2010-09-14 SRAM cell with four SGTs and manufacturing method thereof
KR1020100089932A KR101160105B1 (ko) 2009-09-14 2010-09-14 반도체 기억 장치 및 그 제조 방법
CN2010102843051A CN102024815B (zh) 2009-09-14 2010-09-14 半导体存储器件及其制造方法
US12/881,554 US8169030B2 (en) 2009-09-14 2010-09-14 Semiconductor memory device and production method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009211300A JP5524547B2 (ja) 2009-09-14 2009-09-14 半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2011061110A JP2011061110A (ja) 2011-03-24
JP2011061110A5 JP2011061110A5 (enExample) 2011-08-11
JP5524547B2 true JP5524547B2 (ja) 2014-06-18

Family

ID=43034204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009211300A Expired - Fee Related JP5524547B2 (ja) 2009-09-14 2009-09-14 半導体記憶装置

Country Status (6)

Country Link
US (1) US8169030B2 (enExample)
EP (1) EP2296176B1 (enExample)
JP (1) JP5524547B2 (enExample)
KR (1) KR101160105B1 (enExample)
CN (1) CN102024815B (enExample)
TW (1) TW201110327A (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013016243A (ja) * 2011-06-09 2013-01-24 Semiconductor Energy Lab Co Ltd 記憶装置
US8755219B2 (en) 2012-02-15 2014-06-17 Unisantis Electronics Singapore Pte. Ltd. Hierarchical wordline loadless 4GST-SRAM with a small cell area
CN103370781A (zh) * 2012-02-15 2013-10-23 新加坡优尼山帝斯电子私人有限公司 半导体存储器件
CN103460373A (zh) * 2012-02-15 2013-12-18 新加坡优尼山帝斯电子私人有限公司 半导体存储器件
US8836051B2 (en) * 2012-06-08 2014-09-16 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
KR101925012B1 (ko) * 2012-07-17 2018-12-05 에스케이하이닉스 주식회사 반도체 장치 및 그의 제조 방법
US9082838B2 (en) * 2012-09-28 2015-07-14 Unisantis Electronics Singapore Pte. Ltd. Method for producing a semiconductor device and semiconductor device
US8969949B2 (en) * 2013-03-10 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for static random access memory device of vertical tunneling field effect transistor
WO2015008387A1 (ja) * 2013-07-19 2015-01-22 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
JP2015032651A (ja) * 2013-08-01 2015-02-16 マイクロン テクノロジー， インク． 半導体装置
WO2015019444A1 (ja) * 2013-08-07 2015-02-12 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
US10361270B2 (en) * 2013-11-20 2019-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Nanowire MOSFET with different silicides on source and drain
JP5832057B1 (ja) 2014-02-24 2015-12-16 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 記憶装置、半導体装置、及び記憶装置、半導体装置の製造方法
WO2015129021A1 (ja) * 2014-02-28 2015-09-03 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置、及び半導体装置の製造方法
JP6114425B2 (ja) * 2016-03-11 2017-04-12 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
EP3507802A4 (en) * 2016-08-31 2020-04-08 Micron Technology, Inc. DETECTION AMPLIFIER STRUCTURES
EP3507831B1 (en) 2016-08-31 2021-03-03 Micron Technology, Inc. Memory arrays
US11211384B2 (en) 2017-01-12 2021-12-28 Micron Technology, Inc. Memory cells, arrays of two transistor-one capacitor memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry
US10290639B2 (en) * 2017-09-12 2019-05-14 Globalfoundries Inc. VNW SRAM with trinity cross-couple PD/PU contact and method for producing the same
US10559572B2 (en) 2018-06-29 2020-02-11 International Business Machines Corporation Vertical transistor contact for a memory cell with increased density
US10566453B2 (en) 2018-06-29 2020-02-18 International Business Machines Corporation Vertical transistor contact for cross-coupling in a memory cell
CN109326650B (zh) * 2018-10-10 2022-04-19 中国科学院微电子研究所 半导体器件及其制造方法及包括该器件的电子设备
US11640987B2 (en) * 2021-02-04 2023-05-02 Applied Materials, Inc. Implant to form vertical FETs with self-aligned drain spacer and junction
WO2022239196A1 (ja) * 2021-05-13 2022-11-17 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60128654A (ja) 1983-12-16 1985-07-09 Hitachi Ltd 半導体集積回路
JPS63239973A (ja) * 1986-10-08 1988-10-05 テキサス　インスツルメンツ　インコーポレイテツド 集積回路およびその製造方法
JP2703970B2 (ja) 1989-01-17 1998-01-26 株式会社東芝 Ｍｏｓ型半導体装置
KR0121992B1 (ko) 1993-03-03 1997-11-12 모리시다 요이치 반도체장치 및 그 제조방법
JP3403231B2 (ja) * 1993-05-12 2003-05-06 三菱電機株式会社 半導体装置およびその製造方法
JP3036588B2 (ja) * 1997-02-03 2000-04-24 日本電気株式会社 半導体記憶装置
JP3467416B2 (ja) 1998-04-20 2003-11-17 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及びその製造方法
US6229161B1 (en) * 1998-06-05 2001-05-08 Stanford University Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches
JP2001210727A (ja) * 1999-12-23 2001-08-03 Texas Instr Inc <Ti> メモリ・デバイス
US6583452B1 (en) * 2001-12-17 2003-06-24 T-Ram, Inc. Thyristor-based device having extended capacitive coupling
WO2003082954A1 (en) * 2002-03-28 2003-10-09 Communications Research Laboratory, Independent Administrative Institution Process for production of molecular devices
US7138685B2 (en) 2002-12-11 2006-11-21 International Business Machines Corporation Vertical MOSFET SRAM cell
JP2005303111A (ja) * 2004-04-14 2005-10-27 Renesas Technology Corp 半導体記憶装置
JP5114968B2 (ja) * 2007-02-20 2013-01-09 富士通セミコンダクター株式会社 半導体装置及びその製造方法
WO2009095999A1 (ja) * 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体記憶装置
US8288795B2 (en) * 2010-03-02 2012-10-16 Micron Technology, Inc. Thyristor based memory cells, devices and systems including the same and methods for forming the same

Also Published As

Publication number Publication date
KR101160105B1 (ko) 2012-06-26
US8169030B2 (en) 2012-05-01
US20110062523A1 (en) 2011-03-17
CN102024815B (zh) 2013-04-10
TW201110327A (en) 2011-03-16
KR20110029101A (ko) 2011-03-22
JP2011061110A (ja) 2011-03-24
CN102024815A (zh) 2011-04-20
EP2296176B1 (en) 2014-08-20
EP2296176A1 (en) 2011-03-16

Similar Documents

Publication Publication Date Title
JP5524547B2 (ja) 半導体記憶装置
KR101147582B1 (ko) 반도체 기억 장치와 그 제조방법
CN101933137B (zh) 半导体存储器件
JP4756221B2 (ja) 半導体記憶装置
CN101933136B (zh) 半导体存储器件
JP2011066109A (ja) 半導体記憶装置
WO2009096467A1 (ja) 半導体記憶装置
KR20130116334A (ko) 반도체 기억 장치
JP2014099664A (ja) 半導体記憶装置
WO2013121537A1 (ja) 半導体記憶装置
JP5489272B2 (ja) 半導体記憶装置
JPWO2013121537A1 (ja) 半導体記憶装置
JP5566697B2 (ja) 半導体記憶装置
JPWO2013121536A1 (ja) 半導体記憶装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110623

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110916

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20110927

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20110921

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130628

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130703

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131002

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140115

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140314

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140402

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140410

R150 Certificate of patent or registration of utility model

Ref document number: 5524547

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees