JP5497985B2 - 半導体パッケージ - Google Patents

半導体パッケージ Download PDF

Info

Publication number
JP5497985B2
JP5497985B2 JP2007531463A JP2007531463A JP5497985B2 JP 5497985 B2 JP5497985 B2 JP 5497985B2 JP 2007531463 A JP2007531463 A JP 2007531463A JP 2007531463 A JP2007531463 A JP 2007531463A JP 5497985 B2 JP5497985 B2 JP 5497985B2
Authority
JP
Japan
Prior art keywords
semiconductor package
package according
electrode
conductive
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007531463A
Other languages
English (en)
Other versions
JP2008512876A (ja
Inventor
スタンディング マーティン
ジェイ クラーク ロバート
Original Assignee
インターナショナル レクティフィアー コーポレイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by インターナショナル レクティフィアー コーポレイション filed Critical インターナショナル レクティフィアー コーポレイション
Publication of JP2008512876A publication Critical patent/JP2008512876A/ja
Application granted granted Critical
Publication of JP5497985B2 publication Critical patent/JP5497985B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/296—Organo-silicon compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/2969—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81054—Composition of the atmosphere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8122—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/81224—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0715—Polysiloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/186—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30101—Resistance

Description

本願は、米国特許仮出願第６０／６０９，５９７号（２００４年９月１３日出願，発明の名称：「次世代高性能パワーデバイス用微細接続パッケージ」）に基づくものであって、右出願の開示内容を組み入れており、かつ同出願による優先権を主張するものである。
本発明は、半導体パッケージ、およびこのパッケージの製造方法に関する。
半導体ダイ（半導体回路）の最新世代は、小型で、かつハイパワーである。したがって、このような半導体ダイ用の半導体パッケージは、小型にすることができ、新世代パワー半導体デバイスに低抵抗で接続できるものであり、かつエンドユーザが使いやすいピン配列と外部端子を有するものでなければならない。
本発明は、上記事情に鑑みてなされてもので、小型の半導体ダイに対応して小型にすることができ、かつユーザが使いやすいピン配列と外部端子を有する半導体パッケージを提供することを目的としている。
本発明に係る半導体パッケージは、第１の電極、第２の電極、前記第１の電極と電気的かつ機械的に接続された第１の導電性クリップ、および前記第２の電極と電気的かつ機械的に接続された第２の導電性クリップを有する半導体ダイを備えている。
本発明の一様相においては、半導体ダイを被覆するのに、不動態被膜を用いる。不動態被膜は、第１および第２の導電性クリップの少なくとも一部をも被覆するのが好ましい。不動態被膜とは、成形用化合物等からなるハウジングを用いることなく、半導体ダイを保護しうる誘電体ポリマーの薄膜である。この不動態被膜に適する材料は、ポリシロキサン系のポリマーである。
本発明のもう一つの様相においては、各電極は、対応する導電性クリップのフィンガー部（指のような形状の部分）に電気的および機械的に接続される複数のフィンガー部を有している。
本発明に係る半導体パッケージは、ＩｎＡｌＧａＮ系合金（例えばＧａＮやＡｌＧａＮ）等の３価の窒化物系パワー半導体デバイスに最も適している。このようなパワー半導体デバイスは、非常に小型で、しかも低抵抗接続が要求されるハイパワー機能を有するからである。また、本発明の半導体パッケージは、公知の技術によっては、外部の要素と接続することができない小型のシリコンベースのデバイスにも同様に適用しうる。
本発明の上記以外の特徴および効果は、添付の図面を参照して行う、以下の説明から明らかになると思う。
図１に示すように、本発明に係るパッケージに用いる半導体ダイ10は、半導体本体９、第１の電極（ソース電極またはドレイン電極）12、および第２の電極（ドレイン電極またはソース電極）14を備えている。両電極12,14は、半導体本体９の同一の面に設けられている。また、各電極12,14は、それぞれ、互いに入り込むようなパターンで延びるフィンガー部16,18を有している。フィンガー部16,18は、それぞれ、共用給電部20,22に電気的に接続されている。
半導体ダイ10は、第１の制御電極（第１のゲート電極）24、第２の制御電極（第２のゲート電極）26、第１の電流検知電極28、および第２の電流検知電極29を備える双方向のパワーデバイスである。米国特許出願第１１／０５６，０６２号は、双方向パワー半導体デバイスの一例を記載している。
半導体ダイ10は、ＩｎＡｌＧａＮ系合金（例えばＧａＮやＡｌＧａＮ）から形成された３価の窒化物系パワー半導体デバイスである。半導体ダイ10は、例えば、３価の窒化物系ショットキーデバイス、または金属絶縁体半導体ヘテロジャンクション電界効果トランジスタ（ＭＩＳＨＦＥＴ）や金属酸化物半導体ヘテロジャンクション電界効果トランジスタ（ＭＯＳＨＦＥＴ）のような高電子モビリティートランジスタ（ＨＥＭＴ）その他の３価の窒化物系ヘテロジャンクション電界効果トランジスタ（ＨＦＥＴ）とすることができる。
半導体ダイ10の大きさは、概ね、１．８mm×３．６mmである。半導体ダイ10は、電流検知機能を有する双方向のスイッチングデバイスとするのが好ましい。
半導体ダイの性能を高めるには、半導体ダイの電極を、体積の大きな外部要素に接続する必要がある。さもないと、広がり抵抗が蓄積されるからである。
また、半導体ダイが小型の場合には、電極の幅が狭いため、公知の表面実装技術によっては、ユーザが直接接触することはできない。したがって、パッケージ化する際には、エンドユーザが、公知の製造環境において取り扱えるように、電極の大きさと配置を変えなければならない。
パワー半導体デバイスにおいては、性能がかなり損なわれることを甘受して、電極の幅を０．８mm以下としても、回路基板の導電性パッドに直接接続するのは困難である。さらに、一辺が３．６mm以下の半導体ダイにおいては、電極の幅を０．８mmに縮小した場合でも、４個を超える電極を設けることは不可能である。
本発明に係る半導体パッケージは、幅が約０．８mm以下の電極を有する半導体ダイに適している。本発明に係る半導体パッケージは、微細形状のクリップボンディング技術を用いることによって、電極の配置に拘らず、小型の半導体ダイへの接続を可能とする。導電性クリップは、比較的薄く形成し（０．１００mm以下のオーダー）、かつ半導体の保護および半田との濡れ性改善のために、銅めっきを施すのが好ましい。
図２に示すように、本発明に係る半導体パッケージ30は、半導体本体９、第１の電極12と電気的および機械的に連結された第１の導電性クリップ32、および第２の電極14と電気的および機械的に連結された第２の導電性クリップ34を備えている。
第１の導電性クリップ32のフィンガー部33は、第１の電極12のフィンガー部16と電気的および機械的に連結されている。また、第２の導電性クリップ34のフィンガー部35は、第２の電極14のフィンガー部18と電気的および機械的に連結されている。フィンガー部33,35は、それぞれ、外部リードとして働く第１および第２の共用コネクタ31,37と接続されている。
また、半導体パッケージ30は、第１の制御電極24と電気的および機械的に接続された第１の導電性クリップ36、第２の制御電極26と電気的および機械的に接続された第２の導電性クリップ38、第１の電流検知電極28と電気的および機械的に接続された第１の電流検知導電性クリップ40、ならびに第２の電流検知電極29と電気的および機械的に接続された第２の電流検知導電性クリップ42を備えている。
図３〜図６に示すように、半導体パッケージ30は、少なくとも半導体ダイ10を被覆する不動態被膜44によって保護されている。導電性クリップ32,34,36,38,40,42も、外部の要素（例えば回路基板の導電性パッド）との接続に必要な部分を除いて、不動態被膜44によって保護されている。不動態被膜44は、半導体ダイ10を保護することのできる材料から形成されている。このため、半導体パッケージ30は、成形用化合物その他の材料から形成されるハウジングを必要としない。
導電性クリップ32,34,36,38,40,42は、半導体パッケージ30用の外部コネクタまたは外部リードとして働くことに留意するべきである。各導電性クリップ32,34,36,38,40,42は、外部の要素（例えば回路基板の導電性パッド）との接続に用いる部分を有している。図２〜図６に示すように、導電性クリップ32,34,36,38,40,42における外部接続用の部分は、半導体ダイ10の外縁を超えて延出しており、この部分の表面（外部接続面）46は、拡張されている。外部接続面４６は、他の部分の外部接続面と共面をなすようにするのが好ましい。
したがって、表面実装が不可能な小型の半導体ダイでも、回路基板の導電性パッドと接続しうるようになる。外部接続面46は、半導体ダイ10から離間して設けるのが好ましい。他の回路要素を接続した後に、接続のために流し込んだ材料の残留物を除去したり、回路基板の導電性パッドと外部接続面46との接続を検査したりできるからである。
導電性クリップ32,34,36,38,40,42は、半田や導電性エポキシ樹脂等の導電性の接着剤48を介して、半導体ダイ10の各電極と電気的および機械的に接続されている。この外、導電性クリップ32,34,36,38,40,42は、冷間圧接によって、半導体ダイ10の各電極と直接接続させることもできる。
導電性クリップ32,34,36,38,40,42は、金属製のクリップを微細加工する技術を用いて、リードフレームの一部とすることもできる。この場合には、まず導電性クリップをスタンプ加工し、ついで、大きな部分をパンチング等によって除去する。この後、レーザ切削、レーザ研磨、エッチング等によって微細加工を施す。なお、パンチングをレーザ切削、レーザ研磨、エッチング等と置き換えることもできる。
リードフレームを形成した後は、半田付けしうるように、銅や、無電解ニッケルに浸漬した金（ＥＮｉＧ）によって、めっきを施すのが好ましい。
リードフレームの一部としての導電性クリップ32,34,36,38,40,42を、適当な電極に電気的および機械的に接続する際には、導電性の接着剤を、半導体ダイ10の電極、またはリードフレームに蒸着する。すなわち、半田のような導電性接着剤を、ペースト状にして、半導体ダイ10の電極、またはリードフレームに蒸着する。この際、リードフレームは、半田付けの前に、溶融した半田に浸漬することもできる。本発明の半導体パッケージに好適な半田は、金（８０重量％）と錫（２０重量％）からなる半田である。
半導体ダイとリードフレームは、どのような方法で互いに半田付けしたとしても、その後、半田の再流動工程にかけて、導電性クリップ32,34,36,38,40,42を適当な電極に接続する。半田の再流動工程は、適当な環境（減圧酸素、真空、フォーミングガス（水素と窒素の混合ガス）等）の下において、レーザによる半田付け技術を用いて行う。
半導体ダイとリードフレームを互いに半田付けした後は、必要に応じて、洗浄工程にかけ、ついで、半導体ダイとリードフレームの組立て体を不動態被膜で被覆する。半導体ダイとリードフレームの組立て体を不動態被膜で覆うには、ポリシロキサン系ポリマー等の適当な不動態被膜の材料に浸漬し、その後、必要に応じて、不動態被膜を硬化させる。
ついで、リードフレームから、各導電性クリップを切り出すことによって、本発明に係る半導体パッケージが得られる。レーザ切削、レーザ研磨、エッチング等は、微細加工が可能であるため、導電性クリップの切り出しに適している。
本発明に係る半導体パッケージは、工程数が多いため複雑な面もあるが、複数の工程にわたって、同じレーザ装置を使用しうるため、必ずしもコスト高にはならない。なお、レーザを用いると、材料を１分当たり１０ｍ以上の速度で切削することができるため、製造を迅速に行うことができる。
以上、本発明を特定の実施形態に即して説明してきたが、当業者であれば、他の変形例も容易に想起しうると思われる。本発明の技術的範囲は、本明細書による開示に限定されるものではなく、特許請求の範囲の記載のみによって画定されるべきである。
本発明の一実施形態に係る半導体パッケージにおける半導体ダイの平面図である。 図１の半導体ダイに用いられる半導体パッケージの底面図である。 図２の３−３方向から視た側面図である。 図２の４−４方向から視た側面図である。 図２の５−５線に沿う断面図である。 図２の６−６線に沿う断面図である。
符号の説明
９ 半導体本体
10 半導体ダイ
12 第１の電極
14 第２の電極
16,18 フィンガー部
20,22 共用給電部
24 第１の制御電極
26 第２の制御電極
28 第１の電流検知電極
29 第２の電流検知電極
30 半導体パッケージ
32 第１の導電性クリップ
34 第２の導電性クリップ
33 フィンガー部
35 フィンガー部
31,37 共用コネクタ
36 第１の導電性クリップ
38 第２の導電性クリップ
40 第１の電流検知導電性クリップ
42 第２の電流検知導電性クリップ
44 不動態被膜
46 外部接続面
48 接着剤

Claims (28)

  1. ソース電極およびドレイン電極を同一面上に有する半導体ダイと、
    第１の共用コネクタに接続された第１の複数のフィンガー部を有する第１の導電性クリップであって、前記第１の共用コネクタは、前記半導体ダイの同一面上で前記ソース電極と電気的および機械的に接続され、前記半導体ダイの外縁を超えて外側に延出するフランジを構成する、該第１の導電性クリップと、
    第２の共用コネクタに接続された第２の複数のフィンガー部を有し、前記ドレイン電極と電気的および機械的に接続された第２の導電性クリップと、
    前記半導体ダイを包み込む不動態被膜であって、他のハウジング要素無しに前記半導体ダイを保護可能な不動態材料から形成される該不動態被膜と
    を備える半導体パッケージ。
  2. 前記半導体ダイは、３価の窒化物系半導体から形成されていることを特徴とする請求項１記載の半導体パッケージ。
  3. 前記３価の窒化物系半導体は、ＩｎＡｌＧａＮ系合金であることを特徴とする請求項２記載の半導体パッケージ。
  4. 前記ソース電極および前記ドレイン電極は、フィンガー部を有することを特徴とする請求項１記載の半導体パッケージ。
  5. 前記各電極のフィンガー部は、互いに間に入り込むように配置されていることを特徴とする請求項４記載の半導体パッケージ。
  6. 制御電極と、この制御電極と電気的および機械的に接続された導電性クリップとをさらに備えることを特徴とする請求項１記載の半導体パッケージ。
  7. 電流検知電極と、この電流検知電極と電気的および機械的に接続された電流検知クリップとをさらに備えることを特徴とする請求項６記載の半導体パッケージ。
  8. 前記半導体ダイは、第１の制御電極、この第１の制御電極と電気的および機械的に接続された第１の導電性制御クリップ、第２の制御電極、ならびにこの第２の制御電極と電気的および機械的に接続された第２の導電性制御クリップを備えることを特徴とする請求項１記載の半導体パッケージ。
  9. 電流検知電極と、この電流検知電極と電気的および機械的に接続された第１の電流検知導電性クリップとをさらに備えていることを特徴とする請求項８記載の半導体パッケージ。
  10. 前記第１および第２の導電性クリップは、導電性の接着剤を介して、それぞれ、前記ソース電極および前記ドレイン電極と電気的および機械的に接続されていることを特徴とする請求項１記載の半導体パッケージ。
  11. 前記導電性の接着剤は、金とスズの合金からなることを特徴とする請求項１０記載の半導体パッケージ。
  12. 前記導電性の接着剤は、半田または導電性のポリマーからなることを特徴とする請求項１０記載の半導体パッケージ。
  13. 前記不動態被膜は、ポリマーからなることを特徴とする請求項１記載の半導体パッケージ。
  14. 前記ポリマーは、ポリシロキサンであることを特徴とする請求項１３記載の半導体パッケージ。
  15. それぞれフィンガー部を含むソース電極およびドレイン電極を同一面上に有する半導体ダイと、
    第１の共用コネクタを有する第１の導電性クリップであって、前記第１の共用コネクタは前記半導体ダイの前記同一面上で前記ソース電極と電気的および機械的に接続され、前記半導体ダイの外縁を超えて外側に延出するフランジを構成する、該第１の導電性クリップと、
    前記ドレイン電極と電気的および機械的に接続された第２の導電性クリップと、
    を備える半導体パッケージ。
  16. 前記半導体ダイを包み込む不動態被膜をさらに備えていることを特徴とする請求項１５記載の半導体パッケージ。
  17. 前記半導体ダイは、３価の窒化物系半導体から形成されていることを特徴とする請求項１５記載の半導体パッケージ。
  18. 前記３価の窒化物系半導体は、ＩｎＡｌＧａＮ系合金であることを特徴とする請求項１７記載の半導体パッケージ。
  19. 前記各電極のフィンガー部は、互いに間に入り込むように配置されていることを特徴とする請求項１５記載の半導体パッケージ。
  20. 制御電極と、この制御電極と電気的および機械的に接続された導電性クリップとをさらに備えていることを特徴とする請求項１５記載の半導体パッケージ。
  21. 電流検知電極と、この電流検知電極と電気的および機械的に接続された電流検知クリップとをさらに備えていることを特徴とする請求項２０記載の半導体パッケージ。
  22. 前記半導体ダイは、第１の制御電極、この第１の制御電極と電気的および機械的に接続された第１の導電性制御クリップ、第２の制御電極、ならびにこの第２の制御電極と電気的および機械的に接続された第２の導電性制御クリップを備えていることを特徴とする請求項１５記載の半導体パッケージ。
  23. 電流検知電極と、この電流検知電極と電気的および機械的に接続された電流検知クリップとをさらに備えていることを特徴とする請求項２２記載の半導体パッケージ。
  24. 前記第１および第２の導電性クリップは、導電性の接着剤を介して、それぞれ、前記ソース電極および前記ドレイン電極と電気的および機械的に接続されていることを特徴とする請求項１５記載の半導体パッケージ。
  25. 前記導電性の接着剤は、半田または導電性のポリマーからなることを特徴とする請求項２４記載の半導体パッケージ。
  26. 前記導電性の接着剤は、金とスズの合金からなることを特徴とする請求項２４記載の半導体パッケージ。
  27. 前記不動態被膜は、ポリマーからなることを特徴とする請求項１６記載の半導体パッケージ。
  28. 前記ポリマーは、ポリシロキサンであることを特徴とする請求項２７記載の半導体パッケージ。
JP2007531463A 2004-09-13 2005-09-13 半導体パッケージ Active JP5497985B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US60959704P 2004-09-13 2004-09-13
US60/609,597 2004-09-13
PCT/US2005/032743 WO2006031886A2 (en) 2004-09-13 2005-09-13 Power semiconductor package

Publications (2)

Publication Number Publication Date
JP2008512876A JP2008512876A (ja) 2008-04-24
JP5497985B2 true JP5497985B2 (ja) 2014-05-21

Family

ID=36060673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007531463A Active JP5497985B2 (ja) 2004-09-13 2005-09-13 半導体パッケージ

Country Status (4)

Country Link
US (3) US7466012B2 (ja)
JP (1) JP5497985B2 (ja)
CN (1) CN100444371C (ja)
WO (1) WO2006031886A2 (ja)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5497985B2 (ja) 2004-09-13 2014-05-21 インターナショナル レクティフィアー コーポレイション 半導体パッケージ
US20060202320A1 (en) * 2005-03-10 2006-09-14 Schaffer Christopher P Power semiconductor package
US7671455B2 (en) * 2005-11-02 2010-03-02 International Rectifier Corporation Semiconductor device package with integrated heat spreader
US20070187288A1 (en) * 2006-02-16 2007-08-16 Haggard Clifton C Disk holding device
US7655962B2 (en) * 2007-02-23 2010-02-02 Sensor Electronic Technology, Inc. Enhancement mode insulated gate heterostructure field-effect transistor with electrically isolated RF-enhanced source contact
US7674666B2 (en) * 2007-02-23 2010-03-09 Sensor Electronic Technology, Inc. Fabrication of semiconductor device having composite contact
US8174099B2 (en) * 2008-08-13 2012-05-08 Atmel Corporation Leadless package with internally extended package leads
US8395392B2 (en) * 2008-12-23 2013-03-12 Sensor Electronic Technology, Inc. Parameter extraction using radio frequency signals
US8338871B2 (en) * 2008-12-23 2012-12-25 Sensor Electronic Technology, Inc. Field effect transistor with electric field and space-charge control contact
JP5468804B2 (ja) * 2009-03-31 2014-04-09 古河電気工業株式会社 半導体チップ、半導体パッケージ、パワーモジュール、及び半導体パッケージの製造方法
US8564110B2 (en) * 2009-10-27 2013-10-22 Alpha & Omega Semiconductor, Inc. Power device with bottom source electrode
US9391005B2 (en) * 2009-10-27 2016-07-12 Alpha And Omega Semiconductor Incorporated Method for packaging a power device with bottom source electrode
DE102011008952A1 (de) * 2011-01-19 2012-07-19 Texas Instruments Deutschland Gmbh Mehrchipmodul, Verfahren zum Betreiben desselben und DC/DC-Wandler
US8586997B2 (en) 2011-02-15 2013-11-19 Sensor Electronic Technology, Inc. Semiconductor device with low-conducting field-controlling element
WO2013036593A1 (en) 2011-09-06 2013-03-14 Sensor Electronic Technology, Inc. Semiconductor device with low-conducting field-controlling element
US9263533B2 (en) 2011-09-19 2016-02-16 Sensor Electronic Technology, Inc. High-voltage normally-off field effect transistor including a channel with a plurality of adjacent sections
US9748362B2 (en) 2011-09-19 2017-08-29 Sensor Electronic Technology, Inc. High-voltage normally-off field effect transistor with channel having multiple adjacent sections
US9673285B2 (en) 2011-11-21 2017-06-06 Sensor Electronic Technology, Inc. Semiconductor device with low-conducting buried and/or surface layers
US8994035B2 (en) 2011-11-21 2015-03-31 Sensor Electronic Technology, Inc. Semiconductor device with low-conducting buried and/or surface layers
US8581660B1 (en) * 2012-04-24 2013-11-12 Texas Instruments Incorporated Power transistor partial current sensing for high precision applications
CN103545268B (zh) * 2012-07-09 2016-04-13 万国半导体股份有限公司 底部源极的功率器件及制备方法
TWI503929B (zh) * 2012-07-09 2015-10-11 萬國半導體股份有限公司 底部源極的功率裝置及製備方法
US9184111B2 (en) * 2013-11-09 2015-11-10 Delta Electronics, Inc. Wafer-level chip scale package
KR102163725B1 (ko) 2013-12-03 2020-10-08 삼성전자주식회사 반도체 소자 및 그 제조방법
KR102153041B1 (ko) 2013-12-04 2020-09-07 삼성전자주식회사 반도체소자 패키지 및 그 제조방법
US10515910B2 (en) 2014-11-07 2019-12-24 Infineon Technologies Ag Semiconductor device having a porous metal layer and an electronic device having the same
US9324819B1 (en) 2014-11-26 2016-04-26 Delta Electronics, Inc. Semiconductor device
TWI604583B (zh) * 2016-10-05 2017-11-01 矽品精密工業股份有限公司 線路結構及疊層組合
US10074597B2 (en) 2017-01-20 2018-09-11 Infineon Technologies Austria Ag Interdigit device on leadframe for evenly distributed current flow
US10692801B2 (en) 2018-05-31 2020-06-23 Infineon Technologies Austria Ag Bond pad and clip configuration for packaged semiconductor device
US11289407B2 (en) * 2020-06-23 2022-03-29 Vanguard International Semiconductor Corporation Package structure
KR20220064662A (ko) * 2020-11-12 2022-05-19 삼성전자주식회사 반도체 소자 패키지 및 그 제조방법

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3878553A (en) * 1972-12-26 1975-04-15 Texas Instruments Inc Interdigitated mesa beam lead diode and series array thereof
JPS55130178A (en) * 1979-03-30 1980-10-08 Fujitsu Ltd Semiconductor device
US4390598A (en) * 1982-04-05 1983-06-28 Fairchild Camera & Instrument Corp. Lead format for tape automated bonding
US4721986A (en) * 1984-02-21 1988-01-26 International Rectifier Corporation Bidirectional output semiconductor field effect transistor and method for its maufacture
US4635092A (en) * 1984-06-04 1987-01-06 General Electric Company Tape automated manufacture of power semiconductor devices
US4755697A (en) * 1985-07-17 1988-07-05 International Rectifier Corporation Bidirectional output semiconductor field effect transistor
GB8519373D0 (en) 1985-08-01 1985-09-04 Unilever Plc Encapsulation of fet transducers
JPS62188275A (ja) 1986-02-13 1987-08-17 Nec Corp 電界効果トランジスタ
JP2698645B2 (ja) * 1988-05-25 1998-01-19 株式会社東芝 Ｍｏｓｆｅｔ
JP2661442B2 (ja) * 1991-12-03 1997-10-08 日本電気株式会社 樹脂封止型半導体装置及びその製造方法
FR2691836B1 (fr) * 1992-05-27 1997-04-30 Ela Medical Sa Procede de fabrication d'un dispositif a semi-conducteurs comportant au moins une puce et dispositif correspondant.
JP3350152B2 (ja) * 1993-06-24 2002-11-25 三菱電機株式会社 半導体装置およびその製造方法
US5847436A (en) * 1994-03-18 1998-12-08 Kabushiki Kaisha Tokai Rika Denki Seisakusho Bipolar transistor having integrated thermistor shunt
US6093970A (en) * 1994-11-22 2000-07-25 Sony Corporation Semiconductor device and method for manufacturing the same
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
DE69723765T2 (de) 1996-05-17 2004-04-15 Eastman Kodak Co. Elektrofotografische Elemente mit bevorzugter Pigmentpartikelgrößenverteilung gewählte Titel weicht ab
JPH1074793A (ja) * 1996-08-30 1998-03-17 Sony Corp 半導体装置と、半導体装置の製造方法と、半導体製造装置
JPH10223901A (ja) * 1996-12-04 1998-08-21 Sony Corp 電界効果型トランジスタおよびその製造方法
JP3779789B2 (ja) * 1997-01-31 2006-05-31 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6166436A (en) * 1997-04-16 2000-12-26 Matsushita Electric Industrial Co., Ltd. High frequency semiconductor device
JP4122600B2 (ja) 1998-11-12 2008-07-23 三菱電機株式会社 電解効果トランジスタおよび半導体回路
KR20000057810A (ko) * 1999-01-28 2000-09-25 가나이 쓰토무 반도체 장치
JP3393602B2 (ja) * 2000-01-13 2003-04-07 松下電器産業株式会社 半導体装置
EP1258040A4 (en) * 2000-02-10 2009-07-01 Int Rectifier Corp VERTICAL-CONDUCTING PROTUBERANCE CHIP WITH CONTACT PLOTS ON ONE SURFACE
EP1278249B8 (en) * 2000-03-31 2013-11-27 Toyoda Gosei Co., Ltd. Group-iii nitride compound semiconductor device
US6512304B2 (en) 2000-04-26 2003-01-28 International Rectifier Corporation Nickel-iron expansion contact for semiconductor die
JP2002040095A (ja) * 2000-07-26 2002-02-06 Nec Corp 半導体装置及びその実装方法
JP4055459B2 (ja) 2001-04-24 2008-03-05 日産化学工業株式会社 シリカ系被膜及びその形成方法、並びに、シリカ系被膜を形成するための塗布液及びその製造方法
JP4041660B2 (ja) * 2001-05-31 2008-01-30 ユーディナデバイス株式会社 半導体装置及びその製造方法
US20040212017A1 (en) * 2001-08-07 2004-10-28 Hirotaka Mizuno Semiconductor device and ic card
US6936855B1 (en) * 2002-01-16 2005-08-30 Shane Harrah Bendable high flux LED array
JP2003258179A (ja) * 2002-02-28 2003-09-12 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP2003258001A (ja) 2002-03-05 2003-09-12 Murata Mfg Co Ltd 高周波半導体装置
US6853072B2 (en) * 2002-04-17 2005-02-08 Sanyo Electric Co., Ltd. Semiconductor switching circuit device and manufacturing method thereof
US20030218246A1 (en) * 2002-05-22 2003-11-27 Hirofumi Abe Semiconductor device passing large electric current
JP2004039657A (ja) * 2002-06-28 2004-02-05 Renesas Technology Corp 半導体装置
JP4463482B2 (ja) * 2002-07-11 2010-05-19 パナソニック株式会社 Ｍｉｓｆｅｔ及びその製造方法
JP2004080221A (ja) * 2002-08-13 2004-03-11 Fujitsu Media Device Kk 弾性波デバイス及びその製造方法
TW200427111A (en) * 2003-03-12 2004-12-01 Shinetsu Chemical Co Material for coating/protecting light-emitting semiconductor and the light-emitting semiconductor device
US20050199899A1 (en) * 2004-03-11 2005-09-15 Ming-Der Lin Package array and package unit of flip chip LED
US7475964B2 (en) * 2004-08-06 2009-01-13 Hewlett-Packard Development Company, L.P. Electrical contact encapsulation
JP5497985B2 (ja) * 2004-09-13 2014-05-21 インターナショナル レクティフィアー コーポレイション 半導体パッケージ
US7288803B2 (en) * 2004-10-01 2007-10-30 International Rectifier Corporation III-nitride power semiconductor device with a current sense electrode
US7402845B2 (en) * 2005-12-30 2008-07-22 International Rectifier Corporation Cascoded rectifier package

Also Published As

Publication number Publication date
CN100444371C (zh) 2008-12-17
WO2006031886A2 (en) 2006-03-23
US20060131760A1 (en) 2006-06-22
US9048196B2 (en) 2015-06-02
WO2006031886A3 (en) 2006-06-15
CN101015055A (zh) 2007-08-08
US20150262960A1 (en) 2015-09-17
US9620471B2 (en) 2017-04-11
JP2008512876A (ja) 2008-04-24
US7466012B2 (en) 2008-12-16
US20090008804A1 (en) 2009-01-08

Similar Documents

Publication Publication Date Title
JP5497985B2 (ja) 半導体パッケージ
JP5558714B2 (ja) 半導体パッケージ
CN102308383B (zh) 半导体管芯封装件及其制造方法
US8188587B2 (en) Semiconductor die package including lead with end portion
US20110284997A1 (en) Chip-Exposed Semiconductor Device and Its Packaging Method
KR20080055670A (ko) 차폐케이스를 구비한 패키지
KR20170086828A (ko) 메탈범프를 이용한 클립 본딩 반도체 칩 패키지
US7656034B2 (en) Semiconductor device and method for manufacturing the same
US20180096918A1 (en) Lead And Lead Frame For Power Package
JP2008294219A (ja) 半導体装置及びその製造方法
JP3685659B2 (ja) 半導体装置の製造方法
JP5025394B2 (ja) 半導体装置及びその製造方法
JP2006310609A (ja) 半導体装置
CN114203659A (zh) 多层互连带
JP4694594B2 (ja) 半導体装置
US11929306B2 (en) Semiconductor device comprising first and second lead frames
JP3995661B2 (ja) パワーｍｏｓｆｅｔの製造方法
JP2007251218A (ja) パワーｍｏｓｆｅｔの製造方法およびパワーｍｏｓｆｅｔ
KR101473356B1 (ko) 히트 슬러그의 접지방법
JP2005064532A (ja) 半導体装置
CN115810602A (zh) 半导体装置
JP2003051513A (ja) 半導体装置の実装用部材、半導体装置の実装構造、半導体装置の実装方法
JP2004119699A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
US20080211085A1 (en) Semiconductor package having insulating substrate
JP2004207310A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器

Legal Events

Date Code Title Description
RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20091201

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100409

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100511

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20100621

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20100628

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100913

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20101015

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101019

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20110118

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20110125

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110128

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20110221

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20110228

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110322

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110726

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20110812

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20110819

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20111117

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20111125

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20111222

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20120105

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120126

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120515

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120918

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20120926

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20121130

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20130329

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20130403

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20130507

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20130510

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20131015

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20131018

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20131114

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20131119

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131216

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140307

R150 Certificate of patent or registration of utility model

Ref document number: 5497985

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250