US7402845B2 - Cascoded rectifier package - Google Patents

Cascoded rectifier package Download PDF

Info

Publication number
US7402845B2
US7402845B2 US11/649,120 US64912007A US7402845B2 US 7402845 B2 US7402845 B2 US 7402845B2 US 64912007 A US64912007 A US 64912007A US 7402845 B2 US7402845 B2 US 7402845B2
Authority
US
United States
Prior art keywords
package
conductive pad
another
conductive
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US11/649,120
Other versions
US20070176291A1 (en
Inventor
Chuan Cheah
Kunzhong Hu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies North America Corp
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Priority to US11/649,120 priority Critical patent/US7402845B2/en
Assigned to INTERNATIONAL RECTIFIER CORPORATION reassignment INTERNATIONAL RECTIFIER CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEAH, CHUAN, HU, KUNZHONG
Publication of US20070176291A1 publication Critical patent/US20070176291A1/en
Application granted granted Critical
Publication of US7402845B2 publication Critical patent/US7402845B2/en
Assigned to Infineon Technologies Americas Corp. reassignment Infineon Technologies Americas Corp. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL RECTIFIER CORPORATION
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H01L2224/37599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the present invention relates to power semiconductor rectifier packages and particularly to III-nitride type compound semiconductor component (CSC) heterojunction type semiconductor devices, including bidirectional III-nitride transistors, used in such packages.
  • CSC III-nitride type compound semiconductor component
  • Power semiconductor devices including rectifiers used for PFC (power factor correction) applications, that include a single material semiconductor device, such as a silicon-based power semiconductor device (e.g. silicon-based or SiC based diodes), are well known.
  • silicon-based power semiconductor device e.g. silicon-based or SiC based diodes
  • SiC silicon carbide
  • Such rectifiers typically have inherent weaknesses, such as a surge current capability and forward conduction limitations.
  • CSC transistors e.g. heterojunction III-nitride based power semiconductor devices (referred to hereafter as compound semiconductor component, or CSC), for example, high electron mobility transistors (HEMTs), metal insulator semiconductor (MISHEMTs), metal oxide semiconductor (MOSHEMTs), and the like devices, are known.
  • HEMTs high electron mobility transistors
  • MISHEMTs metal insulator semiconductor
  • MOSHEMTs metal oxide semiconductor
  • An example of a bidirectional CSC is disclosed in U.S. patent application Ser. No. 11/056,062, assigned to International Rectifier and incorporated herein by reference. It is known to arrange a bidirectional CSC with a diode in a cascode configuration in a circuit to obtain a rectifier suitable for applications such as PFC.
  • a CSC packaged with a diode it is desirable to have a CSC packaged with a diode to use as a rectifier package that can be used as an integrated device in a power application such as a PFC.
  • a semiconductor package includes a substrate having a first conductive pad and a second conductive pad spaced and isolated electrically from the first conductive pad both pads disposed on a common surface; a III-nitride compound semiconductor component including two power electrodes, and a gate electrode; a diode arrangement connected at one pole thereof to one of the power electrodes through the first conductive pad and to the gate electrode at another one of the poles through the second conductive pad, whereby the diode arrangement and the compound semiconductor component are operatively connected to one another wirebondlessly.
  • the CSC is a bidirectional switch having two gate electrodes and the diode arrangement includes two diodes.
  • a package according to the present invention may further include a strap for connecting the diode arrangement to one of the gates of the CSC.
  • the package may include a heat spreader which thermally connects the CSC to the substrate.
  • FIG. 1A shows a circuit diagram of a boost converter according to the prior art.
  • FIG. 1B shows a top plan view of a bidirectional CSC used in a package according to the present invention.
  • FIG. 2 illustrates a cascoded rectifier arrangement using a bidirectional CSC and a diode arrangement.
  • FIG. 3 illustrates another cascoded rectifier arrangement using a bidirectional CSC and a diode arrangement.
  • FIG. 4A shows a top plan view of a package according to the present invention.
  • FIG. 4B shows a cross-sectional view along line 4 B- 4 B viewed in the direction of the arrows.
  • FIG. 4C shows a cross-sectional view along line 4 C- 4 C viewed in the direction of the arrows.
  • FIG. 4D shows a cross-sectional view along line 4 D- 4 D viewed in the direction of the arrows.
  • FIG. 4E shows a top plan view of a substrate used in a package according to the present invention.
  • FIG. 4F illustrates a bottom plan view of a substrate used in a package according to the present invention.
  • FIGS. 5A-5D illustrate selected steps in the fabrication of a package according to the present invention.
  • a typical PFC circuit may be a boost circuit which includes a diode 10 as a rectifier.
  • a typical bidirectional CSC 12 includes a first gate pad 14 disposed at one comer of the die, a second gate pad 16 disposed at another opposing corner of the die, first power electrodes 18 , and second power electrodes 20 .
  • first and second power electrodes 18 and 20 may be alternately arranged.
  • first and second power electrodes 18 , 20 may serve as both source or drain depending on the direction of the current.
  • FIG. 2 illustrates schematically the arrangement of a bidirectional CSC and a diode arrangement (or a plurality) of diodes to form a cascoded rectifier which can replace diode 10 in a PFC circuit.
  • the arrangement includes a bidirectional CSC 12 , having first gate pad 14 thereof shorted to its first power electrodes 18 , and second gate pad 16 thereof shorted to second power electrodes 20 through a diode arrangement 22 .
  • diode arrangement 22 may include a single diode having the anode 24 thereof shorted to an external lead and the cathode 26 thereof shorted to second power electrodes 20 of CSC 12 .
  • first power electrodes 18 of CSC 12 are shorted to another external lead 30 .
  • Diode arrangement 22 may be two or more diodes connected to obtain the same rating of a larger diode.
  • first gate pad 14 of CSC 12 may be shorted to another external lead 32 instead of being shorted to first power electrodes 18 of CSC 12 .
  • the arrangement shown by FIG. 3 is identical to the one shown by FIG. 2 .
  • a semiconductor package according to the preferred embodiment of the present invention includes substrate 34 , which may be an IMS, DBC or the like, CSC 12 , two diodes 22 A, 22 B, which constitute diode arrangement 22 , and molded housing 36 .
  • substrate 34 which may be an IMS, DBC or the like
  • CSC 12 two diodes 22 A, 22 B, which constitute diode arrangement 22
  • molded housing 36 is rendered transparent in FIG. 4A for better illustration.
  • diodes 22 A, 22 B may be replaced with a single diode.
  • First and second power electrodes 18 , 20 of CSC 12 are electrically and mechanically coupled to respective conductive fingers 38 , 40 on substrate 34 , and cathode electrodes of diodes 22 A, 22 B are electrically and mechanically coupled to a conductive pad 42 on substrate 34 .
  • Conductive fingers 38 are connected to second power electrodes 20 and are integral with conductive pad 42 whereby second power electrodes 20 are electrically connected to cathode electrodes of diodes 22 A, 22 B.
  • a conductive strap 44 (formed preferably from copper or copper alloy) is electrically and mechanically coupled to the anode electrodes of diodes 22 A, 22 B and electrically and mechanically coupled to a second conductive pad 48 .
  • Fingers 40 are electrically and mechanically coupled to first power electrodes 18 of CSC 12 and are integral with a third conductive pad 50 .
  • substrate 34 includes a fourth conductive pad 52 , which is electrically and mechanically coupled to first gate pad 14 of CSC 12 .
  • each conductive pad 42 , 48 , 50 , 52 is electrically connected to a respective land on an opposing surface of substrate 34 through one metal filled via or a number of metal filled vias (not shown) in substrate 34 .
  • FIG. 4F shows the bottom view of the package to illustrate the land arrangement in the preferred embodiment.
  • a heat spreader 62 (formed preferably from copper or a copper alloy) is thermally and mechanically connected to the back of CSC 22 using a thermal epoxy or the like material. Heat spreader 62 is then extended to and thermally coupled to substrate 34 using a thermally conductive adhesive such as a thermal epoxy or the like.
  • Molded housing 36 which is preferably formed from a mold compound, preferably covers strap 44 , heat spreader 36 , and encapsulates diodes 22 A, 22 B, and CSC 12 .
  • a conductive adhesive such as a conductive epoxy or solder may be used.
  • a layer of solder resist 64 is applied to the top surface of substrate 34 (see FIG. 4E ) and patterned to include openings over fingers 38 , 40 , pads 42 , 48 , 56 , 52 as illustrated by FIG. 5A .
  • a conductive adhesive e.g. solder or conductive epoxy
  • Cathode electrodes of diodes 22 A, 22 B are then disposed over the conductive adhesive on pad 42 , and CSC 12 is flip mounted such that second power electrodes 20 thereof are disposed on the conductive adhesive on fingers 38 .
  • first power electrodes 18 are disposed on the conductive adhesive on fingers 40 .
  • first gate pad 14 of CSC 12 is disposed on the conductive adhesive that is on pad 52
  • second gate pad 16 is disposed on the conductive adhesive that is on pad 48 .
  • pad 48 is exposed through two openings 48 ′, 48 ′′. Opening 48 ′ receives a conductive adhesive body for connection to second gate pad 16 .
  • a conductive adhesive is applied to the anode electrodes of diodes 22 A, 22 B and pad 48 through opening 48 ′′, and the arrangement is exposed to heat to cure the adhesive. For example, if solder is used, the arrangement is taken to the reflow temperature of the solder.
  • FIG. 5C illustrates the results after the curing step.
  • thermally conductive adhesive 66 e.g. thermal epoxy
  • Spreader 62 is then disposed on both thermally conductive adhesive bodies 66 , and cured, for example, in a thermal step.
  • mold compound is applied to form molded housing 36 as explained, whereby a package according to the present invention is obtained.
  • no wirebonding is used to integrate CSC 12 and diode arrangement 22 , which may reduce packaging related parasitic resistance and inductance.
  • thermoly conductive substrate such as an IMS
  • a conductive strap and a heat spreader may result in favorable thermal characteristics.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor package that includes a compound component and a diode arranged in a cascode configuration to function as a rectifier.

Description

RELATED APPLICATION
This application claims benefit of U.S. Provisional Application Ser. No. 60/755,646, filed on Dec. 30, 2005, entitled GaN Cascoded Rectifier and Package Therefor, incorporated in full herein by reference.
FIELD OF THE INVENTION
The present invention relates to power semiconductor rectifier packages and particularly to III-nitride type compound semiconductor component (CSC) heterojunction type semiconductor devices, including bidirectional III-nitride transistors, used in such packages.
BACKGROUND OF THE INVENTION
Power semiconductor devices, including rectifiers used for PFC (power factor correction) applications, that include a single material semiconductor device, such as a silicon-based power semiconductor device (e.g. silicon-based or SiC based diodes), are well known. For example, silicon carbide (SiC) high voltage schottky rectifiers offer an absence of recovery charges, which makes them suitable for hard switched, high frequency applications like power factor correction. However, such rectifiers typically have inherent weaknesses, such as a surge current capability and forward conduction limitations.
CSC transistors, e.g. heterojunction III-nitride based power semiconductor devices (referred to hereafter as compound semiconductor component, or CSC), for example, high electron mobility transistors (HEMTs), metal insulator semiconductor (MISHEMTs), metal oxide semiconductor (MOSHEMTs), and the like devices, are known. An example of a bidirectional CSC is disclosed in U.S. patent application Ser. No. 11/056,062, assigned to International Rectifier and incorporated herein by reference. It is known to arrange a bidirectional CSC with a diode in a cascode configuration in a circuit to obtain a rectifier suitable for applications such as PFC.
It is desirable to have a CSC packaged with a diode to use as a rectifier package that can be used as an integrated device in a power application such as a PFC.
SUMMARY OF THE INVENTION
A semiconductor package according to the present invention includes a substrate having a first conductive pad and a second conductive pad spaced and isolated electrically from the first conductive pad both pads disposed on a common surface; a III-nitride compound semiconductor component including two power electrodes, and a gate electrode; a diode arrangement connected at one pole thereof to one of the power electrodes through the first conductive pad and to the gate electrode at another one of the poles through the second conductive pad, whereby the diode arrangement and the compound semiconductor component are operatively connected to one another wirebondlessly.
In the preferred embodiment, the CSC is a bidirectional switch having two gate electrodes and the diode arrangement includes two diodes. A package according to the present invention may further include a strap for connecting the diode arrangement to one of the gates of the CSC. Furthermore, the package may include a heat spreader which thermally connects the CSC to the substrate.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1A shows a circuit diagram of a boost converter according to the prior art.
FIG. 1B shows a top plan view of a bidirectional CSC used in a package according to the present invention.
FIG. 2 illustrates a cascoded rectifier arrangement using a bidirectional CSC and a diode arrangement.
FIG. 3 illustrates another cascoded rectifier arrangement using a bidirectional CSC and a diode arrangement.
FIG. 4A shows a top plan view of a package according to the present invention.
FIG. 4B shows a cross-sectional view along line 4B-4B viewed in the direction of the arrows.
FIG. 4C shows a cross-sectional view along line 4C-4C viewed in the direction of the arrows.
FIG. 4D shows a cross-sectional view along line 4D-4D viewed in the direction of the arrows.
FIG. 4E shows a top plan view of a substrate used in a package according to the present invention.
FIG. 4F illustrates a bottom plan view of a substrate used in a package according to the present invention.
FIGS. 5A-5D illustrate selected steps in the fabrication of a package according to the present invention.
 DETAILED DESCRIPTION OF THE FIGURES
Referring to FIG. 1A, a typical PFC circuit may be a boost circuit which includes a diode 10 as a rectifier.
Referring to FIG. 1B, a typical bidirectional CSC 12 includes a first gate pad 14 disposed at one comer of the die, a second gate pad 16 disposed at another opposing corner of the die, first power electrodes 18, and second power electrodes 20. Note that first and second power electrodes 18 and 20 may be alternately arranged. In a bidirectional first and second power electrodes 18, 20 may serve as both source or drain depending on the direction of the current.
FIG. 2 illustrates schematically the arrangement of a bidirectional CSC and a diode arrangement (or a plurality) of diodes to form a cascoded rectifier which can replace diode 10 in a PFC circuit. The arrangement includes a bidirectional CSC 12, having first gate pad 14 thereof shorted to its first power electrodes 18, and second gate pad 16 thereof shorted to second power electrodes 20 through a diode arrangement 22. Note that diode arrangement 22 may include a single diode having the anode 24 thereof shorted to an external lead and the cathode 26 thereof shorted to second power electrodes 20 of CSC 12. Note further that first power electrodes 18 of CSC 12 are shorted to another external lead 30. Diode arrangement 22 may be two or more diodes connected to obtain the same rating of a larger diode.
Referring now to FIG. 3, in an alternative arrangement, first gate pad 14 of CSC 12 may be shorted to another external lead 32 instead of being shorted to first power electrodes 18 of CSC 12. In all other respects, the arrangement shown by FIG. 3 is identical to the one shown by FIG. 2.
Referring now to FIGS. 4A-4F, a semiconductor package according to the preferred embodiment of the present invention includes substrate 34, which may be an IMS, DBC or the like, CSC 12, two diodes 22A, 22B, which constitute diode arrangement 22, and molded housing 36. Note that molded housing 36 is rendered transparent in FIG. 4A for better illustration. Further note that diodes 22A, 22B may be replaced with a single diode.
First and second power electrodes 18, 20 of CSC 12 are electrically and mechanically coupled to respective conductive fingers 38, 40 on substrate 34, and cathode electrodes of diodes 22A, 22B are electrically and mechanically coupled to a conductive pad 42 on substrate 34. Conductive fingers 38 are connected to second power electrodes 20 and are integral with conductive pad 42 whereby second power electrodes 20 are electrically connected to cathode electrodes of diodes 22A, 22B.
A conductive strap 44 (formed preferably from copper or copper alloy) is electrically and mechanically coupled to the anode electrodes of diodes 22A, 22B and electrically and mechanically coupled to a second conductive pad 48. Fingers 40 are electrically and mechanically coupled to first power electrodes 18 of CSC 12 and are integral with a third conductive pad 50. Note that substrate 34 includes a fourth conductive pad 52, which is electrically and mechanically coupled to first gate pad 14 of CSC 12. Also note that each conductive pad 42, 48, 50, 52 is electrically connected to a respective land on an opposing surface of substrate 34 through one metal filled via or a number of metal filled vias (not shown) in substrate 34. Thus, conductive pad 42 is connected to land 54, pad 48 is connected to land 56, pad 50 is connected to land 58, and pad 52 is connected to land 60. Lands 54, 56, 58 and 60 serve as leads for external connection to the package. FIG. 4F shows the bottom view of the package to illustrate the land arrangement in the preferred embodiment.
According to one aspect of the present invention, a heat spreader 62 (formed preferably from copper or a copper alloy) is thermally and mechanically connected to the back of CSC 22 using a thermal epoxy or the like material. Heat spreader 62 is then extended to and thermally coupled to substrate 34 using a thermally conductive adhesive such as a thermal epoxy or the like. Molded housing 36, which is preferably formed from a mold compound, preferably covers strap 44, heat spreader 36, and encapsulates diodes 22A, 22B, and CSC 12.
Note that to obtain electrical and mechanical coupling as disclosed herein a conductive adhesive such as a conductive epoxy or solder may be used.
Referring to FIGS. 5A-5D, in order to fabricate a package according to the present invention, first a layer of solder resist 64 is applied to the top surface of substrate 34 (see FIG. 4E) and patterned to include openings over fingers 38, 40, pads 42, 48, 56, 52 as illustrated by FIG. 5A. Next, a conductive adhesive (e.g. solder or conductive epoxy) is applied to pad 42, and fingers 38, 40 which are exposed through openings in solder resist 64. Cathode electrodes of diodes 22A, 22B are then disposed over the conductive adhesive on pad 42, and CSC 12 is flip mounted such that second power electrodes 20 thereof are disposed on the conductive adhesive on fingers 38. Similarly, first power electrodes 18 are disposed on the conductive adhesive on fingers 40. In addition, first gate pad 14 of CSC 12 is disposed on the conductive adhesive that is on pad 52, and second gate pad 16 is disposed on the conductive adhesive that is on pad 48. Note that pad 48 is exposed through two openings 48′, 48″. Opening 48′ receives a conductive adhesive body for connection to second gate pad 16. Thereafter, a conductive adhesive is applied to the anode electrodes of diodes 22A, 22B and pad 48 through opening 48″, and the arrangement is exposed to heat to cure the adhesive. For example, if solder is used, the arrangement is taken to the reflow temperature of the solder. FIG. 5C illustrates the results after the curing step.
Next, a thermally conductive adhesive 66 (e.g. thermal epoxy) is applied to the back of CSC 12 and a portion of substrate 34 (see FIG. 5D). Spreader 62 is then disposed on both thermally conductive adhesive bodies 66, and cured, for example, in a thermal step. Thereafter, mold compound is applied to form molded housing 36 as explained, whereby a package according to the present invention is obtained.
Advantageously, no wirebonding is used to integrate CSC 12 and diode arrangement 22, which may reduce packaging related parasitic resistance and inductance.
Moreover, using a combination thermally conductive substrate such as an IMS, a conductive strap and a heat spreader may result in favorable thermal characteristics.
Although the present invention has been described in relation to particular embodiments thereof, many other variations, combinations of features, and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

Claims (11)

1. A semiconductor package, comprising:
a substrate having a first conductive pad and a second conductive pad spaced and isolated electrically from said first conductive pad both pads disposed on a common surface;
a III-nitride compound semiconductor component including two power electrodes, and a gate electrode;
a diode arrangement connected at one pole thereof to one of said power electrodes through said first conductive pad and to said gate electrode at another one of said poles through said second conductive pad, whereby said diode arrangement and said compound semiconductor component are operatively connected to one another wirebondlessly.
2. The package of claim 1, further comprising a conductive strap electrically connected between said another one of said poles and said second conductive pad.
3. The package of claim 1, further comprising a heat spreader thermally connected to said compound semiconductor component and thermally connected to said substrate.
4. The package of claim 1, further comprising a third conductive pad electrically connected to another one of said power electrodes.
5. The package of claim 4, wherein said compound semiconductor component includes another gate electrode and further comprising a fourth conductive pad electrically connected to said another gate electrode.
6. The package of claim 4, wherein each power electrode is electrically connected to a conductive pad through a respective finger.
7. The package of claim 4, wherein each conductive pad is electrically connected to a respective land on another common surface opposite said common surface.
8. The package of claim 4, wherein each conductive pad is electrically connected to a respective land on another common surface opposite said common surface.
9. The package of claim 1, wherein said diode arrangement includes two diodes.
10. The package of claim 1, wherein said compound semiconductor component is a bidirectional switch.
11. The package of claim 1, wherein said compound semiconductor component includes a plurality of first power electrode and a plurality of second power electrodes, said power electrodes being alternately arranged, wherein each power electrode is electrically and mechanically connected to a respective conductive finger which is connected to a respective conductive pad on said substrate.
US11/649,120 2005-12-30 2007-01-03 Cascoded rectifier package Active 2027-02-08 US7402845B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/649,120 US7402845B2 (en) 2005-12-30 2007-01-03 Cascoded rectifier package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US75564605P 2005-12-30 2005-12-30
US11/649,120 US7402845B2 (en) 2005-12-30 2007-01-03 Cascoded rectifier package

Publications (2)

Publication Number Publication Date
US20070176291A1 US20070176291A1 (en) 2007-08-02
US7402845B2 true US7402845B2 (en) 2008-07-22

Family

ID=38321244

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/649,120 Active 2027-02-08 US7402845B2 (en) 2005-12-30 2007-01-03 Cascoded rectifier package

Country Status (1)

Country Link
US (1) US7402845B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110019450A1 (en) * 2009-07-21 2011-01-27 Robert Callanan High Speed Rectifier Circuit
US9536800B2 (en) 2013-12-07 2017-01-03 Fairchild Semiconductor Corporation Packaged semiconductor devices and methods of manufacturing

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5497985B2 (en) 2004-09-13 2014-05-21 インターナショナル レクティフィアー コーポレイション Semiconductor package
US8816497B2 (en) 2010-01-08 2014-08-26 Transphorm Inc. Electronic devices and components for high efficiency power circuits
US8847563B2 (en) * 2010-07-15 2014-09-30 Cree, Inc. Power converter circuits including high electron mobility transistors for switching and rectifcation
WO2012055570A1 (en) * 2010-10-28 2012-05-03 Microgan Gmbh Diode circuit
US8546849B2 (en) * 2011-05-04 2013-10-01 International Rectifier Corporation High voltage cascoded III-nitride rectifier package utilizing clips on package surface
US8853707B2 (en) * 2011-05-04 2014-10-07 International Rectifier Corporation High voltage cascoded III-nitride rectifier package with etched leadframe
US8853706B2 (en) * 2011-05-04 2014-10-07 International Rectifier Corporation High voltage cascoded III-nitride rectifier package with stamped leadframe
US10658264B2 (en) 2017-09-01 2020-05-19 Analog Devices, Inc. Diamond-based heat spreading substrates for integrated circuit dies

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5616886A (en) * 1995-06-05 1997-04-01 Motorola Wirebondless module package
US7329909B2 (en) * 2005-02-02 2008-02-12 Kabushiki Kaisha Toshiba Nitride semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5616886A (en) * 1995-06-05 1997-04-01 Motorola Wirebondless module package
US7329909B2 (en) * 2005-02-02 2008-02-12 Kabushiki Kaisha Toshiba Nitride semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110019450A1 (en) * 2009-07-21 2011-01-27 Robert Callanan High Speed Rectifier Circuit
US8681518B2 (en) * 2009-07-21 2014-03-25 Cree, Inc. High speed rectifier circuit
US9536800B2 (en) 2013-12-07 2017-01-03 Fairchild Semiconductor Corporation Packaged semiconductor devices and methods of manufacturing

Also Published As

Publication number Publication date
US20070176291A1 (en) 2007-08-02

Similar Documents

Publication Publication Date Title
US7402845B2 (en) Cascoded rectifier package
US7220617B2 (en) Semiconductor device and method of manufacturing the same
US9530774B2 (en) Semiconductor package for III-nitride transistor stacked with diode
US9799627B2 (en) Semiconductor package structure and method
JP5558714B2 (en) Semiconductor package
US20240339421A1 (en) Electronic component and semiconductor device
US9852968B2 (en) Semiconductor device including a sealing region
US11011445B2 (en) Semiconductor package device
JP2012222361A (en) Stacked composite device including group iii-v transistor and group iv vertical transistor
KR102418458B1 (en) Power semiconductor module
JP7494271B2 (en) Semiconductor device and power module
JP2014131027A (en) Cascode circuit integration of group iii-n and group iv devices
KR20070100849A (en) Power semiconductor package
US10685909B2 (en) Power package having multiple mold compounds
CN116525588A (en) Semiconductor device and preparation method thereof
US20240014193A1 (en) Semiconductor device
US9824958B2 (en) Chip carrier structure, chip package and method of manufacturing the same
US9754862B2 (en) Compound semiconductor device including a multilevel carrier
US10848074B2 (en) High voltage bridge rectifier
JP2013197590A (en) Group iii-v and group iv composite diode
CN220121840U (en) Semiconductor device, casode device and driving sealing power device
CN103545283B (en) Semiconductor packages with multiple lead frames and forming method thereof
JP2004221381A (en) Semiconductor device
US9806008B1 (en) Clip based semiconductor package for increasing exposed leads
Lee et al. A new package of high-voltage cascode gallium nitride device for high-frequency applications

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL RECTIFIER CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEAH, CHUAN;HU, KUNZHONG;REEL/FRAME:019081/0707

Effective date: 20070110

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: INFINEON TECHNOLOGIES AMERICAS CORP., CALIFORNIA

Free format text: CHANGE OF NAME;ASSIGNOR:INTERNATIONAL RECTIFIER CORPORATION;REEL/FRAME:046612/0968

Effective date: 20151001

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12