JP2014131027A - Cascode circuit integration of group iii-n and group iv devices - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cascode circuit integration assembly of group III-N and group IV devices.SOLUTION: An integration assembly 200 includes a printed circuit board 230, and a depletion mode III-nitride transistor die 212 and a group IV transistor die 214 connected with the printed circuit board 230. The depletion mode III-nitride transistor die 212 is arranged on one side of the printed circuit board 230, and the group IV transistor die 214 is arranged on the reverse side of the printed circuit board 230. At least one via 220 in the printed circuit board 230 connects the depletion mode III-nitride transistor die 212 with the group IV transistor die 214 electrically. In many embodiments, the depletion mode III-nitride transistor die 212 and the group IV transistor die 214 are cascoded.

Description

  This application claims the benefit and priority of US Provisional Patent Application No. 61 / 738,945, “Cascode Circuit Integration of Group III-N and Group IV Devices,” filed December 18, 2012. The disclosure of the above application is fully incorporated by reference into the present application.

The following commonly assigned US patent application relates to other aspects of the embodiments disclosed in this application and describes other aspects of the embodiments disclosed in this application. This US patent application is fully incorporated by reference into this application.
-US Patent Application No. 13 / 018,780, filed on February 1, 2011 and patented as US Patent No. 8,399,912 "III-Nitride Power Device with Solderable Front Metal"
・ US Patent Application No. 09 / 780,080 “Vertical Conduction Flip-Chip Device with Bump Contacts on Single Surface” filed on Feb. 9, 2001 and patented as US Pat. No. 6,653,740
US patent application Ser. No. 09 / 819,774, filed Mar. 28, 2001 and patented as US Pat. No. 6,624,522, “Chip Scale Surface Mounted Device and Process of Manufacture”
US patent application Ser. No. 11 / 372,679, filed Mar. 10, 2006 and patented as US Pat. No. 8,017,978 “Hybrid Semiconductor Device”

Definitions As used herein, the term “Group III-V” means a compound semiconductor comprising at least one Group III element and at least one Group V element. For example, a group III-V semiconductor can take the form of a group III-nitride semiconductor (group III nitride semiconductor). “III-nitride” or “III-N” is a compound semiconductor containing nitrogen and at least one group III element such as aluminum (Al), gallium (Ga), indium (In), and boron (B). For example, aluminum gallium nitride (Al _x Ga _(1-x) N), indium gallium nitride (In _y Ga _(1-y) N), aluminum indium gallium nitride (Al _x In _y Ga _(1-xy) N ), arsenide gallium nitride phosphide _{(GaAs a P b N (1} -ab)), arsenide phosphide aluminum indium gallium nitride _{(Al x In y Ga (1} -xy) As a P b N (1-ab)) such as However, it is not limited to these. In addition, III-nitrides generally have any polarity including, but not limited to, Ga polarity, N polarity, semipolar or nonpolar crystal orientation. In addition, the III-nitride material can include either a wurtzite type, a zinc blende type, or a mixed crystal polymorph, and include a single crystal or monocrystal, a polycrystal, or an amorphous crystal structure. Can do. As used herein, “gallium nitride”, “GaN” means a III-nitride compound semiconductor, and group III elements contain some or substantial amounts of gallium, but in addition to gallium, other group III Elements can also be included. Further, the III-V group or GaN transistor means a composite high voltage enhancement mode transistor formed by connecting a low voltage group IV transistor and a group III-V or GaN transistor with a cascode.

  Furthermore, as used herein, “LV device”, “low voltage semiconductor device”, “low voltage transistor”, etc. means a low voltage device having a typical voltage range of up to about 50 volts. Typical voltage ranges are low voltage (LV): about 0 V to 50 V, intermediate voltage (MV): about 50 V to 200 V, high voltage (HV): about 200 V to 1200 V, ultra high voltage (UHV): about 1200 V including. The LV device may comprise any suitable group IV semiconductor material. Also, as used herein, the term “Group IV” refers to a semiconductor comprising at least one Group IV element including silicon (Si), germanium (Ge) and carbon (C), eg, SiGe and SiC. Including compound semiconductors such as Group IV also refers to a semiconductor material consisting of a layer of Group IV elements or doping of Group IV elements to produce strained silicon or other strained Group IV materials. Further, the group IV-based composite substrate may include, for example, an SOI (semiconductor on insulator), a SIMOX (separation by implantation of oxygen) process substrate, and an SOS (silicon on sapphire). Furthermore, Group IV devices can include devices formed using a CMOS process, but can also include NMOS and PMOS device processes.

  III-nitride materials are semiconducting compounds with a relatively wide, direct band gap and potentially strong piezoelectric polarization, allowing for the creation of high breakdown fields, high saturation rates, and two-dimensional electron gas (2DEG) . As a result, III-nitride materials are used in many power applications such as depletion mode (eg, normally-on) III-nitride transistors (eg, high electron mobility transistors), and diodes.

  In certain applications, it is desirable to couple a depletion mode III-nitride transistor to a group IV transistor (eg, a silicon transistor). For example, in power management applications where normally-off characteristics of power devices are generally desired, a depletion mode III-nitride transistor can be cascode connected with a group IV transistor to produce an enhancement mode composite device. Also, depletion mode III-nitride transistors and group IV transistors need to be efficiently packaged or assembled to meet cost, performance, size, and throughput requirements.

  The present invention is directed to cascode circuit integration of III-N and Group IV devices, substantially as shown and / or described in at least one of the drawings, and more in the claims. It will be fully revealed.

FIG. 3 shows a circuit diagram of an exemplary power conversion circuit according to an embodiment of the present disclosure. FIG. 3 presents an exemplary circuit diagram of a depletion mode III-nitride transistor coupled to a group IV transistor according to one embodiment of the present disclosure. FIG. 3 presents a top view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure. FIG. 3 presents a cross-sectional view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure. FIG. 3 presents a cross-sectional view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure. FIG. 3 presents a cross-sectional view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure. FIG. 3 presents a cross-sectional view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure. FIG. 3 presents a cross-sectional view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure. FIG. 3 presents a cross-sectional view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure. FIG. 3 presents a cross-sectional view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure. FIG. 3 presents a cross-sectional view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure. FIG. 3 presents a cross-sectional view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure. FIG. 3 presents a cross-sectional view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure. FIG. 3 presents a bottom view of a die in an exemplary chip package according to an embodiment of the present disclosure. FIG. 3 presents a cross-sectional view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure. FIG. 3 presents a cross-sectional view of a portion of an exemplary integrated assembly according to one embodiment of the present disclosure.

  The following description includes specific information related to embodiments in the present disclosure. The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments. Unless otherwise noted, equivalent or corresponding components in the figures are denoted by the same or corresponding reference numerals. Further, the drawings and descriptions in this application are not generally shown in the correct dimensional ratios and are not intended to correspond to actual relative dimensions.

FIG. 1A shows a circuit diagram of an exemplary power conversion circuit according to an embodiment of the present disclosure. As shown in FIG. 1, the power conversion circuit 100 includes a control integrated circuit (IC) 102 and a power switching stage 104. The power switching stage 104 includes at least one switch such as a high side switch 106a and a low side switch 106b. In power switching stage 104, high side switch 106a and low side switch 106b are coupled between high side voltage _VH and low side voltage _VL , and output node 110 is between high side switch 106a and low side switch 106b.

  The power conversion circuit 100 has a pulse width adjustment (PWM) input signal PWM_In and a switching voltage SW as an output. The control IC 102 receives the PWM input signal PWM_In and an arbitrary switching voltage SW, and provides a high side drive signal HO and a low side drive signal LO, which are gate drive signals, as outputs. The control IC 102 can also be referred to as a drive IC and a gate drive IC. The power switching stage 104 receives the high side drive signal HO and the low side drive signal LO as the input and output switching voltages SW.

  The control IC 102 is configured to generate a high side drive signal HO and a low side drive signal LO based on the PWM input signal PWM_In and an arbitrary switching voltage SW, and the high side switch 106a of the power switching stage 104 using synchronous rectification and Each of the low side switches 106b is driven.

The power switching stage 104 is shown by way of example as a half bridge coupled between a high side voltage V _H and a low side voltage V _L. High-side switch 106a has a drain _{D A} coupled to high-side voltage _{V H,} and the source _{S A} coupled to an output node 110, a gate _{G A} high-side driving signal HO of the high-side switch 106a Configured to receive. Similarly, the low-side switch 106b has a drain _{D B} coupled to the output node 110, a source _{S B} coupled to the low-side voltage _{V L,} has a gate _{G B} of the low-side switch 106b is a low-side driving signal LO Configured to receive.

  In the power conversion circuit 100, each of the high-side switch 106a and the low-side switch 106b (also referred to as power switches 106a and 106b) is a depletion mode (eg, normally-on) III-nitride transistor, particularly a high electron mobility transistor. (HEMT). By including at least one depletion mode III-nitride transistor in the power switching stage 104, the power conversion circuit 100 allows the high breakdown field, high saturation rate, and two-dimensional electron gas (2DEG) provided by the III-nitride material. ) Can be used.

  It is desirable to couple at least one depletion mode III-nitride transistor to a group IV transistor (eg, a silicon transistor). For example, it is desirable for at least one depletion mode III-nitride transistor to act as an enhancement mode device in the power conversion circuit 100. This is accomplished by linking at least one depletion mode III-nitride transistor with a group IV transistor in cascode connection to produce an enhancement mode composite device, such as enhancement mode composite device 106 of FIG. 1B.

Referring to FIG. 1B, FIG. 1B presents an exemplary circuit diagram of a depletion mode III-nitride transistor coupled to a group IV transistor, according to one embodiment of the present disclosure. The enhancement mode composite device 106 includes a composite gate G, a composite source S, and a composite drain D. The enhancement mode composite device 106 may correspond to at least one high side switch 106a and low side switch 106b in FIG. More specifically, in the power conversion circuit 100, one of the enhancement mode composite devices 106 can be used as the high side switch 106a, and the other enhancement composite device 106 can be used as the low side switch 106b. Can do. Thus, an enhancement mode composite device 106, the composite gate G, composite source S, and the combined drain D of the high side power switch 106a, respectively, the gate _{G A,} may correspond to the source _{S A,} and the drain _{D A.} Furthermore, an enhancement mode composite device 106, the composite gate G, composite source S, and the combined drain D of low-side switch 106b, respectively, the gate G _B, may correspond to the source S _B, and the drain D _B.

  Enhancement mode composite device 106 includes a depletion mode III-nitride transistor 112 in cascode connection with a group IV transistor 114. The group IV transistor 114 may be a silicon-based power switching device such as a power metal oxide semiconductor field effect transistor (MOSFET). In this embodiment, the group IV transistor 114 is an enhancement mode transistor, more specifically, an enhancement mode silicon transistor. As shown, group IV transistor 114 includes a diode, which can be formed as a body diode or on a common die with group IV transistor 114. The depletion mode III-nitride transistor 112 may be a III-nitride heterojunction field effect transistor (HFET), more specifically a III-nitride HEMT such as a GaN-based HEMT.

  In enhancement mode composite device 106, drain D2 of group IV transistor 114 is coupled to source S1 of depletion mode III-nitride transistor 112, so that both devices are in blocking mode under reverse voltage conditions. As configured, the IV group transistor 114 can be an LV device and the depletion mode III-nitride transistor 112 can be an HV-device or MV-device. A similar device is disclosed in related US patent application Ser. No. 11 / 372,679 “Hybrid Semiconductor Device” filed Mar. 10, 2006 and patented as patent 8,017,978. Assigned to the assignee). Further, in enhancement mode composite device 106, gate G 1 of depletion mode III-nitride transistor 112 is coupled to source S 2 of group IV transistor 114. Accordingly, the depletion mode III-nitride transistor 112 is off absent at the gate G2 of the group IV transistor 114, and the enhancement mode composite device 106 is a normally off device.

  The depletion mode III-nitride transistor 112 and the group IV transistor 114 are coupled together and can be housed in a common package that can be coupled to a printed circuit board (PCB). However, the common package increases the parasitic inductance and thermal impedance of the enhancement mode composite device 106. These device characteristics are particularly important in high frequency, high current applications, such as when the depletion mode III-nitride transistor 112 and group IV transistor 114 form a power switch. Further, the depletion mode III-nitride transistor 112 and group IV transistor 114 assembly in a common package, and the assembly of the common package on the PCB, can be expensive.

  According to various embodiments of the present disclosure, the depletion mode III-nitride transistor 112 is on a depletion mode III-nitride transistor die located on the PCB, and the group IV transistor 114 is an IV located on the PCB. On the transistor transistor die. Thus, a depletion mode III-nitride transistor can be coupled to a group IV transistor while avoiding increased parasitic inductance, thermal impedance, and assembly cost, while simultaneously forming a high performance composite device such as enhancement mode composite device 106. be able to.

  Referring to FIGS. 2A and 2B, FIG. 2A presents a top view of a portion of an exemplary integrated assembly, according to one embodiment of the present disclosure. FIG. 2B presents a cross-sectional view of a portion of an exemplary integrated assembly, according to one embodiment of the present disclosure. 2B corresponds to the 2B-2B cross section of FIG. 2A. The power conversion circuit 100 of FIG. 1A can be formed in the integrated assembly 200 of FIGS. 2A and 2B.

  Integrated assembly 200 includes control IC 202 and enhancement mode composite device 206, corresponding to control IC 102 and enhancement mode composite device 106 in FIGS. 1A and 1B, respectively. Although only enhancement mode composite device 206 is shown, integrated assembly 200 may include multiple enhancement mode composite devices that may be similar to or different from enhancement mode composite device 206 to form power conversion circuit 100. it can.

  Enhancement mode composite device 206 includes a depletion mode III-nitride transistor die 212 and a group IV transistor die 214, corresponding to depletion mode III-nitride transistor 112 and group IV transistor 114, respectively, in FIG. 1B. Depletion mode III-nitride transistor die 212 and group IV transistor die 214 are each separate devices and are coupled to PCB 230. The depletion mode III-nitride transistor die 212 is disposed on the surface 218a of the PCB 230, and the group IV transistor die 214 is disposed on the surface 218b of the PCB 230 opposite to the surface 218a. In doing so, the overall footprint of the enhancement mode composite device 206 is, for example, to place the depletion mode III-nitride transistor die 212 over the group IV transistor die 214, as shown. By making it possible, it can be reduced.

  PCB 230 includes at least one via, such as vias 220a and 220b extending through PCB 230. The PCB 230 may further include various additional components such as one or more inductors, capacitors, resistors, and / or other enhancement mode composite devices embedded in or on the PCB 230. For example, one or more output capacitors and / or output inductors of the power conversion circuit 100 can be located on or in the PCB 230. Any additional components can be electrically coupled to enhancement mode composite device 206 via conductive traces on PCB 230. Also, although only vias 220a and 220b are shown, PCB 230 can include a variety of other structures within PCB 230, such as different levels of conductive wiring, coupled by vias.

  At least one via, such as vias 220 a and 220 b in PCB 230, electrically couples depletion mode III-nitride transistor die 212 to group IV transistor die 214. As shown, vias 220a and 220b optionally extend completely through PCB 230. Vias 220a and 220b include a conductive material such as copper. Vias 220 a and 220 b are disposed between the depletion mode III-nitride transistor die 212 and the group IV transistor die 214. In doing so, a short coupling is created through the PCB 230 with low parasitic inductance and low resistance. As a specific example, via 220b couples source S1 of depletion mode III-nitride transistor die 212 (shown in FIG. 1B) to drain D2 of group IV transistor die 214 (shown in FIG. 1B). In addition, via 220a couples gate G1 of depletion mode III-nitride transistor die 212 (shown in FIG. 1B) to source S2 of group IV transistor die 214 (shown in FIG. 1B). Other vias electrically couple depletion mode III-nitride transistor die 212, group IV transistor die 214, and / or control IC 202, or a power conversion circuit between planes 218a and 218b of PCB 230. Used for electrical routing of either 100 nodes or terminals.

  Thus, depletion mode III-nitride transistor die 212 is coupled to group IV transistor die 214, when coupling the depletion mode III-nitride transistor and group IV transistor in a common package to the PCB. Avoid the increased parasitic inductance, thermal impedance, and assembly cost that can occur. In addition, a circuit including a depletion mode III-nitride transistor and a group IV transistor can be formed on the PCB. In the illustrated embodiment, the circuit is a power conversion circuit 100 formed on a PCB 230, which is connected to the PCB 230 with a depletion mode III-nitride transistor die 212 and a group IV transistor die 214. including. More specifically, the depletion mode III-nitride transistor die 212 is coupled with a group IV transistor die 214 utilizing PCB 230 in a cascode connection to provide a high performance power switch within the power conversion circuit 100.

As shown in FIGS. 2A and 2B, enhancement mode composite device 206 corresponds, by way of example, to high side switch 106a in FIG. 1A. Accordingly, the high-side voltage V _H (ie, the input voltage V _H ), the switching voltage SW (ie, the output voltage SW), and the high-side drive signal HO (ie, the gate drive signal HO) are connected to the respective wirings 216a, 216b on the PCB 230 and It is shown to be at 216c. The wirings 216a, 216b, and 216c include a conductive material such as copper. The wiring in the various embodiments disclosed herein can also be located on or on the top surface of the PCB and / or embedded within the PCB. Note that although the control IC 202 is shown disposed on the surface 218a of the PCB 230, the control IC 202 can alternatively be disposed on the surface 218b of the PCB 230. Also, the PCB 230 can include various other wirings and / or vias to form the power conversion circuit 100 of FIG. 1A.

  3A, 3B, 3C, 3D, 3E, 3F, and 3G illustrate a cross-sectional view of a portion of an exemplary integrated assembly, according to various embodiments of the present disclosure. 3A, 3B, 3C, 3D, 3E, 3F, and 3G show integrated assemblies 300a, 300b, 300c, 300d, 300e, 300f, and 300g, corresponding to integrated assembly 200 of FIGS. 2A and 2B. 3A, 3B, 3C, 3D, 3E, 3F, and 3G, surfaces 318a and 318b, depletion mode III-nitride transistor die 312, group IV transistor die 314, PCB 330, and vias 320a and 320b are shown in FIG. 2A, respectively. And 2B, corresponding to faces 218a and 218b, depletion mode III-nitride transistor die 212, group IV transistor die 214, PCB 230, and vias 220a and 220b.

  FIGS. 3A, 3B and 3C show that at least one of group IV transistor die 314 and depletion mode III-nitride transistor die 312 is encapsulated on PCB 330. In FIG. 3A, at least the depletion mode III-nitride transistor die 312 is encapsulated on the surface 318 a of the PCB 330. The integrated assembly 300a includes a sealant 340a, which is utilized to at least seal the depletion mode III-nitride transistor die 312 on the PCB 330. An example of the sealant 340a is a crop top sealant such as various resins including an epoxy resin. Sealant 340a can protect depletion mode III-nitride transistor die 312 from moisture, chemicals and contaminants. Furthermore, the sealant 340a can compensate for thermal mismatch between the depletion mode III-nitride transistor die 312 and the PCB 330 while providing mechanical support and electrical insulation.

  In FIG. 3B, at least the group IV transistor die 314 is sealed on the PCB 330. The integrated assembly 300b includes an encapsulant 340b, which is utilized to at least encapsulate the group IV transistor die 340b on the surface 318b of the PCB 330. An example of the sealant 340b is a crop top sealant such as epoxy. Sealant 340b can protect group IV transistor die 314 from moisture, chemicals and contaminants. Further, the sealant 340b can compensate for thermal mismatch between the group IV transistor die 314 and the PCB 330 while providing mechanical support and electrical insulation.

  In FIG. 3C, at least the group IV transistor die 314 and the depletion mode III-nitride transistor die 312 are encapsulated on the PCB 330. The integrated assembly 300c includes a sealant 340a and a sealant 340b. Encapsulant 340a is utilized to encapsulate at least the depletion mode III-nitride transistor die 312 on surface 318a of PCB 330, and encapsulant 340b is at least group IV on surface 318b of PCB 330. Used to seal the transistor die 314. The sealant 340b may include a material that is the same as or different from the material of the sealant 340a. Utilizing different materials for encapsulant 340a and encapsulant 340b means that group IV transistor die 314 and depletion mode III-nitride transistor die 312 may have different semiconductor materials (eg, silicon and GaN, respectively) having different thermal profiles. ) Is advantageous. FIGS. 3A, 3B and 3C show an embodiment in which the group IV transistor die 314 is directly below the depletion mode III-nitride transistor die 312 and is not offset from the depletion mode III-nitride transistor die 312. . However, FIG. 3D shows an embodiment in which the group IV transistor die 314 is just below the depletion mode III-nitride transistor die 312 but is offset. Thus, there is an overlap between the group IV transistor die 314 and the depletion mode III-nitride transistor die 312. On the other hand, FIGS. 3E, 3F and 3G show that the group IV transistor die 314 does not overlap the depletion mode III-nitride transistor die 312 and the group IV transistor die 314 does not overlap the depletion mode III-nitride transistor die 312. An embodiment is shown that deviates from the depletion mode III-nitride transistor die 312 without overlapping the depletion mode III-nitride transistor die 312 rather than just below.

  Also, as shown in FIGS. 3E, 3F, and 3G, at least one bond wire can be utilized to couple the depletion mode III-nitride transistor die 312 to the group IV transistor die 314. At least one bond wire can be optionally sealed as shown. Referring to FIG. 3E, the integrated assembly 300e includes at least one bond wire, such as bond wires 324a and 324b, that electrically couple the depletion mode III-nitride transistor die 312 to the PCB 330. More specifically, bond wire 324 a electrically couples depletion mode III-nitride transistor die 312 to wiring 322 a on PCB 330. Bond wire 324b also electrically couples depletion mode III-nitride transistor die 312 to wiring 322b on PCB 330, as shown. Further, wiring 322b on PCB 330 is electrically coupled to via 320a as shown.

  Referring to FIG. 3F, integrated assembly 300f includes at least one bond wire, such as bond wires 324c and 324d, that electrically couple group IV transistor die 314 to PCB 330. Referring to FIG. More specifically, bond wire 324 d electrically couples group IV transistor die 314 to wiring 322 d on PCB 330. The bond wire 324c electrically couples the group IV transistor die 314 to the wiring 322c on the PCB 330, as shown. Further, wiring 322c on PCB 330 is electrically coupled to via 320a as shown.

  Referring to FIG. 3G, integrated assembly 300g includes at least one bond wire, such as bond wires 324c and 324d, that electrically couple group IV transistor die 314 to PCB 330. Referring to FIG. Integrated assembly 300g also includes at least one bond wire, such as bond wires 324a and 324b, that electrically couple depletion mode III-nitride transistor die 312 to PCB 330. The bond wire 324 a electrically couples the depletion mode III-nitride transistor die 312 to the wiring 322 a on the PCB 330. Bond wire 324b electrically couples depletion mode III-nitride transistor die 312 to wiring 322b on PCB 330, as shown. Wiring 322b on PCB 330 is electrically coupled to via 320a as shown. Bond wire 324 d also electrically couples group IV transistor die 314 to wiring 322 d on PCB 330. The bond wire 324 c electrically couples the group IV transistor die 314 to the wiring 322 c on the PCB 330 as shown. Wiring 322c on PCB 330 is electrically coupled to via 320a as shown.

  Thus, in some embodiments, at least one bond wire is utilized to couple the depletion mode III-nitride transistor die 312 to the group IV transistor die 314. Thus, it should be understood that any of source S1, drain D1, and gate G1 of FIG. 1B is provided on either the top or bottom surface of depletion mode III-nitride transistor die 312. In addition, any of the source S2, the drain D2, and the gate G2 in FIG. 1B is provided on either the upper surface or the lower surface of the group IV transistor die 314. Further, any one of the composite source S, the composite drain D, and the composite gate G of FIG. 1B is provided on either the surface 318a or the surface 318b of the PCB 330.

  Referring to FIG. 4, FIG. 4 presents a cross-sectional view of a portion of an exemplary integrated assembly, according to one embodiment of the present disclosure. In FIG. 4, the integration assembly 400 corresponds to the integration assembly 200 in FIGS. 2A and 2B. Thus, the power conversion circuit 100 can be formed with an integrated assembly 400 that includes the control IC 102. Integrated assembly 400 includes surfaces 218a and 218b, depletion mode III-nitride transistor die corresponding to surfaces 218a and 218b, depletion mode III-nitride transistor die 212, group IV transistor die 214, and PCB 230 of FIGS. 2A and 2B. 412, group IV transistor die 414, and PCB 430.

  In integrated assembly 400, depletion mode III-nitride transistor die 412 and group IV transistor 414 are coupled to PCB 430. Also, the depletion mode III-nitride transistor die 412 and the group IV transistor die 414 are disposed on the same surface of the PCB 430. The same surface is shown as surface 418a, but may alternatively be surface 418b. In PCB 430, at least one wire, such as wire 422, electrically couples depletion mode III-nitride transistor die 412 to group IV transistor die 414. Like other wires described herein, wire 422 includes a conductive material such as copper. Since the depletion mode III-nitride transistor die 412 and group IV transistor die 414 are arranged side by side on the PCB 430, the interconnect 422 and others that connect the depletion mode III-nitride transistor die 412 and group IV transistor die 414 Any of the wires, conductive clips, bond wires, and / or other coupling means can be made small with low parasitic inductance and low resistance.

  Depletion mode III-nitride transistor die 412 and / or group IV transistor die 414 can optionally be encapsulated on PCB 430. For example, FIG. 4 shows sealant 440a and sealant 440b corresponding to sealant 340a and sealant 340b, respectively, described above. Alternatively, the depletion mode III-nitride transistor die 412 and the group IV transistor die 414 may be sealed with a common sealant. The common sealant can include the control IC 102 and / or other components of the power conversion circuit 100.

  Referring now to FIG. 5, FIG. 5 presents a cross-sectional view of a portion of an exemplary integrated assembly, according to one embodiment of the present disclosure. In FIG. 5, the power conversion circuit 100 can be formed of an integrated assembly 500 that includes a control IC 102. The integrated assembly 500 includes the surfaces 218a and 218b of FIGS. 2A and 2B, and the surfaces 518a and 518b corresponding to the PCB 230, and the PCB 530.

  FIG. 5 shows enhancement mode composite devices 506a and 506b on PCB 530. FIG. The enhancement mode composite device 506a may correspond to the high side switch 106a of FIG. 1A, and the enhancement mode composite device 506b may correspond to the low side switch 106b of FIG. 1A. Wiring 522 and / or other coupling means electrically couples hunting mode composite devices 506a and 506b, thereby forming power switching stage 104 of FIG. 1A. The power switching stage 104 of FIG. 1A includes two power switches (enhancement mode composite devices 506a and 506b). However, the power switching stage 104 generally includes at least one power switch. Each power switch may be configured similarly to that described herein. In particular, each power switch can include similar components coupled to the same PCB in a similar manner. By doing so, the power switch can form one or more half bridges. Thus, the power conversion circuit 100 can take a variety of forms, and the power conversion circuit 100 can be a synchronous buck converter, a two-phase power converter, a three-phase power converter, and other types of power including at least a power switch. It can be a buck converter such as a conversion circuit.

  The enhancement mode composite devices 506a and 506b can be configured in the same manner as the enhancement mode composite device described above, and thus detailed description thereof is omitted. Enhancement mode composite device 506a includes a depletion mode III-nitride transistor die 512a and a group IV transistor die 514a. Enhancement mode composite device 506b includes a depletion mode III-nitride transistor die 512b and a group IV transistor die 514b. The depletion mode III-nitride transistor dies 512a and 512b are optionally encapsulated with a common encapsulant as illustrated as encapsulant 540a. Similarly, group IV transistor dies 514a and 514b are optionally sealed with a common sealant as shown as sealant 540b. Moreover, the sealing agent 540a and the sealing agent 540b can seal other components of the power conversion circuit 100. Further, any of the depletion mode III-nitride transistor dies 512a and 512b and the group IV transistor dies 514a and 514b may be sealed separately.

  The depletion mode III-nitride transistor die and group IV transistor die described herein can be exposed dies, or any die can be included in a chip scale package, flip chip package, or other chip package. Can be. Examples of chip packages include a DirectFET® package, a quad-flat no-leads (QFN) package, and a leadless package. An exemplary chip package is described in further detail below.

  Referring to FIGS. 6A and 6B, FIG. 6A presents a bottom view of a die in an exemplary chip package, according to one embodiment of the present disclosure. FIG. 6B presents a cross-sectional view of a portion of an example integrated assembly including an example chip package, according to one embodiment of the present disclosure. The cross-sectional view of FIG. 6B corresponds to the chip package along the 6B-6B cross section of FIG. 6A.

  FIG. 6A shows a chip package 642 that includes a die 644, which corresponds to either a depletion mode III-nitride transistor die or a group IV transistor die as described herein. Accordingly, FIG. 6B shows an integration assembly 600, which corresponds to any of the various integration assemblies described herein. All the electrodes of the chip package 642 can be arbitrarily formed on the surface 646 of the chip package 642. Chip package 642 includes a plurality of elongated digits configured for external circuit coupling through solder bars. More specifically, the chip package 642 includes an extended source digit 650 interspersed with extended drain digits 652. Chip package 642 further includes an extended gate digit 654. Each extended source digit 650, extended drain digit 652, and extended gate digit 654 are configured for electrical circuit coupling via respective solder bars 660, as shown in FIGS. 6A and 6B.

  In a specific embodiment, die 644 includes a passivation layer 662 and each plurality of elongated digits is a solderable contact that is exposed through an opening in the passivation layer 662. Multiple extension digits are thereby soldered to solder bars 660 on PCB 630. Related U.S. Patent Application No. 13 / 018,780, filed February 1, 2011 and patented as Patent No. 8,399,912 “III-Nitride Power Device Having Solderable Front Metal with Source and Drain Solder Bars” ( (Assigned to the assignee of the present application) shows a chip package that can be similar to the chip package 642. It should be noted that in other embodiments, the solderable contacts can have different configurations in addition to or instead of the extended digits shown. Further, any number of contacts can be provided on either side of the chip package 642 for electrical coupling to any of the various ends of the chip package 642.

  FIG. 6B further illustrates that any of the dies described herein can optionally include an underfill disposed between the die and the PCB. For example, in integrated assembly 600, underfill 664 is disposed between die 664 and PCB 630. Underfill 664 can protect the solderable contacts of chip package 642 from moisture, chemicals, and contaminants. Further, the underfill 664 can compensate for thermal mismatch between the die 644 and the PCB 630 while providing mechanical support and electrical insulation. Examples of underfill 664 include a variety of resins including epoxy resins. In some embodiments, the chip package 642 is sealed as described for FIGS. 3A, 3B, 3C, 3D, 3E, 3F, and 3G.

  Referring to FIG. 7, FIG. 7 illustrates a cross-sectional view of a portion of an exemplary integrated assembly, according to one embodiment of the present disclosure. FIG. 7 shows an integration assembly 700 corresponding to the integration assembly 600 of FIG. 6B. Integrated assembly 700 includes chip package 742, die 744, PCB 730, and underfill 764, corresponding to chip package 642, die 644, PCB 630, and underfill 664 of FIGS. 6A and 6B, respectively. The example underfill 664 can include a variety of resins including epoxy resins. In some embodiments, the chip package 742 is sealed as described with respect to FIGS. 3A, 3B, 3C, 3D, 3E, 3F, and 3G.

  In contrast to chip package 642, chip package 742 is configured to flip chip bond to PCB 730 by utilizing solder bumps 770 to electrically bond to die 744. Related US patent application Ser. No. 09 / 780,080 “Vertical conduction flip-chip device with bump contacts on single surface” filed on Feb. 9, 2001 and patented as US Pat. No. 6,653,740. Shows a package that can be similar to the chip package 742.

  Similar to chip package 642, any number of contacts of chip package 742 can be provided on either side of chip package 742 and electrically coupled to any of the various ends of chip package 742. . Chip packages 642 and 742 are two possible approaches for the depletion mode III-nitride transistor die and group IV transistor die described above. However, other approaches are possible and may be combined.

  In some embodiments, bond wires are utilized to bond one or more contacts to the opposite sides of chip packages 642 and 742, similar to those described above. Also, in some embodiments, one or more conductive clips can be utilized to couple to one or more contacts on the opposite sides of chip packages 642 and 742. For example, the conductive clip may be configured to connect a drain provided on the opposite side of the group IV transistor die or depletion mode III-nitride transistor die to the printed circuit board. The source and the gate may be provided on a surface opposite to the opposite surface. Related US patent application Ser. No. 09/817774 “Chip scale surface mounted device and process of manufacture” filed Mar. 28, 2001 and patented as patent 6,624,522, assigned to the assignee of the present application. Indicates a chip package (for example, a DirectFET (registered trademark) package) that can be similar to the above-described chip package.

  Accordingly, as described above with respect to FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 3C, 3D, 3E, 3F, 3G, 4, 5, 6A, 6B, and 7, embodiments of the present disclosure provide an integrated assembly. In an integrated assembly, a depletion mode III-nitride transistor die and a group IV transistor die are coupled to a printed circuit board and coupled together by the printed circuit board. In so doing, embodiments of the present invention provide parasitic inductance, resistance, thermal impedance, and cost associated with housing a depletion mode III-nitride transistor die and group IV transistor die in a common package. Can be avoided. Thus, circuits such as power conversion circuits can be formed in an integrated assembly while achieving improved performance at reduced cost.

  From the above description, it is apparent that the concepts described in the present application can be realized without departing from the scope of these concepts using various techniques. Further, although these concepts have been described with specific reference to particular embodiments, it is understood by those skilled in the art that changes in form and detail may be made without departing from the scope of these concepts. Is the place that admits. As such, the described embodiments are illustrative in all respects and not limiting. It is also apparent that the present application is not limited to the specific embodiments described herein, and that numerous reconfigurations, modifications, and alternatives are possible without departing from the scope of the invention.

Claims (20)

A printed circuit board;
A depletion mode III-nitride transistor die and a group IV transistor die coupled to the printed circuit board;
The depletion mode III-nitride transistor die is disposed on one side of the printed circuit board, and the group IV transistor die is disposed on the opposite side of the printed circuit board;
The integrated assembly further comprising at least one via in the printed circuit board for electrically coupling the depletion mode III-nitride transistor die to the group IV transistor die.   The integrated assembly of claim 1 wherein the depletion mode III-nitride transistor die is cascode connected to the group IV transistor die.   The integrated assembly of claim 1 wherein the depletion mode III-nitride transistor die is disposed over the group IV transistor die.   The integrated assembly of claim 1, wherein the group IV transistor die is immediately below the depletion mode III-nitride transistor die and is not offset from the depletion mode III-nitride transistor die.   The integrated assembly of claim 1 wherein the group IV transistor die is offset from the depletion mode III-nitride transistor die.   The integrated assembly of claim 1, wherein the III-nitride transistor die comprises a plurality of elongated digits configured for external circuit coupling through solder bars.   The integrated assembly of claim 1, wherein the group IV transistor die comprises a passivation layer and solderable contacts that are exposed through openings in the passivation layer.   The integrated assembly of claim 1, wherein the III-nitride transistor die comprises a passivation layer and solderable contacts exposed through openings in the passivation layer.   The integrated assembly of claim 1, further comprising a conductive clip connecting a drain of the group IV transistor die to the printed circuit board.   The integrated assembly of claim 1, wherein the group IV transistor die and the depletion mode III-nitride transistor die form an enhancement mode composite device.   The integrated assembly of claim 1, wherein the group IV transistor die comprises an enhancement mode transistor.   The integrated assembly of claim 1, wherein at least one of the group IV transistor die and the III-nitride transistor die is encapsulated on the printed circuit board.   The integrated assembly of claim 1, wherein the III-nitride transistor die comprises a high electron mobility transistor. A printed circuit board;
A depletion mode III-nitride transistor die and a group IV transistor die coupled to the printed circuit board,
The depletion mode III-nitride transistor die and the group IV transistor die are disposed on the same side of the printed circuit board;
The integrated assembly further comprising at least one interconnect on the printed circuit board that electrically couples the depletion mode III-nitride transistor die to the group IV transistor die.   15. The integrated assembly of claim 14 wherein the depletion mode III-nitride transistor die is cascode connected with the group IV transistor die.   The integrated assembly of claim 14 wherein the depletion mode III-nitride transistor die is in a chip scale package.   The integrated assembly of claim 14, wherein the group IV transistor die is in a chip scale package. A printed circuit board;
A power conversion circuit formed on the printed circuit board comprising a depletion mode III-nitride transistor die and a group IV transistor die coupled to the printed circuit board; and
An integrated assembly wherein the depletion mode III-nitride transistor die is coupled with the group IV transistor die by a cascode connection by the printed circuit board.   The integrated assembly of claim 18, wherein the power conversion circuit further comprises a control IC disposed on the printed circuit board.   19. The integrated of claim 18, wherein the depletion mode III-nitride transistor die is disposed on one side of the printed circuit board and the group IV transistor die is disposed on the opposite side of the printed circuit board. assembly.